JP2001273192A - Digital system having microprocessor and method for operating the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To properly cope with the case of erroneously address-designating a device which does not exist in the address space of a system in a digital system having various kinds of memories and devices. SOLUTION: In a digital system having a microprocessor 100, a cache 120 and the various kinds of memories and devices (140a to 140n), a physical address attribute memory(PAAM) 130 generates a signal for controlling a cash memory mode of a fixed map. When, plural devices exist in the address space of the digital system having different functions and characteristics, in response to an attribute bit in the PAAM related with the memory mapped address of the device, an error is reported or using of each device is restricted to prevent its misuse.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates generally to a digital system having a microprocessor and a method of operating the digital system, and more particularly to a digital system having a cache memory circuit and operating the digital system. On how to make it.

A microprocessor is a general purpose processor that can achieve high instruction throughput to execute running software and can have a wide range of processing requirements according to the particular software application involved. Different polymorphic processors are known. For example, a digital signal processor (DS
P) is widely used for certain applications, such as mobile phone processing applications. DSPs are typically built to optimize the performance of the applications involved, and to achieve this they employ more specialized execution units and instruction sets.

In order to reduce instruction and / or data memory access time and obtain high instruction throughput,
A cache memory is provided. In computer systems that use cache memory, certain cache memory modes need to be controlled. Caches in common microprocessor systems
Signals for controlling the memory are often input from a memory management unit. However, in embedded systems, such as those employing digital signal processors, there is often no memory management unit.

[0004] In addition, the various memory mapped peripherals that may be provided in a particular embedded system may not all have the same access capabilities.

Generally, in the form of the present invention, a digital system comprises a microprocessor, cache and various memories, and a plurality of devices. A signal controlling a certain cache memory mode is a physical address attribute memory (physical address a).
tribute memory (PAAM). When there are multiple devices in the address space of a digital system having different functions and characteristics, an error is signaled in response to an attribute bit in the PAAM associated with the memory-mapped address of the device,
Otherwise, restricting the use of each device prevents its misuse. In addition, there may be a memory management unit with address translation and / or memory protection features, but this is not required for PAAM operation.

A specific embodiment according to the present invention will now be described, by way of example only, with reference to the accompanying drawings, in which: In these figures, the same reference numerals are used to refer to the same parts unless otherwise indicated.

[0007] Corresponding numbers and symbols in different drawings and tables refer to corresponding parts unless otherwise indicated.

The invention finds application, for example, to a digital signal processor (DSP) implemented in an application specific integrated circuit (ASIC), but also finds application to other types of processors. The ASIC may include one or more megacells that include custom-designed functional circuits combined with pre-designed functional circuits provided by a design library with each other.

FIG. 1 is a block diagram of a digital system including one embodiment of the present invention. Figure 1 for clarity
Shows only portions of a microprocessor (DSP) 100 that are relevant to understanding one embodiment of the present invention. DSP1
Details of the general structure of 00 are well known and can easily be found elsewhere. For example, Boto (Fre
U.S. Pat. No. 5,072,418 issued to Derick Boutaud et al. describes a DSP in detail. Gary Swobod
a) US Patent No. 5,329,4 issued to others
No. 71 describes in detail how to test and emulate a DSP. To enable those of ordinary skill in the microprocessor to make and use the present invention,
The details of the multiple parts of the DSP 100 relating to one embodiment of the present invention are described in sufficient detail below.

Referring to FIG. The DSP 100 includes a circuit for an instruction execution pipeline. The instruction and execution pipeline includes memory and device circuits 140a to 140a.
Address generation circuits are provided for forming addresses on the address bus 102 for accessing data and instructions from 0n. Further, the memory and device circuits 140a to 140a to
140n also includes memory mapped registers and interfaces to various physical devices such as timers, serial ports, parallel ports, and the like. A memory management unit (MMU) 110 is connected via an address bus 102 to a DSP address generator. MMU
110 translates the logical address on address bus 102 into a physical address and translates it to physical address bus 112.
To supply. Logical addressing provides fixed reference frames for instructions and data that are not directly connected to the actual physical memory connected to DSP 100. Those skilled in the art are advised to use MM for address translation.
Now that we know the general operation of the U unit,
The operation of MMU 110 will not be further described. For the purposes of the present invention, the MMU 110 is optionally present. In fact, most DPS systems use MM
It does not currently have a memory management unit such as U110. When there is no MMU 110, the address generation circuit of the DSP 100 generates a physical address instead of a logical address, and the physical address bus 112 is directly connected to the address bus 102 of the DSP 100.

Still referring to FIG.
A memory 120 is connected to the physical address bus 112 to provide requested instructions and / or data to the DSP 100 faster than the memory and device circuits 140a-140n. Bus 122 represents both an address bus connected to the cache, and a data bus that supplies access instructions and / or data to the central processing unit (CPU) of DSP 100. Those skilled in the art are familiar with cache circuits, and thus will not describe the operation of cache memory 120 in detail here. In addition, a physical address attribute (PAAM) 130 is connected to the physical address bus 112 and is a physical address arbitrarily provided to the cache 120 and the DSP 100, and may be used in an on-chip or off-chip Used to describe the capabilities of the ware. The underlying hardware is random in memory semantics
For access memory (RAM), the cache is
There are many degrees of freedom to access that location. The lower layer hardware is, for example, a serial port receiving F.
In the case of an FIFO buffer, semantics are very different from RAM, and the cache must be careful not to mask the volatile operation of the FIFO.

[0012] PAAM 130 is typically only considered on cache misses. The nature of the address that triggers a cache miss is connected to the cache by a cacheable attribute signal 132 generated by PAAM 130. Cache 120 selects a detectable cache behavior for that device type performed at the physical address that triggered the cache miss in response to the cacheable attribute signal. The action signal 134 is
It is also provided to various memory and device circuits 140a-140n to inform the bus interface of information to make better use of the addressed device.

Several assumptions can be made for an embedded system, such as the system of FIG. 1, typical of a DSP system. For example, as described above, an MMU may be present, but often not required and not present. The physical address space is occupied by various devices such as RAM, read only memory (ROM), and input / output (I / O), timers and the like. Program access to ROMs and various devices is not uncommon. In the cache in the embedded system, the physical address for backing up the location is determined by the presence or absence of the MMU.
It is necessary to act rationally based on M or device. Once the embedded system is designed and built, the configuration and address assignments of RAM, ROM and devices are hardly changed unless the address mapping is also programmable. In general, it is important to pay attention to empty memory space addresses so that they do not lead to system delays, except that erroneous accesses to empty memory space addresses are promptly reported as errors and properly handled. That is what. Errors are signaled in several ways, for example, by a bus transaction completion status or by an interrupt. When notified, the processor responds with a vector to the interrupt, depending on the environment, or by setting an error status.

Many different operating systems (OSs) have been employed with various embedded systems, including commercially available, self-made and bare hardware. Conveniently, using a physical address attribute map,
The reliability of operation of a digital system with any of these operating systems can be improved.

FIG. 2A shows the physical address attribute map 130 of the system of FIG.
FIG. 2 is a block diagram implemented by a sociative mapping. Associative mapping relies on finding attribute associations based on address range comparisons. A physical address is compared to several address ranges, and a match provides the attributes of the address. The comparison block 210 determines whether the PAAM
At 130 represents any number of comparison blocks 210a-210n that can be verified. Comparison block 21
0a, the upper limit register 220 and the lower limit register 22
There is one. Comparator 222 compares the contents of upper limit register 220 with the physical address provided from address bus 112 and asserts an output signal if the physical address is less than or equal to the upper limit. Similarly, comparator 223 asserts an output signal if the physical address is equal to or greater than the contents of lower limit register 221. A
The ND gate 224 receives two signals from the two comparators and is connected to enable the attribute register 225 so that when the input physical address has a value between the lower limit and the upper limit, Only the cacheable attribute signal 132 and the attribute signal 134 are driven. The upper limit register 220, the lower limit register 221, and the attribute registers associated with each other are configured to be readable and writable by the DSP 100 as memory-mapped registers. For example, in other embodiments, some or all of these registers may be RO
M or electrically rewritable programmable ROM
(EEPROM).

Thus, a set of registers is recognized in the address space associated with the memory subsystem. When accessing each of the memory subsystems, the PAA
M monitors the address of each memory request to the memory subsystem to detect which of a set of registers is accessed and provides an attribute signal associated with the area. The cache operates in the first mode when detecting an access in the first memory area in response to an attribute signal supplied from the PAAM. When the cache detects an access in the second memory area, it operates in the second mode. Similarly, when the cache detects an access in a particular memory area in response to an attribute signal supplied from the PAAM, the cache operates in the first mode, and the memory subsystem operates in a different memory area. When the access is detected, it operates in the second mode. If a particular area is accessed, such as an empty area, PAAM asserts a control signal when this area is detected,
Notify P100 and perform appropriate operation.

[0017] Associative mapping has several features that should be recommended as follows. That is, the complexity can be easily set by increasing or decreasing the number of comparison registers. Can be easily adjusted to support different physical address sizes. It also supports large address areas with a variable range, including very small or large areas. In addition, associative mapping has some disadvantages, such as: That is, it can occur when one or more limit registers are incorrectly set and the above address ranges match the provided physical addresses. PAAM
May not have a sufficient number of address range comparison blocks for a particular instance of the system. Each compare block is relatively expensive in terms of transistor count and the resulting integrated circuit (IC) die size, and fully aligned associatively address mapped PAAM is unacceptable for embedded system applications. Can be something.

FIG. 2B is a block diagram of another embodiment in which the physical address attribute map 130 of the system of FIG. 1 is implemented by direct mapping. Direct mapping uses a portion of the physical address as an index into the attribute table. If the table is large enough to map all physical addresses, then there is no need for associative comparisons. In FIG. 2B, table 250
Is connected to the physical address bus 112 via the decoder 251.
Has a large number of entries that can be selected by decoding a part of. In this embodiment, address bus 112 is a 32-bit bus. Each entry in the table 250 is a 4-byte entry, 16M
B represents a total of 4 gigabytes of physical address space of fixed size. Each entry represents a 24-bit address range, so that only the eight most significant address bits need to be decoded by decode circuit 251. In order to completely cover eight address bits, 256 entries are required. Each entry is arranged so that it can be read as one memory-mapped item. Therefore, PAA
The entire M table 250 occupies an address space of 1024 bytes. The base address of the PAAM table megacell can be instantiated at various locations in various embedded systems and is ordered by its size (1024 bytes). Each entry is further subdivided into 16 sub-areas each representing a 1 MB physical address space. The path setting circuit 252 converts the information stored in each table entry into the cacheable attribute signal 13.
2. Enable routing to the attribute signal 134 or both. In another embodiment, these attribute signals are not separated.

The direct mapping is based on the number of transistors and I
There is an advantage that the cost can be reduced in terms of the C area. This does not bother with multiple matches and, if completely filled, will always cover the entire physical memory address space. However, direct memory has some disadvantages in that the complexity of the direct mapped mechanism is in fixed overhead that cannot be easily scaled. It is not easy to support small region sizes without excessive number of table entries.

In many embedding system implementations, P
Most of the contents of the AAM table are constant because they correspond to addresses for on-chip resources or addresses that no device can have due to bus limitations. In many cases, only the physical address that can address a device on an external bus needs to have a programmable register. Therefore, a part of the table 250 is implemented by the ROM. Alternatively, a portion may be implemented, for example, by an EEPROM.

FIG. 3 illustrates a set of physical address attributes for each entry in the physical address attribute map of FIGS. 2A and 2B. The area of the physical address space is specified by a 32-bit PAAM entry. These bits are divided into several groups, as described below, namely, copy management, access specifiers, and secondary area free flags.

The four attribute specifier bits are included in a copy management group, and as shown in Table 1, control the operation of a caching mechanism that enables a plurality of copies of data in the area to be created. Defined. These specify what caching is feasible or necessary, depending on certain circumstances, when accessing data from this area.

[0023]

[Table 1]

FIG. 3 shows a synchronous store (Synchrono).
us Store: SS). This is used in implementation systems that support out-of-order memory operations. The SS bits are stored in this area in a strict order. 1
The store for an address with SS of is a synchronous store. The DSP pipeline must not perform any other load or store operations until this store has completed on the device. An SS of 1 is significant only when IW is 1 or PC is 0. PC is 1 and IW
Is 0, the operation of the chip is undefined and may change from implementation to implementation. If SS is 1, IW is 1, and WA is 1, and writing to an area causes a write assignment, such a situation may occur. In this case, the operation is defined to perform a cache restore and a cache line read if necessary before performing a synchronous write to the device and cache (or caches).

The access specifier group indicates whether the device supports a read operation and / or a write operation, as defined in Table 2.

[0026]

[Table 2]

The sub-region empty flags e15 to e0 indicate empty sub-regions. Each region is divided into 16 and each is controlled by one of the flags. When the sub area flag is 0, the area specifiers NR, NW, SS, P
S, IW, WA and PC control the sub-area. When the sub area flag is 1, the sub area is designated by the designated specifier PA.
AM_EMPTY (NR and NW are 1 and everything else is 0)

The reserved bits r5 and r8 to r15 are reserved and must be read as 0 in this embodiment. Writes to these bits must be ignored. Other embodiments may define these bits for various functions.

Table 3 shows a set of definitions that can be used to program the programmable entries in PAAM in the embedded system initialization program. By using definitions 9-16, programs can be written that will take appropriate action on the most common devices in the system. For example, definition 9 is stored in each PAAM table entry corresponding to an address area that is not implemented. Definition 14 is stored in each PAAM table entry corresponding to a memory area implemented as ROM. Other entries in the PAAM are loaded appropriately according to the characteristics of the associated address area.

The PAAM needs to be in the region coded as PAM_DEV, definition 15. This is S
To set S, changes to the PAAM entry are immediately recognized by the next DSP load or store operation. When changing the PAAM, it is often necessary to flush the associated cache. For example, PAAM_PC is cleared as follows:
Change area entry when setting PAAM_IW when setting _PC in an entry, setting PAAM_NW or PAAM_NR when setting PAAM_PC in an entry, or setting PAAM_PS when setting PAAM_PC in an entry It is necessary to flush the cache of the address in the area included in.

[0031]

[Table 3]

The IW and WA specifiers have an interaction.
Table 4 shows the behavior of a fully functional cache system for these two. It should be noted that various system implementations may ignore WA in some or all environments.

[0033]

[Table 4]

When a 16 MB area of memory contains some type of device, the PAAM entry must be set to a function compatible with all devices in that area. Usually, this means that it will only be set when all devices in the area can be cached. NR and NW are set only when applied to all devices in the region. IW
Need to be set as needed by the devices in that area.

In another embodiment of the present invention, there is a great deal of freedom in selecting the designated PAAM for implementation. This choice involves balancing the functionality and flexibility of programmable PAAM with the cost of implementing the entire mechanism. The system implementation has two methods: (1) constant entry method, (2)
The method of implementing only a certain number of bits per register can reduce the chip area used.

(1) Many parts of many physical address spaces do not require programmable PAAM registers,
It may be implemented by certain entries. Most of the physical address space may not have any devices.
In addition, the physical address space that maps to on-chip devices may not require programmable registers, or may require only certain bits to be programmable. For example, on-chip RAM
Would need only the PS bit. Typically,
To be fully programmable (for the implemented range), when designing an IC or megamodule that includes a PAAM, it should be provided with an external bus that may be built to include unknown devices It is.

(2) Only a few designator bits can be implemented. The chip needs to implement a PC when it has a cache. In addition, other copy management bits can be implemented. When supporting memory sharing, PS can be implemented. To support sharing,
Can perform cache snooping. When the cache can use these values, WA and IW can be implemented. The chip needs to implement NR and NW when supporting error detection, but can omit these if not. A chip that can obtain sufficient synchronization of input / output device writing without performing SS may be omitted. SS must be performed when the chip performs out-of-order memory operations that prevent reliable device operation due to multiple control registers. Portions of the map that have programmable registers need to set or read the bits to be implemented by writing. Bits that are not implemented must always be read as 0. Implementations that have a cache system that always performs write allocations or writebacks may have a PAAM return constant of 1 in these bit positions. However, PAAM is not expected to return different values based on cache configuration or content. In the implementation, it is possible to select not to implement the sub-region empty flag. In this case, all 16 bits are read as 0 and ignored in writing. These implementations use the specifier in the given entry for all sub-regions associated with that entry.

In another embodiment, a direct mapped table may include a portion of an address, and one or more associatively mapped compare blocks may include other portions of another address space.

In another embodiment, each compare block of the various associatively mapped embodiments may compare all bits of the physical address, or a limited number of the most significant bits of the physical address, resulting in a coarse address range. it can.

In other embodiments, implementing PS may require a programmable register for on-chip memory that may be shared, and in some embodiments, the PS bit from PAAM may be To determine the sharing status of the data in the cache in combination with information from the processor and / or information from the MMU, such as the operation codes used,
May be used.

FIG. 4 is a block diagram of the digital system 400, showing a dual first level cache 41.
0, 420 and a single second level cache 430, and includes embodiments of the present invention. Central processing unit (CPU)
401 is described in further detail below. The first level cache 410 stores one in cache memory 410a.
The direct mapped program cache 410 having a capacity of 6 Kbytes and the L1 program (L1P) controller 410b are connected to the instruction fetch stage of the CPU 401. 16K in cache memory 420a
A two-way associative data cache 420 having a byte capacity and a level 1 data (L1D) controller 420b are connected to the data units D1 and D2 of the CPU 401. A Level 2 (L2) cache memory 430 having four banks of memory (128 Kbytes total) is connected to L1P 410 and L1D 420 via buses 412 and 422, respectively, to provide memory for data and programs. Level 1 instruction cache (L1P) 410 stores instructions used by central processing unit core 401. The central processing unit core 401 first has the level 1 instruction cache 410
Try to access some instruction from. Level 1 data cache (L1D) 420 stores data used by central processing unit core 401.
Two level 1 caches are supported by a level 2 unified cache (L2) 430. Level 1 instruction cache 410 or level 1 data cache 420
In the case of a cache miss, the requested instruction or data is searched from the level 2 unified cache 430.
The requested instruction or data is stored in the level 2 unified cache (L
2) If stored in 430, it is supplied to the requesting level 1 cache and transferred to the central processing unit core 401. As known in the art,
The requested instruction or data may be provided simultaneously to both the requesting cache and the central processing unit core 401 for high speed use.

External memory interface (EMI
F) 450 provides a 64-bit data path to external memory (not shown), which passes memory data through an extended direct memory access (DMA) controller 440 to a level 2 cache. Memory 4
30. Extended DMA controller 440 is connected to receive all read and write requests from L2 cache 430 via physical address / data bus 431. The details of the operation of the extended DMA controller are not important to the present invention. Detail is,
A data bus using a synchronous standby loop including a read address and data bus and a write address and data bus (Data Bus Using Synchronous Latency Lo)
op Including Read Address And Data Busses And Writ
e Address And Data Busses)
(TI-26021), and a hub interface unit and an application unit interface for an extended direct memory access processor (Hub Interface Unit And Applicatrion Unit)
Interface For Expanded Direct Memory Access Proces
US Patent Application No. (TI-2)
8979).

The EMIF 452 provides a 16-bit interface for accessing an external peripheral device (not shown). The expansion bus 470 supports a host and input / output.

The three multi-channel buffer serial ports (McBSP) 460, 462, 464 are connected to a DMA controller 440. A detailed description of McBSP can be found in US patent application Ser. No. 09 / 055,011 (TI
-26204, Seshan et al.). The emulation circuit 50 accesses the internal operation of the integrated circuit 1 that can be controlled by the external test / development system (XDS) 51.

The CPU 401 further has an instruction fetch, an instruction dispatch and an instruction code pipeline, a dual data path 1 and a data path 2. Data path 1 includes an arithmetic and load / store unit D1, a multiplier M1, an ALU / shifter S1, an arithmetic logic unit (AL
U) L1, having a plurality of execution units including a shared multiport register file A for reading data and writing data. The decoded instructions are passed from the instruction fetch / decode pipeline via various control line sets (not shown) to functional units D1, M
1, S1 and L1. Data is stored in registers
From the file to / to the load / store unit D1 via a first set of buses, a multiplier M1 via a second set of buses.
ALU / shifter unit S via the third set of buses
1 and to the ALU L1 via the fourth set of buses. It should be noted that data is supplied to / from load / store units D1 to / from cache memory 420 via a fourth set of buses. The entire data path described above is duplicated by the data path 2 having the register file B and the execution units D2, M2, S2 and L2. Instructions are fetched from a set of bus instruction cache memories 410 by an instruction fetch unit. The size and configuration of the various caches are not significant to the present invention. They are,
This is a matter of design choice. Further, the particular choice and number of execution units is a matter of design choice and is not critical to the present invention. A description of the various architectural configurations of the microprocessor 400 of FIG.
croprocessor with Improved Instruction Set Archtec
No. 09/70 by the same applicant entitled
3,096 (TI-30302).
A description of the basic set of instructions for microprocessor 400 is further described in commonly-assigned application Ser. No. 09 / 012,81 entitled Improved Microprocessor.
No. 3 (TI-25311).

External test system 404 represents various known test systems for debugging and emulating integrated circuits. One such system is a processor state sensing circuit, system and method (Pro
cessor Condition Sensing Circuits, System, and Met
hods) is described in U.S. Pat. No. 5,535,331. The test circuit 403 includes a control register and a parallel signature analysis circuit for testing the integrated circuit 400.

According to a feature of the present invention, PAAM480
Are connected to the physical address bus 431. The cacheable attribute signal 482 indicates that the cacheable information is L
2 cache 430.
The attribute signal 484 is connected to attribute information on a physical memory and a device connected to the extended DMA controller 440.

FIG. 5 is a block diagram of the digital system of FIG. 4, showing various data transfers between various caches, memories, and devices to better describe the operation of PAAM 480. Digital signal processor system 400 includes a number of cache memories, as described with reference to FIG. The complex interrelationships of the parts of digital signal processor system 400 allow for the movement of large numbers of data. These are shown schematically in FIG. 5 and are described below. First, the level one program cache 410 can receive instructions recalled from the level two unified memory 430 for the cache miss fill 501. In this example, level 1
To prevent the instructions stored in the program cache 410 from being modified, a self-modifying code
There is no hardware support for de).
There are two possible data moves between the level 1 data cache 420 and the level 2 unified memory 430.
The first of these data moves is the level 2 unified memory 430
From the cache miss fill 502 to the level 1 data cache 420. The data is further 503
The data is transferred from the level 1 data cache 420 to the level 2 unified memory 430 as shown in FIG. This movement of data may include writing to the level 1 data cache 420 to be serviced by the level 2 unified memory 430, victim eviction from the level 1 data cache 420 to the level 2 unified memory 430,
Raised by a snoop response from level 1 data cache 420 to level 2 unified memory 430. The data can be moved between the level 2 unified memory 430 and the external memory 160, as shown at 504 and 505. This is because the external memory stores the level 2 integrated memory 430
Cache miss to service or external memory 560
2 integrated memory 43 configured as SRAM
With direct memory access 440 data movement to 0,
And a sacrificial eviction from the level 2 unified memory 430 to the external memory 560, or a direct memory access 440 data transfer from a part of the level 2 unified memory 430 configured as an SRAM to the external memory 560. Finally, data can move between the level 2 unified memory 430 and the peripheral device 570, as shown at 506 and 507. These movements may be due to L2 read or write misses, or peripheral 570 and SRAM
Occurs by direct memory access 440 data movement of level 2 unified memory 430 configured as a memory, or by direct memory access 440 data movement from a portion of level 2 unified memory 430 configured as an SRAM to peripheral device 570. . All data movement between the level 2 unified memory 430 and the external memory 560 and between the level 2 unified memory 430 and the peripheral device 570 uses the data transfer bus 543, and the direct memory access 4
40. These direct memory access data movements may occur as a result of commands from the central processing unit core 401 or from other signal processor systems received via the transfer request bus 541.

The number and variation of possible data movements within digital signal processor 400 creates problems that make coherence maintenance difficult. In any cache system, data coherence is a problem.
Cache systems need to control data access so that each returns recent data. For example, in a single-level cache, a read after write to the same memory address held in the cache will need to return new write data. This coherence needs to be maintained independent of processing in the cache. This coherence preserves the transparency of the cache system. That is, the programmer need not be concerned with data movement in the cache and can be programmed with or without a cache system. This transparency characteristic means that the data processor has no cache or has a variable amount of cache.
The correct execution of programs written for members of the processor family. The cache hardware needs to maintain the illusion of a single memory space programmer. For example, the Hazard Directive example is simply a cache
Read entry. Another example of a non-write-allocated cache is reading from a cache entry after a write miss to an address that has new write data in a write buffer waiting to be written to main memory. Cache systems need to include hardware to detect and handle such special cases.

As with the system described above in connection with FIG. 5, a cache system that includes a second level cache introduces additional hazards. Coherence needs to be maintained between levels in the cache, no matter where the recently written data is located. In general, level 1 caches accessing data have the most recent data, while level 2 caches may have stale data. When an access is made to a level 2 cache, the cache system needs to determine whether a new copy of the data is stored by the level 1 cache. Generally, this will trigger a snoop cycle to poll the level 1 cache for newer data before the level 2 cache responds to its access. Snooping is generally similar to normal access to a snooped cache, except that it is given a higher priority. Snoops are given higher priority because the other level cache is stalled waiting for a response to the snoop. If the data stored in the lower level cache has changed because of the last write to the higher level cache, that data is provided to the higher level cache.
This is called a snoop hit. When the data stored in the low-level cache has been cleaned, and thus has not changed, for the last write to the low-level cache, this is recorded in the snoop response, but the data does not move . In this case, the high-level cache can store a valid copy of the data and supply this data.

The two-level cache increases the special case where a hazard exists. Additional hazards from the two-level cache include snooping on the low-level cache, where the corresponding data is the victim of eviction, and write misses on the low-level cache for non-writing allocation systems that place data in the write buffer. And a snoop for the data input. Still other hazards are possible. The details of coherence management are irrelevant to the present invention, and the multilevel cache system coherence between memory selectively configured as a cache or direct access memory and direct memory access.
th Memory Selectively Configured As Cache Or Direc
t Access Memory And Direct Memory Access) is described in detail in commonly assigned U.S. patent application Ser. No. 09 / 603,637 (TI-29344).

PAAM 480 operates similarly to PAAM 130. However, the operation of a multi-level cache relies on careful provision of region specifiers in a cache system. For example, PC
Must always be able to accept requests. None of the caches 410, 420, and 430 can contain a copy from an address marked by the PC as having an area of 0. Similarly, all caches are IW
Need to accept. In order to make the level 1 cache aware of the attribute entries, a copy of the level 1 cache controller 410a / 420a is provided via bus 412/422 when a miss occurs in the level 1 cache.

For some bits, the cache
It is convenient to keep a copy of these bits in the cache so that the cache tag can be examined for each hit. Remote PAAM 551 in level 2 cache 430 is connected to receive and store cache attribute signal 482 in response to each entry stored in cache data storage memory 540. PAAM 551 is associated with cache tag storage 550 so that attribute bits for each valid entry in level 2 cache 430 are available without having to generate a physical address on physical address bus 431a. .

Another feature of this embodiment of the invention is that a defined 2PAA that needs to be known at the time of a cache miss
M bits are present. These two bits are
The WA (write allocation) bit and the SS (synchronous store) bit. When only these two bits are present, the remote PAAM 556
20 and connected to a physical address bus 412a, which is connected to provide an address for the request to the level 2 cache 430. The CPU core 401 has a data unit D
2x32 bit address provided by 1 and D2
Note that it has a bus. A cache miss in response to either address bus results in a request on the physical address bus 412b resulting in a remote PA.
Monitored by AM 556. Remote PAAM556
The remote PAAM 556 has no direct association with the cache tag storage 555 because the reason for supplying is to trade with a cache miss. Since each value is fixed for a given chip design, they are implemented in a small ROM as a direct mapped table. The PAAM attribute bits in the remote PAAM 556 are PAA for each same address range.
Care must be taken to ensure that the attribute bits in M480 match. In this embodiment, there is no hardware supporting the self-modifying code so as not to modify the instructions stored in the level one instruction cache 410. Therefore, the remote PAAM is
Not required for P410.

However, in another embodiment that supports self-modifying codes, the remote PA in L1P
AM is advantageous according to the configuration. For example, WA and S
S is only needed when a store can originate from its cache. The self-modifying code typically contains a program cache that invalidates or replaces the write instruction, and
Proceed with a data side write that snoops the associated buffer. In this configuration, the WA and SS bits are still needed for the data cache, not the program cache.

In this embodiment, PAAM480
Connected to physical address bus 431a. The cacheability attribute signal 482 is connected to the L2 cache 430 and provides cacheability information. The attribute signal 484 is connected to the transfer request circuit 541 and
Physical memory 5 connected to MA controller 440
Provides attribute information for the device 60 and the device 570. In other embodiments, nothing connects the PAAM 480 to the physical device.

In another embodiment, good design modularity is obtained by maintaining a complete copy of the PAAM at each device. The processor needs to cache or auto-configure information from the device for the WA and SS bits to preserve this modularity.

Referring now to FIG.
A more detailed description of the data transfer is provided to explain the further configuration of 480. The level 1 instruction cache interface provides a 256 bit data transfer from the level 2 unified memory 430 to the level 1 instruction cache L1P 410.
Include path. The size of this data path corresponds to half the size of the 64-byte cache entry in level one instruction cache 410, and one instruction fetch
Equal to packet. In the preferred embodiment, the 256 bits are 64 bits from each of the four banks of level 2 unified memory 430. Thus, level two unified memory 430 can provide this amount of data within a single cycle. This occurs regardless of the amount of the Level 2 unified cache 430 configured as a cache.
Level 2 unified memory 430 may be constructed to include a variable amount of static random access memory (SRAM) instead of cache memory. The construction of the digital signal processor system consists of a cache and an addressable static random access memory.
Integrated memory system architecture including memory (U
nified Memory System Archtecture Including Cache A
No. 09 / 603,645 entitled nd Addressable Static Random Access Memory (TI-29).
343) is described in further detail. Cache / SRA Partitioning in Level 2 Unified Memory 430
M spans the data bank rather than within the data bank. Therefore, the level 2 unified memory 430
Always has 25 in the level 1 instruction cache 410 when any part is partitioned as a cache.
Six bits can be supplied. The level one instruction cache 410 can also receive data directly from the data transfer bus 543, for example, when fetching code from an address in non-cacheable memory. Data transfer bus 543 provides only 64 bits per cycle, thus requiring at least 4 cycles to accumulate 256 bits. Level 1 instruction cache 41
The data source for transferring to 0 is the multiplexer 531
Is selected by FIG. 5 shows a level 1 instruction cache 4
32 addresses from 10 to the level 2 unified memory 430
Indicates the supply of bits. Because the level one instruction cache 410 operates on 256 bit boundaries, the eight least significant bits are always zero and may be excluded from the address. Writes to the level 1 instruction cache 410 are not allowed, so the level 1 instruction cache 410
It should be noted that data is never provided to unified memory 430.

The level 1 data cache interface includes a 128-bit data path from level 2 unified memory 430 to level 1 data cache 420. In the preferred embodiment, 128 bits are 2
6 from each of the bank's level 2 unified memories 430
4 bits. This assumes no bank contention with other data transfers. Level two unified memory 430 services only one cache fill data transfer per cycle to level one data cache 420. Thus, when two load / store units in central processing unit 401 each request data and cause a read cache miss in level one data cache 420, two read miss requests to level two unified memory 430 Serviced by a sequence. As mentioned above, the cache / SRAM partitions of the level 2 unified memory 430 span memory banks. Thus, as long as level 2 unified memory 430 is partitioned to include some cache, level 2 unified memory 430 can supply data to level 1 data cache 420 from two banks. Level 1 data cache 420 further includes:
For example, when fetching data from an address of a non-cacheable memory, the data can be received directly from the data transfer bus 543. Data transfer bus 543 provides only 64 bits per cycle. However, accesses to non-cacheable memory addresses are at most 64 bits. In this case, 64 bits are transferred in a single data transfer cycle. The data source to transfer to level 1 data cache 420 is selected by multiplexer 433. FIG.
Addresses from the level 1 data cache 420
The supply of two sets of 32 address bits to the level two unified memory 430 via bus 422a and address bus 423a is shown. Level 1 instruction cache 420 is 25
Since it operates on a 6-bit boundary, the 6 least significant bits are always zero and may be excluded from the address.

Level 1 data cache 420 can provide data to level 2 unified memory 430. This is caused by a write miss, cache entry eviction, and a snoop hit response to the data in the modified state within the level 1 data cache 420. Each load / store unit in the central processing unit 10 can request a data transfer from the level 1 data cache 420 to the level 2 unified memory 430 in the same cycle. Due to a write miss in level 1 data cache 420, only 32 bits of write data are provided from level 1 data cache 420 to L2 unified memory 430. For cache eviction or snoop data response, level 1 data cache 420 provides 128 bits to level 2 unified memory 430 with the same data width as the reverse transfer. Data from level one data cache 420 may also be provided to data transfer bus 543 as selected by multiplexer 537. This can occur as a result of a write to a non-cacheable address.

The interface between level 2 unified memory 430 and data transfer bus 543 includes 2 × 64 bit data buses 431b and 431c. data·
The bus 431b supplies data from the data transfer bus 543 to the level 2 integrated memory 430. This data is combined into a single 64 as selected by multiplexer 535.
Level 2 unified memory 43 via the bit write portion
0 may be stored. Data bus 431c is connected to level 2 unified memory 430 or level 1 data cache 420 as selected by multiplexer 535.
Is a 64-bit bus that supplies data from All transfers using data transfer bus 543 utilize memory access unit 150 directly in response to a command via transfer request bus 541.

The physical address bus 431a is connected to the data
Two physical address portions are provided to enable parallel transfer on buses 431b and 431c. In this embodiment of the invention, PAAM 480 is dual ported so that both physical address portions present on physical address bus 431a can be monitored by PAAM 480.

Some examples of systems that can benefit from the configuration of the present invention are described in US Pat. No. 5,072,418;
In particular, reference is made to FIGS. 2 to 18 of U.S. Pat. No. 5,072,418. U.S. Pat. No. 5,072,41 using a microprocessor in conjunction with the present invention to improve performance and reduce costs.
The system described in No. 8 can be further improved. Such a system is not limiting,
Industrial process control, automotive systems, motor control,
Includes robot control systems, satellite communication systems, echo cancellation systems, modems, video imaging systems, speed recognition systems, encrypted vocoder modem systems, and the like.

FIG. 6 shows an integrated circuit 40 including a digital system 400 in a mobile telecommunications device such as a radiotelephone having an integrated keyboard 12 and display 4.
1 illustrates an example implementation of As shown in FIG. 6, a digital system 400 having a processor 401 comprises:
It is used for a display 14 via a keyboard adapter (not shown) and to a keyboard 12 used for radio frequency (RF) circuitry 16 via a keyboard adapter (not shown).

The fabrication of the digital system 400 includes a multiple step of implanting various amounts of impurities into the semiconductor substrate and diffusing the impurities to a selected depth in the substrate. A mask is formed to control the arrangement of the impurities. Multiple layers of conductive and insulating materials are deposited and etched to interconnect various devices. These steps are performed in a clean room environment.

A significant part of the cost of fabricating a data processing device involves testing. In wafer formation, individual devices are biased to an operational state and probe tested for basic operational functions. The wafer is then split into individual dies that can be sold as bare dies or packages. After packaging, the semi-finished product is biased to an operational state and tested for operational functionality.

An integrated circuit including any of the above embodiments includes a plurality of contacts for surface mounting. However, the integrated circuit may include other configurations, such as a plurality of pins on the underside of the circuit mounted in a zero insertion force socket, indeed any other suitable configuration.

The digital system 400 includes hardware extensions for advanced debugging functions. These are useful for developing application systems. Since these capabilities are part of the core of the CPU 401 itself, they are only available for the JTAG interface with the extended operation mode extension. They are simple and inexpensive, do not require costly cabling, require speed-independent access to cores for complex debugging and economical system development, and require traditional emulator systems. Processor that implements or introduces system resources
Provides access to pins.

Thus, the digital system is provided with a physical address attribute map, whether or not an address translation map is provided. Conveniently, PAA
M provides a signal that controls certain cache miss modes.

Conveniently, for devices residing in the address space of a digital system having different capabilities and features, errors may be reported in response to attribute bits in the PAAM associated with the device's memory-mapped address. By notifying or restricting the use of each device, misuse is prevented.

Advantageously, the capabilities specified by a PAAM entry are declarative rather than mandatory. That is, the attribute bits declare the capabilities of each device, rather than giving a cache directive on its behavior.

Advantageously, PAAM does not require a memory management unit or operating system control. Entries in PAAM are RO at chip design time for many types of systems, including systems on chip.
M can be set with reliability.

Advantageously, PAAM is related to cacheability, write-through, sharing, readability, writeability, and I / O.

Advantageously, many programming
The error can be reported by detecting an access to an address having no device, for example.

Conveniently, PAAM is a device
Provides organized behavior control of I / O memory to make programming access easier.

Conveniently, the PS is
When used in combination with other information based on code or MMU status, very precise sharing control is possible. Thus, the coherence performance and power cost can be carefully controlled for use in mere memory operations that exist for truly shared data.

As used herein, the terms “applied,” “connected,” and “connection” include electrical, including the possibility that additional elements may be present in the electrical connection path. Means to be connected. "Associated" means a control relationship such as a memory resource controlled by an associated port. The terms assert, assert,
No assert, no assert, negate, and negation are used to avoid confusion when processing a combination of active high and active low signals. Assert, and assert is used to indicate that the signal has been activated. No-assert, no-assert, negate, and negation are used to indicate that the signal has been inactive.

While the invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various other embodiments of the invention will be apparent to those skilled in the art from this description. For example, different numbers and sizes of caches may be implemented. The remote part of the PAAM can also be embedded in various peripheral devices. Different sizes and configurations of physical address and data buses may be provided. A microprocessor system that cooperates requests from other DSPs with the transfer request circuit 541 and the data transfer bus 543 can also be configured.

It is therefore intended that the appended claims cover any such modifications of the embodiments as fall within the true scope and spirit of the invention.

The following items are further disclosed with respect to the above description.

(1) In a digital system having a microprocessor, the microprocessor includes:
Central processing unit (CP) connected to the address generation unit
U), a cache connected to said address generation unit via a first address bus, and a memory circuit connected to said cache via a data bus, said memory circuit being connected via a second address bus. The memory circuit connected to receive an address from the address generation unit, and at least a first memory mapped device connected to the second address bus.
Said first memory mapped at a first address;
A mapped device and a physical address attribute map (PAAM) connected to the second address bus, the PAAM being connected to the cache via at least a first attribute control signal; The PA
An AM is operable to assert the first attribute control signal in response to the first address present on the address bus, wherein the signals controlling certain cache memory modes are different. A digital system provided to devices residing in an address space of the digital system having capabilities and characteristics.

(2) The memory circuit further includes a second attribute control signal for connecting the PAAM to the memory circuit, wherein the PAAM is responsive to a second address present on a second address bus. The digital system of claim 1, operable to assert an attribute control signal.

(3) The digital device according to (1), further comprising a memory management unit having an address translation capability connected to the address generation unit and having an output for providing the first address bus. ·system.

(4) The first address bus and the second address bus
4. The digital system according to claim 3, wherein said address buses are the same bus.

(5) The PAAM includes at least a first attribute storage circuit for supplying the first attribute control signal and at least a first pair of comparison circuits respectively connected to receive the second address bus. Operable to enable the first attribute storage circuit only when an address delivered to the second address bus has a value between a low value and a high value. The digital system according to claim 1, further comprising a first comparator.

(6) The PAAM further comprises a plurality of attribute storage circuits and a plurality of pairs of comparators, wherein each of the plurality of attribute storage circuits has only one of the pair of comparators for enabling. 6. The digital system of claim 5, wherein the digital system is connected to one of:

(7) The PAAM comprises a direct mapped multiword storage circuit, wherein the strobe circuit supplies the first attribute control signal in response to the PAAM responding to the most significant address bits of the set. 2. The digital system of claim 1, wherein said digital system is connected to receive a set of most significant bits of said second address bus so as to be operable.

(8) The attribute control signal represents a shared memory, and the cache is operable to maintain data coherence, and the second address
When the first attribute control signal indicates that the data item is not shared in response to the address of the data item on the bus, the cache may The digital system of claim 1 responsive to said first attribute signal so as to preserve coherence.

(9) An integrated keyboard connected to the processor via a keyboard adapter, a display connected to the processor via a display adapter, and a radio frequency (RF) circuit connected to the processor. The digital system of claim 5, further comprising a cellular telephone further comprising an antenna connected to said RF circuit.

(10) Cache memory and memory
A method of operating a digital system comprising a microprocessor having a subsystem, the method comprising: identifying a plurality of regions in an address space associated with the memory subsystem; Detecting which of the plurality of areas is being accessed by monitoring addresses; and operating the cache in a first mode in response to detecting an access in a first memory area. Operating the cache in a second mode in response to detecting an access in a second memory area.

11. The method of claim 10, wherein said step of identifying includes identifying one or more regions having a smaller size than other regions.

(12) The method according to the above (10), wherein the microprocessor is notified of a response for detecting an access in the third memory area in response to the detection.

(13) In response to detecting an access in the third memory area, operating the memory subsystem in the first mode, and in response to detecting an access in the fourth memory area. 11. The method of claim 10, further comprising operating the memory subsystem in a second mode.

(14) Microprocessor (100)
, A cache (120), and various memories and devices (140a-140n). Physical address attribute memory (PAAM)
(130) generates a signal for controlling the map-constant cache memory mode. When a device resides in the address space of a digital system with different capabilities and characteristics, the memory mapped
In response to an attribute bit in the PAAM related to an address, an error is notified or use of each device is restricted, thereby preventing misuse. Further, the P
A memory management unit (110) having an address translation capability and / or a memory protection function may be provided without requiring the operation of the AAM.

This application is based on the provisional application No. 60 / 183,527 filed on Feb. 18, 2000 (TI-30).
302PS), and 35 USC §119e of Preliminary Application No. 60 / 183,418 (TI-29846PS).
Claim priority based on (1).

[Brief description of the drawings]

FIG. 1 is a block diagram of a digital system having a single cache and including an embodiment of the present invention.

FIG. 2A is a block diagram in which a physical address attribute map of the system in FIG. 1 is implemented by direct mapping; B
FIG. 4 is a block diagram of another embodiment in which the physical address attribute map of the system in FIG. 1 is implemented by direct mapping.

FIG. 3 is a diagram showing a physical address attribute set for a physical address belonging map of FIGS. 2A and 2B.

FIG. 4 is a block diagram of a digital system having a dual first level cache and a single second level cache and including one embodiment of the present invention.

FIG. 5 is a block diagram of the digital system of FIG. 4 illustrating data transfer between various caches, memories and devices.

FIG. 6 illustrates a radiotelephone digital system including the DSP of FIG.

[Explanation of symbols]

Reference Signs List 100 Microprocessor (DSP) 110 Memory management unit (MMU) 112 Physical address bus 120 Cache memory 122 Bus 130, 480, 551, 556 Physical address attribute map (PAAM) 140a-140n Memory and device circuit 410 Level 1 instruction cache 420 Level 1 data cache 430 Level 2 unified memory 440 Direct memory access

Claims (2)

[Claims] 1. In a digital system having a microprocessor, the microprocessor includes a central processing unit (CP) connected to an address generation unit.
U), a cache connected to the address generation unit via a first address bus, and a memory circuit connected to the cache via a data bus, the memory circuit being connected via a second address bus. The memory circuit connected to receive an address from the address generating unit, and at least a first circuit connected to the second address bus.
The first memory-mapped device mapped by a first address, and a physical address attribute map (PAAM) connected to the second address bus. The PAAM connected to the cache via at least a first attribute control signal, the PAAM being responsive to the first address present on the address bus. A digital system operable to assert a signal, the signal controlling a certain cache memory mode being provided to devices residing in an address space of the digital system having different capabilities and characteristics. 2. A method of operating a digital system with a microprocessor having a cache memory and a memory subsystem, comprising: identifying a plurality of regions in an address space associated with the memory subsystem. Detecting which of the plurality of areas is being accessed by monitoring the address of each memory request to the memory subsystem; and responding to detecting an access in the first memory area. Operating the cache in a first mode
Operating the cache in a second mode in response to detecting an access in a second memory area.