JP2001273190A - Method for recording variable length data in sdram recorder - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for recording to SDRAMs variable length data which is supplied consecutively by a large quantity like a radar video. SOLUTION: A [11,10] on the side of MSB compared with A [9...0] of a COLUMN address are assigned to an address bit for SDRAM block selection, and when the selection of one ROW address in an SDRAM block #1 is finished, a ROW address in an SDRAM block #2 is selected automatically. By adopting this constitution, an active command ACTV is issued to the next ROW address just before recording in one ROW address is finished. When the recording area of the former ROW address becomes full, data can be recorded in the next address continuously. Since data can be recorded across the ROW addresses, a large-amount of consecutive variable length data can be recorded without omission.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an SDRAM (Synchronous Dynamic Random Accesor) for storing data of variable length, such as radar video supplied from a radar device.
s Memory).

[0002]

2. Description of the Related Art An SDRAM is a synchronous DRAM (Dynamimu) that inputs and outputs stored information in synchronization with a clock supplied from an external circuit such as a logical operation circuit (CPU).
c Random Access Memory). The operation of an SDRAM is basically the same as that of a DRAM. SDRAM
The biggest difference between the operation of the DRAM and the operation of the DRAM is that S
In a DRAM, input and output of data and commands are all performed in synchronization with the rise of a clock. In the SDRAM, continuous data input / output can be performed in synchronization with a clock in a burst mode.

In the SDRAM, access to a memory for writing and reading is performed by specifying an address using a ROW address and a COLUMN address. Working SDR
In AM, the ROW address is 409 from 0 to 4095.
There are many six. Also, each ROW address has multiple COLs
Consists of a UMN address. In the current SDRAM,
In many cases, each ROW address consists of 512 COLUMN addresses from 0 to 511 or 1024 COLUMN addresses from 0 to 1023. As will be described later, many memory spaces in an SDRAM chip are divided into a plurality of (for example, four) banks and each bank is provided with a ROW address and a COLUMN address.

[0004] Typical commands in the SDRAM include an active command (ACTV) and a read command (REAM).
D), write command (WRITE), precharge command (PR
E), a burst stop command (BST) and a refresh command (REF). In these command names, uppercase letters written in parentheses () are symbols.
This is an abbreviation of each command called "." Hereinafter, the active command is referred to as an active command ACTV, and other commands are similarly described. However, in the drawings described later, each command is simply represented by its abbreviated notation due to the limitation of the description range, and the write command WRITE is further shortened by the symbol WR
It is written in. The functions of these commands are as follows.

The active command ACTV is a command for designating a ROW address and making the designated ROW address active. By executing the write command WRITE or the read command READ specifying the ROW address only when the ROW address is in the active state, writing or reading to or from each COLUMN address can be performed. The read command READ is a command for reading the selected COLUMN address, and requires a certain time to execute. This fixed time varies depending on the SDRAM, but the time from issuance of the read command READ to execution is, for example, two clock times. The write command WRITE is
This is a command for writing to the OLUMN address, and writing starts when this command is executed. The precharge command PRE is a command for inactivating a ROW address. In order to execute the active command ACTV at a certain ROW address, it is necessary to execute a precharge command PRE to the ROW address before the execution.

The burst stop command BST is a command for stopping the functions of the write command WRITE and the read command READ in the full page burst mode.
During the execution of the write command WRITE, data up to one clock before the burst stop command BST is written, and during the execution of the read command READ, after the input of the burst stop command BST, after the predetermined time (two clock times in the above example). Reading is performed. Refresh command
REF is a command for refreshing (rewriting) a ROW address. Normal refresh is for a certain period (for example,
64ms). For example, 4
In an SDRAM having 096 ROW addresses, it is necessary to execute the refresh command REF 4096 times in order to refresh the entire SDRAM.

[0007] SDRAM access methods include single access, two block access, four block access,
There are five types, eight block access and full page burst access. Single access, two block access, four block access and eight block access can be applied only when the number of data is fixed. The access method can be set by the mode command only when the power is turned on (POWER ON). If the access method is set to one of the above at the time of power-on, once the power is turned off (POWER O
FF), and the access method cannot be changed until the power is turned on again. When 2-block access is selected,
The two-block access operation is continued until the next power ON / OFF.

In single access, data is written and read for one COLUMN address. In 2-block access, data is written and read for 2COLUMN addresses. The same applies to 4-block access and 8-block access. The full page burst access is a mode in which the write operation is continued from execution of the write command WRITE to execution of the burst stop command BST. However, in full page burst access,
Only the COLUMN counter is incremented by one every clock,
The ROW counter is not incremented. Therefore, in the full page burst access mode, one write command WRITE
The maximum data length (that is, the number of data) that can be written by executing is one row address, and two R
Data cannot be recorded continuously over the OW address.

In SDRAM, one active command ACT
The memory area that can be written or read by issuing V is in the range of one ROW address. Therefore, usually 512
Alternatively, in order to store data exceeding the range of 1024 bytes (or words) of one ROW address in the SDRAM, an active command ACTV and a write command WRITE are issued to one ROW address (this ROW address is RW0), and
When data has been recorded in all COLUMNs of the ROW address RW0, a burst stop command BST and a precharge command PRE are issued to the ROW address RW0, and then an active command ACTV and a write command WRITE are issued to the next ROW address RW1. Then, data recording to the ROW address RW1 is started. When the ROW address to be recorded changes from RW0 to RW1, recording is temporarily stopped.

In a computer, data is transferred between a memory (main memory) made of SDRAM and a hard disk. When recording data from the hard disk to SDRAM in this transfer, data transfer is performed under the control of the CPU. Therefore, once data for one ROW address is recorded in SDRAM, it is necessary to suspend data transfer once. There is no problem in the transfer.

FIG. 8 shows an SD for collecting data by a conventional method.
FIG. 9 is a diagram schematically showing a data recording method in the device of FIG. 8, FIG. 10A is a diagram showing a configuration of an SDRAM block # 1 in the SDRAM recording device of FIG. 8, FIG. 10B is a conceptual diagram showing a data recording mode in FIG. 10A, and FIG. 11 is an SDRAM block # in FIG. 10A.
FIG. 2 is a diagram illustrating a circuit for recording data in the first embodiment;

The memory space of the SDRAM chip J1 is shown in FIG.
As shown in the figure, the bank is divided into BANKs (abbreviated as BK in the figure) B0, B1, B2 and B3. Each bank is 4096
It consists of ROW. Each row has 1024 COLUMN
(Column, abbreviated as CLM in the figure.) SDRAM
Chips J2, J3 and J4 have the same configuration as SDRAM chip J1. Since each SDRAM chip has 1024 * 4096 * 4 COLUMNs as conceptually shown in FIG. 10B, 24 bits are required as address bits. The data width of each SDRAM chip is 8 bits.

As shown in FIG. 11, the SDRAM block (BLOCK) comprises four SDRAM chips connected in parallel,
It has a data width of 8 * 4 = 32 bits. In FIG.
A represents an address, and the following [] shows the bit configuration of the address. A [23 ... 0] indicates address bits 0 to 23. D represents data, and the following [] indicates the bit configuration of the data. D [7 ... 0] indicates data bits 0 to 7. In this specification and the accompanying drawings, according to custom, the inside of [] is represented in the order from the MSB side to the LSB side, such as A [23 ... 0]. The notation method of address bits and data bits is the same in FIG. 8 and FIG. 1 described later. SDRAM with the circuit configuration of Fig. 11
In block # 1, data is composed of 32 bits from data bits 0 to 31. Therefore, the data handled by the SDRAM block # 1 is 32 bits, and the required address bits are 24 bits. SDRAM blocks # 2 to # 4 are also SDRA
It has the same configuration as M block # 1.

The SDRAM recording apparatus shown in FIG. 8 has a space of 1024 * 4096 * 4 and can record 32-bit width data.
4 blocks are connected in parallel, and 32-bit data is 1024
COLUMN * 4096ROW * 4BANK * 4 This is a device that can store data in 4 BLOCK memory cells. In this SDRAM recording device, 26 address bits from 0 to 25 are required as a whole. 24 address bits A [23 ... 0] from the 0th to the 23rd are necessary for selecting a memory cell in each SDRAM block. Of the 24 address bits A [23 ... 0] from the 0th to the 23rd, the 10th bit A [9 ... 0] from the 0th to the 9th represent the COLUMN address, and the 12th bit A from the 10th to the 21st. [21… 10] is ROW
Represents the address and the two bits A [23, 2
2] represents a BANK address.

An address bit A [25, 24] consisting of the 24th bit and the 25th bit indicates a block address and is necessary for designating any one of the SDRAM blocks # 1 to # 4. is there.

The SDRAM recording apparatus shown in FIG. 8 is connected to an SDRAM controller (not shown) through address lines and control lines (not shown). The SDRAM controller supplies an address and a command to the SDRAM recording device via an address line and a control line, respectively. Address bit A [23 ...
0] is supplied from the SDRAM controller on the address line 3, and address bits A [25, 24] are supplied from the SDRAM controller on the address line 4.
Supplied from the controller. The address line 3 is composed of 23 pairs of signal lines, and the address line 4 is composed of two pairs of signal lines.

When a large amount of data is recorded in the SDRAM recording apparatus of FIG.
ROW0 at 0 is selected by the active command ACTV and C
Recording is started from OLUMN0, and when data is recorded up to COLUMN 1023 of ROW0, recording is temporarily interrupted and the SDRAM block #
ROW1 in BANK0 of 1 is selected by the ACTV command, recording is similarly started from COLUMN0, recorded to COLUMN 1023 of ROW1, and the ROW address is sequentially increased to 2,3,4,. Reaches 4095, ROW addresses 0 to 4095 are similarly recorded for BANK1, and BANK1 is also recorded.
Record up to 3. Thus, data was recorded on the entire SDRAM block # 1. Up to this point, address bit A [25, 2
4] is 0, 0 (the 25th and 24th address bit values are 0
And 0), and the SDRAM block # 1 is selected.

Next, A [25, 24] is set to 0, 1 (the 25th and 24th address bit values are 0 and 1, respectively), the SDRAM block # 2 is selected, and data is recorded in the entire SDRAM block # 2. I do. Subsequently, A [25, 24] is set to 1, 0 (the 25th and 24th address bit values are 1 and 0, respectively), and the SDRAM block # 3
And record the data in the entire SDRAM block # 3,
Further, A [25, 24] is set to 1, 1 (the 25th and 24th address bit values are 1 and 1, respectively), and the SDRAM block # 4 is selected.
Data is recorded in the entire SDRAM block # 4.

According to the above-described procedure, data is recorded in the entire SDRAM recording apparatus shown in FIG. However, in this method, 1
Since data recording is temporarily interrupted every time the recording of a ROW address is completed, data supplied continuously at high speed cannot be recorded without omission.

Attempts have been made to record radar video, which is radar output, in SDRAM. However, radar is a data source that outputs continuous data at high speed in synchronization with the radar's own timing, and the output of radar video generated by radar is controlled by the CPU that controls the input and output of data in SDRAM. The radar is SDR
Output data unilaterally regardless of the AM standby state,
Moreover, since the length (amount) of the data is variable, it is difficult to store the radar video in the SDRAM. When recording this radar video in SDRAM, the supply of data cannot be expected to end at the end of one ROW address. Therefore, in order to record radar video in SDRAM, it is necessary to continuously record data across two ROW addresses in SDRAM. But,
In the conventional recording method for SDRAM, as described above, ROW
Conventionally, this type of data could not be recorded in SDRAM because recording was interrupted when connecting the addresses.

It is convenient to record a radar video in a semiconductor memory where random access can be performed at high speed, for example, in analyzing a radar video. In a static random access memory (SRAM), which is a kind of semiconductor memory, there is no limitation on a memory area for continuously recording data. Therefore,
Conventional semiconductor memory for recording radar video
SRAM was used. SRAM has a lower storage density than DRAM, and if a device for recording a large amount of data is constituted only by SRAM, the storage device becomes expensive. Therefore, the first and second
Of the input radar video by the switching circuit called a selector.
Sorted to the AM storage unit, the radar video is alternately sent to both SRAM storage units, the radar video is alternately stored in the first or second SRAM storage unit, and the data from the SRAM storage unit on the other side is stored. A radar video recording device that reads and stores read data in a large-capacity storage device such as a hard disk or an MO (Magnetic-Optical disk, magneto-optical disk) is used. In this conventional radar video recording device, for example, while data is stored in the first SRAM storage unit, the data is first stored in the second SRAM storage unit, and the data is read out. The data is transferred to the large-capacity storage device, and when the data is completely stored in the storage capacity of the first SRAM storage unit, the input data is transferred to the second SR by the selector.
The data is distributed to the AM storage unit and stored in the second SRAM storage unit, while data is read from the first SRAM storage unit and transferred to the mass storage device. Selector switching control and first
The input / output control of the first and second SRAM storage units is performed by a selector, and the CPU monitors the state of the selector, and reads data when the switching from the first to the second or the second to the first occurs. I do.

[0022]

As described above, the SDRAM is a high-density random access memory capable of writing and reading data at high speed and at random, as described above. Is expected to be used as storage means for data supplied at high speed. However, due to the characteristics of radar video, which is supplied continuously regardless of the storage operation of SDRAM and the data length is variable, radar video cannot be recorded in SDRAM by the conventional method, and SRAM is used instead. It was as described above. But SRAM
Requires much more elements than SDRAM, so the storage capacity per SRAM chip is about 1/60 of that of SDRAM. Therefore, as described above, usually, a radar video recording device using a large-capacity storage device such as a hard disk or MO has been used.

However, large-capacity storage devices such as hard disks and MOs have much slower access speeds and larger shapes than semiconductor memories. Therefore, high-density semiconductor memories are required for applications such as radar video analysis. There is a need to record data in Therefore, an object of the present invention is to provide a method of recording continuously supplied large-length variable-length data such as radar video in an SDRAM that is a semiconductor memory and that can record at a much higher density than an SRAM. is there.

[0024]

In order to solve the above-mentioned problems, the present invention provides the following means.

(1) When P, Q and M are positive integers of 2 or more, and N is 4 or a positive integer of 4 or more, the block is composed of P blocks from the first to the Pth. The number of ROW addresses in the block is M from 0 to M−1, and each ROW address
To a SDRAM recording device in which the number of COLUMN addresses in the address is N from 0 to N-1 and the number of address bits is Q from the 0th bit to the Q-1th bit, a variable length of which length is not predetermined In the method of recording data,
When s is 2 or a positive integer of 2 or more and N <s <Q, a COLUMN address is selected by N address bits from the 0th bit to the N-1th bit among the address bits, A block is selected by sN address bits from N bits to s-1th bit, and a ROW address is selected by Qs address bits from sth bit to Q-1 bit. A method for recording variable-length data in an SDRAM recording device.

(2) When recording of the data is started while the COLUMN counter value n (n is 0 or 1 or a positive integer of 1 or more) is from 0 to N-3, the COLUMN counter value is set to n. When the active command ACTV and the write command WRITE are issued to the current block p (1 ≦ p ≦ P), the active command ACTV is issued to the next block when the COLUMN counter value n reaches N−2. When the COLUMN counter value n reaches 0, a write command WRITE is issued to the next block, and the write command WRITE is issued to the current block p and the next block.
Is the active command AC in each block.
Delayed at least 2 clock hours from TV, COLU
When the data recording is started when the MN counter value n is N-2, when the COLUMN counter value n is N-2, the active command ACTV is issued to the current block p and the next block, A write command WRITE is issued to the current block p and the COLUMN counter value n
When the COLUMN counter value n is N-2, a write command WRITE is issued to the next block when the COLUMN counter value n is N-2. Sometimes the clock timing of the active command ACTV issued to the next block is the active command ACTV issued to the current block p.
And a method for recording variable-length data in an SDRAM recording device according to the above (1), which is different from a clock timing of a write command WRITE.

(3) When the data recording is started when the COLUMN counter value n is N-2, the write command WRITE addressed to the current block p is the clock of the active command ACTV addressed to the current block p. The write command WRITE addressed to the next block is delayed by 3 clock times from the clock timing of the active command ACTV addressed to the next block, and the active command addressed to the next block is delayed by 2 clock times. The method for recording variable-length data in an SDRAM recording device according to (2), wherein the ACTV is delayed by one clock time from the clock timing of the active command ACTV addressed to the current block p.

(4) To start recording the data when the COLUMN counter value n is N-1, when the COLUMN counter value n is N-1, the active command ACTV is transmitted to the current block p and the next command. A write command WRITE is issued to the current block p and a write command W is issued when the COLUMN counter value n is 0.
Issue RITE to the next block and COLUMN counter value
When the data recording is started when n is N−1, the clock timing of the active command ACTV issued to the next block when the COLUMN counter value n is N−1 is the current block. (2) wherein the clock timing of the active command ACTV and the write command WRITE issued to p is different.
Or a method of recording the variable-length data according to (3) in an SDRAM recording device.

(5) When the data recording is started when the COLUMN counter value n is N-1, the write command WRITE addressed to the current block p is the clock of the active command ACTV addressed to the current block p. The write command WRITE addressed to the next block is delayed by two clock times from the clock timing of the active command ACTV addressed to the next block, and the active command addressed to the next block is delayed by two clock times. The method according to (4), wherein the ACTV is delayed by one clock time from the clock timing of the active command ACTV addressed to the current block p.

(6) The variable length data is a radar video supplied from a radar device, and the length of the data is determined by a time from a recording start time of the data to a recording end time of the data. The time point is a time point t1 when a predetermined minute time δT elapses from the radio wave emission time point t0 of the radar device, and the radio wave reciprocates over the maximum distance R of the monitoring area designated by the radar device at the recording end time point. The time t after the time t1 has elapsed by the time Tr
2. The method of recording variable-length data in an SDRAM recording device according to any one of (2) to (5), wherein the radio wave emission time point t0 is supplied from the radar device.

[0031]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described.
The present invention will be described in more detail.

FIG. 1 is a diagram for explaining an embodiment of the "method of recording variable-length data in an SDRAM recording device" of the present invention. More specifically, data of the data is applied by applying the method of the embodiment. FIG. 2 is a block circuit diagram of an SDRAM recording device for collecting. FIG. 2 is a diagram conceptually showing a data recording area according to the method of the embodiment. FIG. 3 is a circuit block diagram mainly showing an address circuit for selecting an SDRAM block in the circuit of FIG. FIG. 1 omits the gate circuits G1 to G4 in FIG. Gate circuit
G1 to G4 form an address circuit for selecting one of the SDRAM blocks # 1 and # 2.

FIGS. 4, 5 and 6 show the case where a large amount of continuous data is recorded in the SDRAM recording apparatus of FIG.
FIG. 4 is a timing chart of commands and addresses given to the M recording device. More specifically, FIG. 4 is a timing chart when data writing is started when the COLUMN address is 0,
FIG. 5 is a timing chart when data writing is started when the COLUMN address is 1022, and FIG. 6 is a timing chart when the COLUMN address is 1022.
FIG. 10 is a timing chart when data writing is started at 1023. The case of starting writing from CLM addresses 1 to 1021 is the same as in FIG. In FIG. 4, a thick line indicated by reference symbol S1 is a line that vertically separates a region on the paper surface. Thick line F1
The right end of the upper timing chart is continuously connected to the left end of the timing chart below the thick line F1. FIG.
~ COLUMN address 0,1,2,3, ... 1022,1023,
0,... Each represents the time width of one clock, and the command
ACTV, WRITE, BST, PRE, etc. are executed in one clock time.
FIG. 7 shows the SDR when a large amount of continuous data supplied from the radar device is recorded in the SDRAM recording device of FIG.
6 is a flowchart illustrating a flow of processing performed by an SDRAM controller that controls an AM recording device. In the figure,
WR is an abbreviation of write command WRITE, # 1 command,
The commands # 2 and # 4 mean the commands given to the SDRAM block # 1, the SDRAM block # 2 and the SDRAM block # 4, respectively.

In the embodiment shown in FIG. 1, the tenth and eleventh address bits A [11, 10] are stored in the SDRAM blocks # 1 to SD
It is characterized in that it is allocated for selection of RAM block # 4. In this embodiment, the address bits A [9
… 0] represents the COLUMN address, and the address bit A [23 ...
12] indicates a ROW address, and address bits A [25, 24]
Represents a BANK address. A [11,10] represents a block address. In the conventional method described with reference to FIG.
The twenty-fourth and twenty-fifth address bits A [25, 24] are allocated for selection of the SDRAM blocks # 1 to # 4. The embodiment of FIG. 1 is significantly different from the conventional method of FIG. 8 in the function of assigning address bits. Address bits A [25 ... 12] and A [9 ... 0] are address line 1
And address bits A [11,10] are
Supplied with. The SDRAM recording device of FIG. 1 has the same configuration as the device of FIG. 8 except for the address circuit.

By allocating address bits according to the method of FIG. 1, when data is recorded in the SDRAM recording device, the data recording order for COLUMN, ROW, BANK and block (BLOCK) of the SDRAM recording device is as shown in FIG. The concept is shown in Fig. 2. Now, SDRAM block # 1, BANK0, RO
It is assumed that data recording is started from the address W0, COLUMN0. At this time, all the bit values in the address bits [25 ... 0] are 0.

FIG. 4 shows BANK0, ROW0, SDRAM block #
The timing of a command when data recording is started from an address of 1, COLUMN0 is described. The value in the COLUMN address column is the above-mentioned COLUMN counter value n. In the state of FIG. 4, the address A [11,10] of the SDRAM block is 0,0, the SDRAM block # 1 is selected, and the BAN
When the K address is 0 and the value of the ROW counter is 0 (ROW address is 0), the active command ACTV and the write command WRITE are sent to the ROW address 0 of the SDRAM block # 1.
Issue to Thereafter, data is sequentially written to the COLUMN address in the ROW address 0 until the burst stop command BST is issued. COLUM of row address 0
If the burst stop command BST is not issued until data is written to N address 1023, COLUMN address 1
When data is recorded in 023, a burst stop command BST is issued at the next clock timing, and the writing of data to the ROW address 0 of the SDRAM block # 1 ends.

The active command ACTV and the write command WRITE are both commands involving address bits, and since there is only one address bus in the SDRAM recording device, both commands cannot be issued simultaneously. Further, when the active command ACTV is issued to a certain ROW address and the ROW is activated, and then a write command WRITE is issued to the ROW address, at least from the issuance of the active command ACTV to the issuance of the write command WRITE, One clock time interval must be left. That is, the issue of the write command WRITE needs to be delayed by two clock times from the issue of the active command ACTV.

The COLUMN address at the ROW address 0 of the SDRAM block # 1 is 1022 (the COLUMN counter value is 1022).
At the address A [11,10] of the SDRAM block
Set to 0, 1 to select SDRAM block # 2, issue an active command ACTV to ROW address 0 of SDRAM block # 2, and when the COLUMN counter value reaches 1023,
COLUMN address 1 of ROW address 0 in block # 1
Data is recorded at 023, and when the COLUMN counter value reaches 0, a write command WRITE is issued to ROW address 0 of SDRAM block # 2, a BST is issued to ROW address 0 of SDRAM block # 1, and SDRAM is issued. RO in block # 2
Data is sequentially recorded from the COLUMN address 0 to 1023 of the W address 0 or until a recording completion instruction is issued by the burst stop command BST.

Here, when the COLUMN address at ROW address 0 of the SDRAM block # 1 reaches 1022, the SDRAM block
Despite data being recorded at ROW address 0 of block # 1, address A (11, 10) of the SDRAM block is set to 0, 1, SDRAM block # 2 is selected, and SDRAM block # 2 is selected.
The reason why the active command ACTV is issued to the ROW address 0 of No. 2 is that, as described above, an interval of at least one clock time must be provided between issuing the active command ACTV and issuing the write command WRITE. . That is, when the COLUMN address in the ROW address 0 of the SDRAM block # 1 reaches 1023, in order to enable data recording immediately at the next clock timing without interrupting data recording, the next ROW address is required. It is necessary to issue an active command ACTV in advance, make the next ROW address active, and prepare to issue a write command WRITE to the next ROW address.

In order to be able to record data continuously, it is necessary to record data across ROW addresses without interruption. In order to enable recording of data across ROW addresses, in the present invention, the address of the SDRAM block is incremented by one immediately before the end of recording for one ROW address, and one address in the next SDRAM block is incremented. Active command ACTV on ROW address
Issue a write command WRITE to the next SDRAM block.
Be prepared to issue the.

In this embodiment, the COLUMN address A [9
... 0] and A [11,10] on the MSB side from A [9 ... 0]
Allotment is made to address bits for SDRAM block selection, and when selection of one ROW address in one SDRAM block is completed, a ROW address in the next SDRAM block is automatically selected. By adopting this configuration, immediately before recording to one ROW address is completed, the next R
Issue the active command ACTV to the OW address and return to the previous RO
When the recording area of the W address becomes full, recording can be continuously performed at the next ROW address without interruption.

When data is recorded on the SDRAM recording device by the method of the present embodiment, the data is recorded as shown in FIG. Bank address 0, R of SDRAM block # 1
When data recording from COLUMN address 0 to 1023 at OW address 0 is completed, next, the BAN of SDRAM block # 2
COLUMN address 0 in K address 0, ROW address 0
From 1023 to 1023, and the C at the BANK address 0 and ROW address 0 of the SDRAM blocks # 3 and # 4.
Data is recorded from OLUMN addresses 0 to 1023.

Bank address 0, ROW of SDRAM block # 4
When data is recorded from COLUMN 1023 at address 0, data is recorded from COLUMN addresses 0 to 1023 in ROW address 1 of SDRAM blocks # 1 to # 4. Similarly, SDRAM blocks # 1 to # 4 of BANK0
The data is recorded from ROW address 2 to 1023.
Next, for each of Banks 1 to 3, the SDRAM block #
Data is recorded in ROW addresses 0 to 1023 of 1 to # 4. Thus, all COLs in the SDRAM recording device
Data is recorded at the UMN address.

In the data recording method of the present embodiment described above, data recording is not interrupted at the break of the ROW address, and from the first COLUMN address where recording is started to the last COLUMN address where recording is ended. Data is recorded continuously. Because the data is recorded continuously, even if the length of the data is not known in advance,
That is, even if the data length is variable, there is no problem in data recording.

In FIG. 4, addresses BANK0, ROW0, SDRAM block # 1, COLUMN0, that is, address A [25... 0]
The command timing for starting the data recording when the bit values of all the bits are 0 has been described. When data recording is started in a state where the COLUMN address is between 0 and 1021, data recording can be performed in the same manner as described above. To start recording data when the COLUMN address is between 0 and 1021,
When the COLUMN counter value reaches 1021, the SDRAM controller prepares to issue an active command ACTV at the next clock timing. However, in the method of the present embodiment, when data recording is started with the COLUMN address being 1022, it is necessary to start data recording by a method slightly different from the above-described method.

FIG. 5 is a timing chart when data writing is started when the COLUMN address is 1022 (COLUMN counter value is 1022). In the figure, the address A [11, 10] of the SDRAM block is 1, 1, that is, the SDRAM block # 4 is selected, the ROW address of the SDRAM block # 4 is 0, and the COLUMN address is 1022. When to start recording data. At this time, in the COLUMN address 1022, it is necessary to issue the active command ACTV and the write command WRITE to the ROW address 0 of the SDRAM block # 4 and issue the active command ACTV to the ROW address 1 of the SDRAM block # 1. These commands cannot be issued at the same clock timing, and SDRA
Since the active command ACTV and the write command WRITE at the ROW address 0 of the M block # 4 must be spaced by one clock time, at least three clock times are required at the COLUMN address 1022. So, SDRA
Active command AC at ROW address 1 of M block # 1
The interval between issuing a TV and issuing a write command WRITE to ROW address 1 of the same SDRAM block # 1 is as follows:
It is longer by one clock time than in the case of FIG. As is clear from the above description, when data recording is completed with the COLUMN counter value set to 1021, the SDRAM controller issues an active command at the next clock timing.
Do not prepare for and issue ACTV.

FIG. 6 is a timing chart when data writing is started when the COLUMN address is 1023. In the figure, the address A [11, 10] of the SDRAM block is 1, 1, that is, the SDRAM block # 4 is selected, and the SDR
Data recording is started when the ROW address of the AM block # 4 is 0 and the COLUMN address is 1023. The recording start state in FIG. 6 is the same as FIG. 5 except for the COLUMN address value. In FIG. 6, after the active command ACTV is issued to the ROW address 1 of the SDRAM block # 1, the same SD
Write command WRIT to ROW address 1 of RAM block # 1
There will be an interval of one clock time before issuing E. As is clear from the above explanation, when data recording is completed with the COLUMN counter set to 1022, the SDRAM
The controller prohibits the issuance of ACTV to the next SDRAM block.

FIG. 7 shows a case where a large amount of continuous radar video is received from the radar device in the SDRAM recording device of FIG. 1 and the radar video is recorded as data.
6 is a flowchart illustrating a flow of processing performed by an SDRAM controller that controls a RAM recording device. Write Enable in steps S1 and S6 is a signal generated by the video acquisition controller based on the signal supplied from the radar device. The video acquisition controller determines the range of the radar video to be acquired according to various triggers and radar modes supplied from the radar, and generates Write Enable in accordance with the range. The video acquisition controller is an example of the aforementioned SDRAM controller. Indicates whether the video output of the radar device should be recorded. When recording the radar video by the method according to the embodiment of the present invention described with reference to FIGS. 1 to 6, the SDRAM controller controls the SDRAM recording device of FIG. 1 according to the procedure of FIG.

As described above in detail, according to the method of the present embodiment, variable-length data supplied continuously and in large quantities, such as radar video, can be easily recorded in the SDRAM.

Although the present invention has been described in detail with reference to the embodiments, it is needless to say that the present invention is not limited to the embodiments.

[0051]

According to the present invention, as described in detail in the above embodiments, the present invention is a semiconductor memory,
It is possible to provide a method of easily recording continuously supplied variable-length data such as radar video in SDRAM, which can record much higher density than SRAM.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an embodiment of the present invention, and more specifically, is a block circuit diagram of an SDRAM recording device that collects data by applying a method of the embodiment.

FIG. 2 is a diagram conceptually showing a data recording area according to the method described in FIG.

FIG. 3 is a circuit block diagram mainly showing an address circuit for selecting an SDRAM block in the circuit of FIG. 1;

FIG. 4 shows a case where a large amount of continuous data is recorded in the SDRAM recording device of FIG. 1, and when data writing is started when the COLUMN address is 0, a command and an address timing given to the SDRAM recording device FIG.

5 shows a case in which a large amount of continuous data is recorded in the SDRAM recording device of FIG. 1, and when writing of data is started when the COLUMN address is 1022, the timing of a command and an address given to the SDRAM recording device FIG.

FIG. 6 shows a case where a large amount of continuous data is recorded in the SDRAM recording device of FIG. 1, and when data writing is started when the COLUMN address is 1023, timing of a command and an address given to the SDRAM recording device. FIG.

FIG. 7 shows an SDRAM for controlling the SDRAM recording device when recording a large amount of continuous data on the SDRAM recording device of FIG.
5 is a flowchart illustrating a flow of a process performed by a controller.

FIG. 8 is a block circuit diagram of an SDRAM recording device that collects data by a conventional method.

9 is a diagram conceptually showing a data recording method in the apparatus of FIG.

10A is a diagram showing a configuration of an SDRAM block # 1 in the device of FIG. 8, and FIG. 10B is a conceptual diagram showing a data recording mode in FIG.

FIG. 11 is a diagram of a circuit for recording data in the SDRAM block # 1 of FIG.

[Explanation of symbols]

 1 to 4 ... Address line A ... Address ACYV ... Active command BK ... BANK (bank) BST ... Burst stop command CLM ... COLUMN (column) G1 to G4 ... gate circuit J1 to J4 ... SDRAM chip PRE ... precharge command WR ... write command

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G11C 11/34 371H

Claims (6)

[Claims] (1) P, Q and M are 2 or a positive integer of 2 or more,
When N is 4 or a positive integer of 4 or more, the first to Pth
ROW in each block
The number of addresses is M from 0 to M-1, the number of COLUMN addresses in each ROW address is N from 0 to N-1, and the number of address bits is Q from bit 0 to bit Q-1. In a method of recording variable-length data having an undefined length on a certain SDRAM recording device, when s is 2 or a positive integer of 2 or more, and N <s <Q, the second of the address bits The COLUMN address is selected by the N address bits from the 0th bit to the N-1th bit, the block is selected by the sN address bits from the Nth bit to the s-1th bit, and the sth bit is selected. A method for recording variable-length data in an SDRAM recording device, wherein a ROW address is selected by using Qs address bits up to the Q-1th bit. 2. When recording of said data is started while the COLUMN counter value n (n is 0 or 1 or a positive integer of 1 or more) is from 0 to N-3, the COLUMN counter value is n. Active command ACTV and write command
WRITE is issued to the current block p (1 ≦ p ≦ P) and COLU
When the MN counter value n reaches N-2, the active command ACTV is issued to the next block. When the COLUMN counter value n reaches 0, the write command WRITE is issued to the next block. The write command WRITE issued to the block p and the next block is delayed by at least two clock times from the active command ACTV in each block, and the data recording is performed when the COLUMN counter value n is N-2. When the COLUMN counter value n is N-2, an active command ACTV is issued to the current block p and the next block, a write command WRITE is issued to the current block p, and the COLUMN When the counter value n reaches 0, a write command WRITE is issued to the next block, and when the COLUMN counter value n is N-2, the data is written. COLUMN counter value n is N-2
The clock timing of the active command ACTV issued to the next block when
2. The method for recording variable-length data in an SDRAM recording device according to claim 1, wherein the clock timing of the active command ACTV and the write command WRITE issued to p is different. 3. When the data recording is started when the COLUMN counter value n is N-2, the write command WRITE addressed to the current block p is issued by the current block p.
The write command WRITE addressed to the next block is delayed by 3 clock times from the clock timing of the active command ACTV addressed to the next block. 3. The variable length data according to claim 2, wherein the active command ACTV destined for the block is delayed by one clock time from the clock timing of the active command ACTV destined for the current block p. How to record. 4. When the data recording is started when the COLUMN counter value n is N-1, the COLUMN counter value
When n is N-1, the active command ACTV is issued to the current block p and the next block, the write command WRITE is issued to the current block p, and
When the write command WRITE is issued to the next block when the LUMN counter value n is 0 and the recording of the data is started when the COLUMN counter value n is N-1, the COLUMN counter value n becomes N -1
The clock timing of the active command ACTV issued to the next block when
4. The variable length data according to claim 2, wherein the clock timing of the active command ACTV and the write command WRITE issued to the address p is different from that of the SDRAM.
A method of recording on a recording device. 5. When starting recording of said data when the COLUMN counter value n is N-1, the write command WRITE addressed to the current block p is issued by the current block p.
The write command WRITE addressed to the next block is delayed by two clock times from the clock timing of the active command ACTV addressed to the next block. 5. The variable length data according to claim 4, wherein the active command ACTV destined for the current block p is delayed by one clock time from the clock timing of the active command ACTV destined for the current block p. How to record. 6. The variable length data is a radar video supplied from a radar device, and the length of the data is determined by a time from a recording start time of the data to a recording end time of the data. Is a time point t1 when a predetermined minute time δT has elapsed from the radio wave emission time point t0 of the radar device, and the recording end time point is a time when the radio wave reciprocates over the maximum distance R of the monitoring area designated by the radar device 6. The method of recording variable-length data in an SDRAM recording device according to claim 2, wherein the time t2 is a time t2 after a lapse of Tr from the time t1, and the radio wave emission time t0 is supplied from the radar device. .