JP2001267852A - Predistortion circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To compensate also the non-linear characteristic of a phase. SOLUTION: A FET12 and a phase compensating capacitor Cp are respectively connected between a buffer amplifier 11 and earth and between an auxiliary amplifier 14 and earth. The differential resistance of the FET12 impressing a prescribed bias voltage to a gate electrode is exponentially functionally raised to the right when voltage between the drain and source of the FET12 is increased and the differential resistance is reduced when the voltage between the gate and source is increased. A current amount to be branched to the capacitor Cp is changed in accordance with the level of the differential resistance. Thus the non-linear characteristics of the amplitude and phase of a saturated amplifier 3 can be compensated to almost linear states by utilizing the differential resistance and the non-linear characteristic of the current amount branched to the capacitor Cp.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a predistortion circuit for compensating an amplifier having a non-linear characteristic.

[0002]

2. Description of the Related Art If nonlinear characteristics occur in a power amplifier of a high-frequency signal, which is the last stage of a transmitter in radio equipment and video equipment, intermodulation (Inter Modulation) is required when amplifying a plurality of carrier signals having different frequencies. ) Occurs. For example, if the frequency of the first carrier signal input to the power amplifier is f ₁ and the frequency of the second carrier signal is f ₂ (where f ₂ > f ₁ ), the spurious frequency is (2f ₂ − f ₁ ) and (2f ₁ −f ₂ )
The next intermodulation distortion component and the spurious frequency are (3f ₂ −
5th-order intermodulation distortion components 2f ₁ ) and (3f ₁ -2f ₂ ) are generated. As described above, when the intermodulation occurs, many spurs are generated and interfere with the adjacent channels. Therefore, the power amplifier specifies the amount of suppression (IM3) of the third-order intermodulation distortion component for the carrier signal and the amount of suppression (IM5) of the fifth-order intermodulation distortion component for the carrier signal. There is a demand for an amplification characteristic that can provide a large suppression amount as described above. However, since the fifth-order intermodulation distortion component is a spurious signal having a smaller power than that of the third-order intermodulation distortion component, the power of the third-order intermodulation distortion component may be actually set to a predetermined value or less. Become.

[0003] However, as a power amplifier, a class C saturated amplifier generally having a non-linear characteristic in terms of power efficiency is used. Therefore, in order to reduce the power of the third-order intermodulation distortion component caused by the non-linear characteristic even if a saturation amplifier is used, a pre-distortion circuit having a non-linearity opposite to the non-linearity of the power amplifier is provided before the power amplifier. It is provided.

FIG. 1 shows an example of a pre-distortion circuit (Japanese Patent Application No. 11-248322) proposed by the present applicant.
It is shown in FIG. Predistortion circuit 20 shown in FIG.
0 to the input terminal IN of the input signal e _in from the signal source 202.
And a power amplifier 203 serving as a saturation amplifier is connected to the output terminal OUT of the predistortion circuit 200. The output of the power amplifier 203 is supplied to a load resistor RL. By providing the pre-distortion circuit 200 in front, the input / output characteristics of the output signal of the power amplifier 203 with respect to the input signal e _in are made substantially linear.

The pre-distortion circuit 200 includes a buffer amplifier 211 having a gain of almost 0 dB, and an auxiliary amplifier 213 connected to the buffer amplifier 211. The buffer amplifier 211 and the auxiliary amplifier 21
The input impedance of No. 3 matches the impedance of the input side, and its output impedance matches the impedance of the output side. An N-channel MOS field effect transistor (N-MOSFET) 212 is connected between a line for inputting the output of the buffer amplifier 211 to the auxiliary amplifier 213 and the ground. The drain electrode (D) of the N-MOSFET 212 is connected to the line, and the source electrode (S) is connected to the ground. Further, a bias voltage Vgs from a bias voltage source 214 is supplied to the gate electrode (G).
Generally, when the drain-source voltage Vds is changed in a field-effect transistor, the drain current increases as shown in FIG.
6, it changes nonlinearly. As a result, the drain-source voltage with respect to the drain-source voltage Vds
The source-to-source resistance Rds changes nonlinearly as shown in FIG. This non-linear characteristic changes according to the bias voltage Vgs applied to the gate electrode.

A predistortion circuit 2 shown in FIG.
The equivalent circuit of 00 is as shown in FIG. As shown in this equivalent circuit, the N-MOSFET 212 in the predistortion circuit 200 is shown as a resistor Rds connected in parallel between input and output. The internal impedance of the signal source 202 is represented by Rs, the internal impedance Rs is, for example, 50Ω, and the load resistance RL is, for example, 50Ω. The input / output transfer characteristic G of the predistortion circuit 1 at this time is expressed by the following equation. G = {Rds · RL / (Rds + RL)} / {Rs + Rds · RL / (Rds + RL)} (1) where Rds is N-MOSFET2 in equation (1).
Twelve differential resistances between drain and source, that is, AC resistances.

As shown in FIG. 16, the drain current Id with respect to a change in the drain-source voltage Vds exhibits a right-up saturation characteristic, and the drain current increases as the gate-source voltage Vgs increases (Vgs1 <Vgs2).
<Vgs3). From this, as shown in FIG. 16, the differential resistance Rds with respect to the drain-source voltage Vds changes exponentially to the right, and the differential resistance Rds
The ds increases as the drain-source voltage Vds increases, and the differential resistance Rds decreases as the gate-source voltage Vgs increases. Since the differential resistance Rds changes in this manner, the loss characteristic of the pre-distortion circuit 200 due to the transfer characteristic represented by the above equation (1) becomes a non-linear characteristic falling to the right as shown in FIG. 17, the horizontal axis represents the input signal amplitude of the input signal e _in from the signal source 202, and the vertical axis represents the predistortion circuit when the change characteristics of the differential resistors Rds1, Rds2, and Rds3 shown in FIG. 200 losses.

In FIG. 17, the loss of the predistortion circuit 200 is minimized when the differential resistance Rds is maximized. For example, if the differential resistance Rds becomes infinite, the above equation (1) is used. Transfer function G
Becomes G _{Rds = ∞} = RL / (Rs + RL). here,
If Rs = RL, G _{Rds = ∞} = １ ／.
That is, the minimum loss of the pre-distortion circuit 200 is 6 dB as illustrated. Further, when the amplitude of the input signal is set to zero, the differential resistance Rds becomes the smallest, so that the loss of the predistortion circuit 200 becomes the largest. For example, when the input signal amplitude is zero when the gate-source voltage is Vgs3, the differential resistance Rds3 is 10
If it is ohm, the loss of the pre-distortion circuit 200 is about 17 dB because the transfer function G is about 0.142. Therefore, the gain of the auxiliary amplifier 213 shown in FIG. 14 for compensating for the loss of the predistortion circuit 200 is set to 15 dB to 20 dB.

[0009] Summing up the above, the operation of the pre-distortion circuit 200 shown in FIG. 14 is as shown in the flow chart of FIG. That is, as shown in FIG. 18, when the amplitude of the input signal e _in of the signal source 202 increases (step S31), the drain-source voltage Vds of the N-MOSFET 212 increases (step S32). As a result, FIG. As shown, the differential resistance Rds increases (step S33), and the loss of the pre-distortion circuit 200 decreases as shown in FIG. 17 (step S3).
4). As described above, when the amplitude of the input signal e _in of the signal source 202 increases, the loss of the pre-distortion circuit 200 decreases.
03 will be input. Therefore, the non-linear characteristic of the power amplifier 203 having the saturation characteristic shown in FIG. 19A is changed to the pre-distortion circuit 200 shown in FIG.
19, the output level becomes substantially linear as shown by c in FIG. That is, the power amplifier 203
And the non-linear characteristic of the pre-distortion circuit 200 are reversed, so that the overall characteristic of the power amplifier 203 provided with the pre-distortion circuit 200 in front of it as shown in FIG.

[0010]

In the pre-distortion circuit described above, the reverse characteristic of a power amplifier showing a saturation characteristic with respect to amplitude is realized by the pre-distortion circuit. Thus, by providing a predistortion circuit in front of the power amplifier, it is possible to compensate for the non-linear characteristic of the amplitude and obtain a linear characteristic. However, in the amplifier, the phase of the output signal also changes non-linearly according to the input signal level. However, the pre-distortion circuit does not consider the non-linear characteristic of the phase. For this reason, there is a problem that the suppression amount (IM3) of the third-order intermodulation distortion component for the carrier signal in the amplifier exhibiting the saturation characteristic is not improved to a certain degree or more.

Accordingly, an object of the present invention is to provide a predistortion circuit capable of compensating for even the nonlinear characteristic of the phase.

[0012]

In order to achieve the above object, a predistortion circuit according to the present invention is provided in front of an amplifier, and is a predistortion circuit for compensating for nonlinear characteristics of the amplifier. A transistor connected between the line connecting the input terminal and the output terminal and the ground, a bias voltage source for applying a predetermined bias voltage to the control electrode of the transistor, and a phase compensation capacitor connected in parallel with the transistor And

According to another aspect of the present invention, there is provided a predistortion circuit which is provided in front of an amplifier and which compensates for nonlinear characteristics of the amplifier. A transistor connected between the line connecting the input terminal and the output terminal and the ground, a bias voltage source for applying a predetermined bias voltage to the control electrode of the transistor, a phase compensation inductor connected in parallel with the transistor, It has.

Further, in the predistortion circuit according to the present invention, the transistor may be a field effect transistor, a drain electrode may be connected to the line, and a source electrode may be connected to ground.
Further, in the predistortion circuit of the present invention, a buffer amplifier is inserted between the input terminal and the line to which the transistor is connected, and between the line to which the transistor is connected and the output terminal. , An auxiliary amplifier for compensating the amount of attenuation by the transistor may be inserted. Furthermore,
In the predistortion circuit of the present invention, the bias voltage source may be a variable voltage source so that the amount of nonlinear compensation can be adjusted.

According to the present invention, the amplitude is compensated by utilizing the non-linear characteristic of the transistor, and the phase is compensated by the interaction with the phase compensating capacitor or the phase compensating inductor connected in parallel with the transistor. Since compensation can be performed, a pre-distortion circuit capable of compensating for non-linear characteristics of phase in addition to amplitude can be provided. Also, since the non-linear characteristics of the transistor can be changed by the bias voltage applied to the control electrode, by using a bias voltage source as a variable voltage source, the amount of phase and amplitude compensation can be adjusted, and the best compensation can be achieved. Will be able to do it.

[0016]

FIG. 1 shows a circuit configuration of a predistortion circuit according to a first embodiment of the present invention.
The pre-distortion circuit according to the first embodiment is a pre-distortion circuit in a case where an amplifier exhibiting a saturation characteristic is an advanced phase amplifier. The input terminal IN of the pre-distortion circuit 1 shown in FIG.
, And an output terminal OUT of the predistortion circuit 1 is followed by a saturation amplifier 3. The output of the saturation amplifier 3 is supplied to a load resistor RL. When the saturation amplifier 3 is the last stage of the transmitter, the load resistor RL becomes an antenna system. The antenna system generally includes a matching circuit and an antenna. By providing the pre-distortion circuit 1 in front, the input / output characteristics of the output signal of the saturation amplifier 3 with respect to the input signal from the signal source 2 are made almost linear, and the third-order intermodulation distortion component is suppressed for the carrier signal. The amount (IM3) can be made a sufficient suppression amount.

The pre-distortion circuit 1 includes a buffer amplifier 11 having a gain of approximately 0 dB and an auxiliary amplifier 14 connected to the buffer amplifier 11. The input impedance of the buffer amplifier 11 and that of the auxiliary amplifier 14 are matched with the impedance of the input side, and the output impedance is matched with the impedance of the output side. The output of the buffer amplifier 11 is input to the auxiliary amplifier 14, and a field effect transistor (FET) 12 is connected between the line to which the output is transmitted and the ground. This F
The ET 12 is, for example, an N-channel MOS (Metal Oxide).
Semiconductor) type FET (N-MOSFET), the drain electrode (D) is connected to the line, and the source electrode (S) is connected to the ground. Further, the bias voltage Vgs from the bias voltage source 13 is supplied to the gate electrode (G).

In general, when the drain-source voltage is changed in a field-effect transistor, the change in drain current has non-linear characteristics. That is, the differential resistance between the drain and the source with respect to the voltage between the drain and the source changes nonlinearly. The non-linear characteristic of the differential resistance changes depending on the bias voltage Vgs applied to the gate electrode. The pre-distortion circuit 1 shown in FIG. 1 uses the nonlinear characteristic of the differential resistance to compensate for the nonlinear characteristic of the amplitude of the post-saturation amplifier 3. A phase compensation capacitor Cp is connected in parallel with the FET 12. The pre-distortion circuit 1 according to the first embodiment of the present invention is characterized in that the phase compensating capacitor Cp is connected. This phase compensation capacitor Cp is connected to the above-described FET.
By connecting in parallel with the differential resistance between the drain and the source having the nonlinear characteristic in 12, the nonlinear characteristic of the phase of the saturation amplifier 3 provided after the predistortion circuit 1 is compensated.

FIG. 2 shows an equivalent circuit of the pre-distortion circuit 1. In this equivalent circuit, the FET 12 in the predistortion circuit 1 is shown as a drain-source differential resistance Rds connected in parallel between the input and output. However, since the input / output impedance of the buffer amplifier 11 is matched on the input side and the output side and does not affect the transfer characteristics described later, the buffer amplifier 11 is omitted. The internal impedance of the signal source 2 is represented by Rs, and the internal impedance Rs is, for example, 50Ω. Further, the input impedance of the auxiliary amplifier 14 is represented by RL, and the input impedance RL is, for example, 50Ω. Here, the differential resistance R
ds, the phase compensation capacitor Cp, and the parallel impedance obtained by connecting the input impedance RL in parallel are Zp, and the input / output transfer characteristic G of the predistortion circuit 1
Is represented by the following equation. G = Zp / (Rs + Zp) (2) In the equation (2), the impedance Zp is represented by the following equation. Zp = 1 / {(1 / Rds) + jωCp + (1 / RL)} (3) Note that Rds is a differential resistance between the drain and source of the FET 12, and is an AC resistance.

The differential resistance Rds between the drain and source of the FET 12 changes nonlinearly according to the voltage level of the signal output from the buffer amplifier 11. As described above, the non-linear characteristic of the amplitude of the saturation amplifier 3 can be compensated as described above, and the outline thereof will be described with reference to FIGS. As shown in FIG. 16, the drain current Id with respect to the change in the drain-source voltage Vds shows a right-saturation saturation characteristic. Then, Vgs1 <Vgs2 <Vg
As the gate-source voltage Vgs set as s3 increases, the drain current Id increases. in this case,
The differential resistance Rds obtained by differentiating the drain-source voltage Vds with the drain current changes exponentially upward as shown in FIG. Further, the differential resistance Rd
s increases sharply as the drain-source voltage Vds increases, and the differential resistance Rds changes according to the gate-source voltage Vds.
It decreases as shown in the figure as gs increases.

Since the differential resistance Rds changes in this manner, the loss characteristic of the pre-distortion circuit 1 based on the transfer characteristic G expressed by the above equation (2) is similar to the non-linear characteristic falling to the right shown in FIG. The loss of the predistortion circuit 1 is minimized when the input signal level from the signal source 2 is large and the differential resistance Rds is maximized, and when the input signal level from the signal source 2 is almost zero. The differential resistance Rds becomes the smallest, and the loss of the pre-distortion circuit 1 becomes the largest. The auxiliary amplifier 14 assists this loss. For example, the auxiliary amplifier 1
The gain of 4 is 15 dB to 20 dB.

As described above, when the amplitude of the input signal from the signal source 2 increases, the loss of the predistortion circuit 1 decreases, so that a larger input signal is input to the saturation amplifier 3. Therefore, the nonlinear characteristic of the saturation amplifier 3 having the saturation characteristic shown in FIG. 19A is compensated for by the nonlinear characteristic of the predistortion circuit 1 shown in FIG. 19B, and the output level becomes almost linear. That is, since the nonlinear characteristic of the saturation amplifier 3 and the nonlinear characteristic of the pre-distortion circuit 1 are reversed, the overall characteristic of the saturation amplifier 3 in which the pre-distortion circuit 1 is provided in front as shown in FIG. It becomes.

Next, the principle of phase compensation by the phase compensation capacitor Cp will be described with reference to FIG. FIG.
The pre-distortion circuit 1 shown in (a) is shown by the equivalent circuit shown in FIG. The phase relationship between the output signal voltage Vout and the input signal voltage Vin from the signal source 2 of the predistortion circuit 1 shown in FIG. 3A is shown in a vector diagram in FIGS. 3B and 3C. However,
The current It is a current supplied from the signal source 2, and the current It
r is a current shunted to the differential resistance Rds and the input impedance RL of the auxiliary amplifier connected in parallel, and a current Ic is a current shunted to the phase compensation capacitor Cp. The voltage Vrs is a voltage corresponding to a voltage drop due to the internal resistance Rs of the signal source.

As shown in FIG. 3B, the input signal voltage V
in is divided into a voltage drop Vrs due to the internal resistance Rs and an output signal voltage Vout. By the way, since the current Ic is a current flowing in the capacitor, the current Ic is ahead of the current Ir flowing in the resistor by 90 °, and the current It is the current Ic
And the current Ir are vector-combined. The voltage drop Vrs becomes a voltage having the same phase as the current It due to the voltage drop due to the internal resistance Rs. As shown in the figure, the output signal voltage Vout eventually lags behind the input signal voltage Vin by the phase θd. Here, the level of the input signal voltage Vin increases (the drain voltage of the FET 12).
When the source-to-source voltage Vds increases), the differential resistance Rds
Increases to the differential resistance Rds', so that the current I
r decreases like the current Ir ′ shown in FIG. As a result, the shunt ratio of the current Ic increases,
As shown in FIG. 3C, the phase of the current It ′ becomes a more advanced phase. Accordingly, the phase of the voltage drop Vrs 'also becomes a leading phase, and as shown in the drawing, the phase of the output signal voltage Vout' becomes a lagging phase of the phase θd 'which is later than the phase of the input signal voltage Vin'.

In this case, the input signal voltage V from the signal source 2
As the level of “in” increases, the differential resistance Rds increases, and the phase of the output signal voltage Vout becomes a later phase. Further, as the level of the input signal voltage Vin from the signal source 2 decreases, the differential resistance Rds decreases, and the output signal voltage Vds
The phase delay amount of out decreases. in this way,
According to the level of the input signal voltage Vin from the signal source 2,
The delay phase amount of the pre-distortion circuit 1 can be varied. This makes it possible to compensate for the phase of the saturating amplifier 3, which is the leading phase amplifier. When the bias voltage Vgs of the bias voltage source 13 applied to the gate electrode of the FET 12 is changed, the differential resistance Rds changes accordingly, and the shunt ratio of the current Ir and the current Ic changes. Thus, by varying the bias voltage Vgs, the amount of delay of the output signal voltage Vout with respect to the input signal voltage Vin can be adjusted.

Summing up the above, the pre-distortion circuit 1 according to the first embodiment of the present invention has the configuration shown in FIG.
Operates as shown in the flowchart of FIG.
Is compensated for the non-linear characteristics of the amplitude and the phase. Referring to the flowchart shown in FIG.
Of the input signal voltage Vin increases (step S
1), the drain-source voltage Vds of the FET 12 increases and the differential resistance Rds increases (step S2), and as a result, the current Ir flowing through the differential resistance Rds decreases (step S3). As a result, the phase delay of the output voltage Vout increases (step S4), and the output voltage Vout having this delay phase is supplied to the saturation amplifier 3. In this case, the phase of the amplified output from the saturation amplifier 3 advances as the level of the input signal increases (step S).
5) After all, the phase change of the amplified output output from the saturation amplifier 3 decreases (step S6). Thereby, the non-linear characteristics of the amplitude and the phase of the saturation amplifier 3 are compensated by the pre-distortion circuit 1, and the linearity is improved (step S7).

FIG. 5 shows a circuit configuration of a predistortion circuit according to a second embodiment of the present invention. The pre-distortion circuit according to the second embodiment is a pre-distortion circuit in a case where an amplifier exhibiting a saturation characteristic is a lag-phase amplifier. An input signal from a signal source 2 is input to an input terminal IN of the pre-distortion circuit 100 shown in FIG. 5, and a saturation amplifier 3 is provided at an output terminal OUT of the pre-distortion circuit 100. The output of the saturation amplifier 3 is supplied to a load resistor RL. When the saturation amplifier 3 is the last stage of the transmitter, the load resistor RL becomes an antenna system. The antenna system generally includes a matching circuit and an antenna. By providing the pre-distortion circuit 100 in front, the saturation amplifier 3 with respect to the input signal from the signal source 2 can be used.
The input / output characteristics of the output signal are substantially linear, and the amount of suppression of the third-order intermodulation distortion component with respect to the carrier signal (IM
3) can be made a sufficient suppression amount.

This pre-distortion circuit 100
A buffer amplifier 11 having a gain of approximately 0 dB and an auxiliary amplifier 14 connected downstream of the buffer amplifier 11 are provided. The input impedance of the buffer amplifier 11 and that of the auxiliary amplifier 14 are matched with the impedance of the input side, and the output impedance is matched with the impedance of the output side. And
The output of the buffer amplifier 11 is input to an auxiliary amplifier 14, and a field effect transistor (FET) 12 is connected between a line to which the output is transmitted and ground. The FET 12 is, for example, an N-MOSFET,
The drain electrode (D) is connected to the line, and the source electrode (S) is connected to the ground. Further, the bias voltage Vgs from the bias voltage source 13 is supplied to the gate electrode (G).

In a field effect transistor, when the drain-source voltage is changed, the change in the drain current has a non-linear characteristic. That is, the differential resistance between the drain and the source with respect to the voltage between the drain and the source changes nonlinearly. The non-linear characteristic of the differential resistance changes depending on the bias voltage Vgs applied to the gate electrode. Predistortion circuit 1 shown in FIG.
No. 00 compensates for the non-linear characteristic of the amplitude of the post-saturation amplifier 3 by utilizing the non-linear characteristic of the differential resistance. Further, a phase compensation inductor Lp is connected in parallel with the FET 12. The predistortion circuit 100 according to the second embodiment of the present invention is characterized by a configuration in which the phase compensation inductor Lp is connected. This phase compensation inductor Lp is connected to the above-described FET.
By connecting in parallel with the differential resistance between the drain and the source having the nonlinear characteristic in 12, the nonlinear characteristic of the phase of the saturation amplifier 3 provided after the pre-distortion circuit 100 is compensated.

FIG. 6 shows an equivalent circuit of the pre-distortion circuit 100. In this equivalent circuit, the FET 12 in the predistortion circuit 100 is shown as a drain-source differential resistance Rds connected in parallel between the input and output. However, since the input / output impedance of the buffer amplifier 11 is matched on the input side and the output side and does not affect the transfer characteristics described later, the buffer amplifier 1
1 is omitted. The internal impedance of the signal source 2 is represented by Rs, and the internal impedance Rs is, for example, 50Ω. Further, the input impedance of the auxiliary amplifier 14 is represented by RL, and the input impedance RL is, for example, 50Ω. Here, assuming that a parallel impedance obtained by connecting the differential resistance Rds, the phase compensation inductor Lp, and the input impedance RL in parallel is Zp, the input / output transfer characteristic G of the predistortion circuit 100 is expressed by the following equation. G = Zp / (Rs + Zp) (4) However, in the equation (4), the impedance Zp is expressed by the following equation. Zp = 1 / {(1 / Rds) + (1 / jωLp) + (1 / RL)} (5) Rds is a differential resistance between the drain and the source of the FET 12, and is an AC resistance.

The differential resistance Rds between the drain and the source of the FET 12 changes non-linearly according to the voltage level of the signal output from the buffer amplifier 11. As described above, the non-linear characteristic of the amplitude of the saturation amplifier 3 can be compensated for as described above, and the description is omitted here. Next, the principle of phase compensation by the phase compensation inductor Lp will be described with reference to FIG. The pre-distortion circuit 100 shown in FIG. 7A is shown in the equivalent circuit shown in FIG. The pre-distortion circuit 1 shown in FIG.
7B and 7C are vector diagrams showing the phase relationship between the output signal voltage Vout and the input signal voltage Vin from the signal source 2 of FIG. However, current It is a current supplied from the signal source 2, the current Ir is a current shunted to the input impedance RL of the parallel-connected differential resistance Rds an auxiliary amplifier, current I _L in the phase compensating inductor Lp The shunted current. The voltage Vrs is a voltage corresponding to a voltage drop due to the internal resistance Rs of the signal source.

As shown in FIG. 7B, the input signal voltage V
in is divided into a voltage drop Vrs due to the internal resistance Rs and an output signal voltage Vout. Meanwhile, current I _L is delayed 90 ° phase than the current Ir flowing through the resistor from being a current flowing through the inductor, current It is a current I _L
And the current Ir are vector-combined. The voltage drop Vrs becomes a voltage having the same phase as the current It due to the voltage drop due to the internal resistance Rs. As shown in the drawing, the output signal voltage Vout eventually leads the input signal voltage Vin by a phase θf. Here, the level of the input signal voltage Vin increases (the drain voltage of the FET 12).
When the source-to-source voltage Vds increases), the differential resistance Rds
Increases to the differential resistance Rds', so that the current I
r decreases like the current Ir ′ shown in FIG. 7C. As a result, the shunt ratio of the current Ic increases,
As shown in FIG. 7C, the phase of the current It 'is a later phase. Accordingly, the phase of the voltage drop Vrs 'also becomes a lagging phase, and as shown in the figure, the phase of the output signal voltage Vout' becomes a leading phase of the phase θf 'which is earlier than the phase of the input signal voltage Vin'.

In this case, the input signal voltage V from the signal source 2
As the level of in increases, the differential resistance Rds increases, and the phase of the output signal voltage Vout becomes a more advanced phase. Further, as the level of the input signal voltage Vin from the signal source 2 decreases, the differential resistance Rds decreases, and the output signal voltage Vo
The amount of phase advance of ut decreases. As described above, the advance phase amount of the predistortion circuit 1 can be varied according to the level of the input signal voltage Vin from the signal source 2. This makes it possible to compensate for the phase of the saturating amplifier 3, which is an amplifier having a lagging phase. When the bias voltage Vgs of the bias voltage source 13 applied to the gate electrode of the FET 12 is varied, the differential resistance Rds changes accordingly, and the current Ids
shunt ratio of r and current I _L so changed. As described above, by varying the bias voltage Vgs, it becomes possible to adjust the amount of leading phase of the output signal voltage Vout with respect to the input signal voltage Vin.

Summing up the above, the predistortion circuit 100 according to the second embodiment of the present invention operates as shown in the flowchart of FIG. 8 to compensate for the non-linear characteristics of the amplitude and phase of the saturation amplifier 3. I am trying to do it. Referring to the flowchart shown in FIG. 8, when the amplitude of the input signal voltage Vin of the signal source 2 increases (step S11), the drain-source voltage Vd of the FET 12 is increased.
s increases and the differential resistance Rds increases (step S1).
2) As a result, the current Ir flowing through the differential resistance Rds decreases (step S13). Thereby, the output voltage Vou
The phase advance of t increases (step S14), and the output voltage Vout of this advance phase is supplied to the saturation amplifier 3. In this case, the phase of the amplified output from the saturated amplifier 3 is delayed as the level of the input signal is increased (step S15), and the phase change of the amplified output output from the saturated amplifier 3 is reduced after all (step S15). S1
6). Thereby, the non-linear characteristics of the amplitude and phase of the saturation amplifier 3 are compensated by the pre-distortion circuit 100, and the linearity is improved (step S17).

Next, in the predistortion circuit 1 according to the first embodiment of the present invention shown in FIG. 1, the carrier signal of the third-order intermodulation distortion component when the capacitance value of the phase compensation capacitor Cp is changed. Suppression amount (IM3)
9 and the simulation result of the optimum gate-source voltage Vgsopt in the FET 12 are shown in FIG. However, the drain current Id-drain-source voltage Vds characteristics of the FET 12 at this time are as shown in FIG. In addition, FET
A conductance coefficient Kp of 12 is as follows: Kp = 0.2 A / m
² (K = 0.1 A / V ² ) and its threshold voltage Vth
Is set to Vth = 0V.

Referring to FIG. 9, when the input signal power Pin from the signal source 2 is -40 dBm, the single IM3 of the saturation amplifier 3 is about -165 dBm. Here, for example, assuming that the capacitance value of the phase compensation capacitor Cp in the pre-distortion circuit 1 is 30 pF, IM
3 is improved by about 10 dBm to about -175 dBm. Further, when the capacitance value of the phase compensation capacitor Cp is 50 pF, IM3 is improved by about 17 dBm to about -182 dBm. When the capacitance value of the phase compensation capacitor Cp is 70 pF, IM3 is improved by about -193 dBm and about 28 dBm. You. If the capacitance value of the phase compensation capacitor Cp is further increased, IM3 will be increased. That is, the optimum value of the capacitance value of the phase compensation capacitor Cp is about 70 pF.

Next, the optimum value of the capacitance value of the phase compensation capacitor Cp when the input signal power Pin from the signal source 2 is 0 dBm will be verified with reference to FIG. When the input signal power Pin from the signal source 2 is 0 dBm, the single IM3 of the saturation amplifier 3 is set to about -46 dBm. Here, assuming that the capacitance value of the phase compensation capacitor Cp in the pre-distortion circuit 1 is 30 pF, for example,
M3 is improved by about 16 dBm to about -62 dBm. Further, assuming that the capacitance value of the phase compensation capacitor Cp is 50 pF, the amount of improvement of IM3 is slightly reduced to about -59 dBm and about 13 dBm, and the capacitance value of the phase compensation capacitor Cp is reduced to 7 p.
Assuming 0 pF, IM3 is about -65 dBm and about 19 dB
m is also improved. Even if the capacitance value of the phase compensation capacitor Cp is further increased, IM3 will not be further improved. That is, also in this case, the phase compensating capacitor C
The optimum value of p is about 70 pF. in this way,
The optimum value of the phase compensation capacitor Cp that can improve IM3 most is about 70 pF regardless of the input signal level from the signal source 2.

Further, when the capacitance value of the phase compensating capacitor Cp is changed from 0 pF to 90 pF, the optimum gate of the FET 12 which can improve IM3 most can be obtained.
The source-to-source voltage Vgsopt is shown in FIG. Referring to FIG. 9, the capacitance value of the phase compensation capacitor Cp is 0 pF.
In this case, the optimum gate-source voltage Vgsopt is about 1.2 V, and when the capacitance value of the phase compensation capacitor Cp is, for example, 30 pF, the optimum gate-source voltage Vgsopt is about 1.4 V. Further, the optimum gate-source voltage Vgsopt when the capacitance value of the phase compensation capacitor Cp is 50 pF is about 1.3 V, and the optimum gate-source voltage when the capacitance value of the phase compensation capacitor Cp is 70 pF. The voltage Vgsopt is about 0.95V
And the capacitance value of the phase compensation capacitor Cp is 90 pF
In this case, the optimum gate-source voltage Vgsopt is about 0.8V. Thus, the phase compensation capacitor C
The optimum gate-source voltage Vgs that can most improve IM3 when the capacitance value of p is the optimum value of 70 pF.
opt will be about 0.95V.

Next, the case where the phase compensation capacitor Cp is not added and the case where the phase compensation capacitor Cp of 70 pF is added to the pre-distortion circuit 1 according to the first embodiment of the present invention shown in FIG. FIG. 11 shows a simulation result of the phase characteristic of the output signal and the phase characteristic of the output signal of the saturation amplifier 3 provided after the predistortion circuit 1. However, the capacitor C for phase compensation
When p is not added, the gate-source voltage Vgs of the FET 12 is set to about 1.2 V. When the phase compensation capacitor Cp of 70 pF is added, the gate-source voltage Vgs of the FET 12 is about 0. 95V. Vout shown in FIG. 11 is an output signal voltage output from the pre-distortion circuit 1 according to the first embodiment of the present invention as shown in FIG.
ampout is an output signal voltage output from the saturation amplifier 3 as shown in FIG.

Referring to FIG. 11, the phase characteristic of the single saturating amplifier 3 is such that the input power from the signal source 2 is -10 dBm.
From about −21 ° to about −1 as it rises from
The phase advances toward 9 °. That is, the phase is changed so that the phase advances and becomes the phase according to the input power.
In the pre-distortion circuit 1 according to the first embodiment of the present invention shown in FIG. 10, the phase of the output voltage Vout of the pre-distortion circuit 1 when the phase compensating capacitor Cp is not provided is changed from the signal source 2. Is approximately constant at a phase of about −29 ° from −10 dBm to 0 dBm, and changes so that the phase is delayed from about −29 ° to about −32 ° when the input power rises to 2 dBm or more. . Further, the pre-distortion circuit 1 without the phase compensation capacitor Cp as described above.
The phase of the output voltage Vampout of the saturation amplifier 3 in which the input power from the signal source 2 is -10 dBm to 0 dB
m, it is almost constant at a phase of about -21 °,
When the input power increases to 2 dBm or more, the phase changes from about −21 ° to about −18 °.

Then, in the pre-distortion circuit 1 according to the first embodiment of the present invention shown in FIG.
When the phase compensation capacitor Cp is 70 pF, the phase of the output voltage Vout of the predistortion circuit 1 is substantially constant at about -70 ° even when the input power from the signal source 2 rises from -10 dBm to 0 dBm. When the input power rises to 2 dBm or more, the input power increases from about −70 ° to about −72 °.
The phase is delayed toward °. Further, the phase of the output voltage Vampout of the saturation amplifier 3 in which the pre-distortion circuit 1 in which the phase compensation capacitor Cp is set to 70 pF is minus the input power from the signal source 2.
Even when the level increases from 10 dBm to 8 dBm, the phase is substantially constant at about -62 °, and the phase slightly advances when the input power is 9 dBm or more. As described above, the non-linear characteristic of the phase characteristic can be compensated by the pre-distortion circuit 1 according to the first embodiment of the present invention, and the input power becomes about -42 dBm to 2 as shown in FIG.
IM3 can be greatly improved in the range of dBm.

Next, the output power and the third-order intermodulation distortion with respect to the input power from the signal source 2 in the saturation amplifier 3 in which the predistortion circuit 1 according to the first embodiment of the present invention shown in FIG. FIG. 12 is a graph showing the amount of suppression (IM3) of the component with respect to the carrier signal. FIG.
Referring to FIG. 2, the input power from the signal source 2 is −40 dB.
When the input power is 0 dBm, the output power is about 9 dBm when the input power is 0 dBm. Therefore, the saturation amplifier 3 including the pre-distortion circuit 1
Is about 9 dB.

The IM3 of the single saturating amplifier 3 has such a characteristic that the input power from the signal source 2 changes linearly with a change amount of three times the change amount of the input power until the input power from the signal source 2 rises to about -3 dBm. I have. For example, if the input power from the signal source 2 is-
At 5 dBm, IM3 has a suppression amount of about -60 dBm, and when the input power is -40 dBm, IM3 becomes about -165.
The suppression amount is dBm. Further, when the pre-distortion circuit 1 does not include the phase compensation capacitor Cp, the input power from the signal source 2 is about 0 d.
The characteristic is such that it changes linearly with a change amount three times the change amount of the input power until it rises to Bm. For example, when the input power from the signal source 2 is 0 dBm, IM3 is about -50d
Bm, and when the input power is -40 dBm, I
M3 is a suppression amount of about -170 dBm.

Next, when the phase compensation capacitor Cp in the pre-distortion circuit 1 is set to the optimum value of about 70 pF, the input power from the signal source 2 is -40 dB.
m is about 191.7 dBm, and IM3 is reduced to about 21.7 dB by adding the phase compensation capacitor Cp.
Bm can be improved. Further, when the input power from the signal source 2 is -20 dBm, IM3 is approximately -131 dBm.
, And also in this case, the IM3 can be improved by about 21 dBm. Until the input power rises to -7 dBm, IM3 can be improved by about 21 dBm by adding the phase compensation capacitor Cp. Note that IM3 can be improved by about 13 dBm even if the input power from the signal source 2 increases to 0 dBm.
As described above, the addition of the phase compensation capacitor Cp makes it possible to compensate for the non-linear characteristic of the phase in the saturation amplifier 3, and further reduces the IM3 by about 21d
Bm or more can be improved.

FIGS. 9 to 12 described above illustrate the operation and effect of the phase compensation by the predistortion circuit 1 according to the first embodiment of the present invention shown in FIG. FIG. 5 in front of the saturation amplifier 3 in which the phase of the output voltage is delayed as the voltage increases.
In the pre-distortion circuit 100 according to the second embodiment of the present invention shown in FIG.

Note that the FET 12 in the pre-distortion circuit of the first and second embodiments
Is not limited to an N-channel MOSFET, but may be a P-channel MOSFET. In addition, the present invention is not limited to the MOS type, but is applicable to MIS (Metal Insula).
tor Semiconductor), MES (Metal)
Semiconductor), SIT (Static induction Transi)
stor) or any other junction type. Furthermore, bipolar transistors and HEMTs (High Electron Mobility Transistors) are used instead of field effect transistors.
r) or Heterojunction Bipolar Transistor (HBT).

[0047]

As described above, according to the present invention, the amplitude is compensated by using the non-linear characteristic of the transistor.
Since the phase can be compensated by the interaction with the phase compensating capacitor or the phase compensating inductor connected in parallel with the transistor, a pre-distortion circuit that can compensate not only the amplitude but also the non-linear characteristic of the phase is provided. can do. Also, since the non-linear characteristics of the transistor can be changed by the bias voltage applied to the control electrode, by using a bias voltage source as a variable voltage source, the amount of phase and amplitude compensation can be adjusted, and the best compensation can be achieved. Will be able to do it.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a circuit configuration of a predistortion circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating an equivalent circuit of a predistortion circuit according to the first embodiment of the present invention.

FIG. 3 is a diagram for explaining a principle of performing phase compensation by a phase compensation capacitor in the predistortion circuit according to the first embodiment of the present invention.

FIG. 4 is a flowchart showing an operation of the pre-distortion circuit according to the first embodiment of the present invention.

FIG. 5 is a circuit diagram showing a circuit configuration of a predistortion circuit according to a second embodiment of the present invention.

FIG. 6 is a diagram illustrating an equivalent circuit of a predistortion circuit according to a second embodiment of the present invention.

FIG. 7 is a diagram for explaining a principle of performing phase compensation by a phase compensation inductor in a predistortion circuit according to a second embodiment of the present invention.

FIG. 8 is a flowchart illustrating an operation of the pre-distortion circuit according to the second embodiment of the present invention.

FIG. 9 is a diagram illustrating IM3 characteristics with respect to phase compensation capacitance in a saturation amplifier in which a predistortion circuit according to the first embodiment of the present invention is provided.

FIG. 10 is a circuit diagram showing a configuration of a saturation amplifier in which a pre-distortion circuit is provided before the pre-distortion circuit in FIG. 11 showing a phase characteristic with respect to input power in the pre-distortion circuit and the saturation amplifier of the first embodiment of the present invention is there.

FIG. 11 is a diagram illustrating phase characteristics with respect to input power in the pre-distortion circuit and the saturation amplifier according to the first embodiment of the present invention.

FIG. 12 is a diagram illustrating output power and IM3 characteristics with respect to input power in a saturation amplifier in which a predistortion circuit according to the first embodiment of the present invention is provided.

FIG. 13 is a diagram showing a drain current characteristic with respect to a drain-source voltage of an FET in a predistortion circuit according to the present invention.

FIG. 14 is a diagram showing a circuit configuration of a pre-distortion circuit proposed by the present applicant.

FIG. 15 is a diagram showing an equivalent circuit of a pre-distortion circuit proposed by the present applicant.

FIG. 16 is a diagram showing Id-Vds characteristics of an FET and characteristics of a differential resistor Rds with respect to a drain-source voltage Vds in a predistortion circuit proposed by the present applicant.

FIG. 17 is a diagram illustrating a loss characteristic with respect to an input signal amplitude in a predistortion circuit proposed by the present applicant.

FIG. 18 is a flowchart showing an operation of a pre-distortion circuit proposed by the present applicant.

FIG. 19 is a diagram showing output power characteristics with respect to input power in a predistortion circuit proposed by the present applicant.

[Explanation of symbols]

 1,100,200 Predistortion circuit 2,202 Signal source 3 Saturation amplifier 11,211, Buffer amplifier 13,214 Bias voltage source 14,213 Auxiliary amplifier 203 Power amplifier Cp Phase compensation capacitor IN Input terminal Lp Phase compensation inductor OUT Output Terminal RL Load resistance, input impedance of auxiliary amplifier Rs Internal resistance of signal source

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5J090 AA01 AA41 CA21 CA26 FA10 FA19 GN03 HA02 HA06 HA10 HA12 HA25 HA29 HA33 KA03 KA12 SA14 TA02 TA07 5J091 AA01 AA41 CA21 CA26 FA10 FA19 HA02 HA06 HA10 HA12 HA25 HA29 HA33 KA03 KA03 SA12 TA07

Claims (5)

[Claims] 1. A pre-distortion circuit provided before an amplifier for compensating for nonlinear characteristics of the amplifier, wherein the transistor is connected between a line connecting an input terminal and an output terminal and a ground. A pre-distortion circuit comprising: a bias voltage source for applying a predetermined bias voltage to a control electrode of the transistor; and a phase compensation capacitor connected in parallel with the transistor. 2. A pre-distortion circuit provided before an amplifier for compensating for non-linear characteristics of the amplifier, wherein the transistor is connected between a line connecting an input terminal and an output terminal and ground. And a bias voltage source for applying a predetermined bias voltage to a control electrode of the transistor; and a phase compensation inductor connected in parallel with the transistor. 3. The transistor is a field effect transistor, the drain electrode of which is connected to the line,
3. A predistortion circuit according to claim 1, wherein said source electrode is connected to ground. 4. A buffer amplifier is inserted between a line to which the input terminal and the transistor are connected, and an amount of attenuation by the transistor between a line to which the transistor is connected and the output terminal. 3. A pre-distortion circuit according to claim 1, further comprising an auxiliary amplifier for compensating for the difference. 5. The pre-distortion circuit according to claim 1, wherein the bias voltage source is a variable voltage source so that the amount of nonlinear compensation can be adjusted.