JP2001267328A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can reduce the collector resistance of a bipolar transistor having an intrinsic emitter region, intrinsic base region and intrinsic collector region arranged in the vertical direction in a thin SOI layer of several tens to several hundreds of nanometers, and avoid deteriorating characteristics due to current concentration on the intrinsic collector region. SOLUTION: The semiconductor device (5, 6, 8, 18), provided in a semiconductor layer on an insulation film (1) through which a current flows in the thickness direction of the semiconductor layer and comprises a conductive layer (17) which adjoins the semiconductor device and is embedded in the insulation film, and an electrode (29) electrically connected to the conductive layer, and the current flows to the electrode via the interface between the semiconductor device and the conductive layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bipolar transistor, and more particularly, to a transistor in which an intrinsic emitter, an intrinsic base, and an intrinsic collector of a transistor are vertically arranged in a thin film semiconductor layer having a thickness of about several tens nm to several hundreds nm on an insulating layer. Vertical SOI-bipolar transistor.

[0002]

2. Description of the Related Art In recent years, a so-called SOI (Silicon) has been developed.
On Insulator) With the progress of substrate technology,
The development of LSI chips mainly composed of MOS transistors on a thin film SOI layer having a thickness of about several tens nm to several hundreds nm has been activated. This is because, when a MOS transistor is formed on a thin film SOI layer, the source / drain diffusion layers can be formed so as to reach the buried insulating film, thereby reducing the junction capacitance. However, this is because there is an advantage that the circuit can be speeded up and power consumption can be reduced by about several tens of percent compared to a normal Bulk substrate.

On the other hand, in recent years, the market for wireless communication devices has expanded, and the demand for chips having an RF (Radio Frequency) function has increased dramatically. R
Bipolar transistors are mainly used as the transistors that make up the F circuit, and high-speed operation can cope with an increase in the frequency band and low power consumption for application to battery-backed devices such as mobile phones. It becomes important.

As described above, in the future, a MOS transistor will be formed on a thin film SOI layer.
As the importance of an LSI chip on which a transistor is formed increases, a technique for forming a high-speed and low-power-consumption bipolar transistor on the same thin-film SOI layer becomes important.

Referring to FIG. 12, a bipolar transistor structure formed on a thin-film SOI layer of Conventional Example 1 and its problems will be described. The structure disclosed in US Pat. No. 5,087,580 discloses that an n ⁺ -type intrinsic emitter 74 has a p ⁺ -type base 71 as an external base region and an n ⁺ -type collector 75 as an external collector region on both sides. Are provided separately. In such a structure, an n ⁺ -type emitter 73 as an external emitter region is regarded as a gate electrode, and sources and drains having different impurity types are provided on both sides thereof.
Since it has a structure like a MOS transistor, the compatibility with the process of the MOS transistor is good, and the process can be shortened. Further, since the diffusion layers of the external base 71 and the external collector 75 reach the buried insulating film (not shown) by being formed on the thin film SOI layer, the external base 71, the external collector 75, the external base 71 and the intrinsic collector 71 Since the respective parasitic capacitances between the capacitors 76 can be reduced, the structure is convenient for high speed and low power consumption.

However, since the external collector 75 is not located immediately below the intrinsic emitter 74, the intrinsic base 72, and the intrinsic collector 76, which are the intrinsic regions of the device, there is a problem that the collector resistance tends to increase. In addition, the intrinsic collector 7
The current flowing from 6 to the external collector 75 tends to pass through the shortest distance in a portion bent into an L-shape, causing current concentration, further increasing the collector resistance and remarkably reducing fT due to the so-called Kirk effect. It was difficult to raise the speed.

On the other hand, USP-
The structure disclosed in US Pat. No. 5,102,809 is a conventional bipolar transistor formed as a thick film having a thickness of about 1 μm or more on an insulating layer (not shown) as it is. In this structure, n and n ⁺ -type collector 85 is an external collector region significant speed performance degradation for forming the intrinsic region directly under the transistor does not occur, but rather, the conventional p-type bulk transistor on the substrate ⁺ Since the mold collector 85 is formed in contact with the insulating layer (not shown), the parasitic capacitance between the collector and the substrate can be reduced, and high speed and low power consumption may be achieved.

However, in this structure, since the p ⁺ -type base 81 and the n ^-- type intrinsic collector 86 are overlapped in the film thickness direction, the structure of the conventional example 1 described in US Pat. By comparison, the base,
The collector and the parasitic capacitance between the two are large, which is not ideal for high-speed operation and low power consumption. Also,
In the bipolar transistor structure of Conventional Example 2, a thick S of about 1 μm or more is mainly used for the external collector 85 and the like.
Since the OI layer is required, the thickness is several tens nm to several tens nm.
There is also a problem that the process compatibility with a MOS transistor formed on a thin film of about 0 nm is poor.

When the bipolar transistor of the prior art 2 shown in FIG. 13 is to be formed on a thin SOI layer having a thickness of several tens to several hundreds of nm, an n-type intrinsic emitter region 84 which is an intrinsic region of the transistor, a p-type intrinsic base The thicknesses of the region 82 and the n ⁻ -type intrinsic collector region 86 are important parameters for determining the breakdown voltage of the transistor, and cannot be changed unnecessarily. Therefore, when the bipolar transistor of Conventional Example 2 is formed on a thin film SOI layer, it is necessary to reduce the thickness of the n ⁺ -type external collector region 85 immediately below the intrinsic collector region 86. When the external collector region 85 is made thinner, the external collector region can be formed only on the lateral side of the intrinsic collector region like the bipolar transistor of the conventional example 1 shown in FIG. The same problem occurs. Even if the external collector region remains immediately below the intrinsic collector region, the external collector region in this case is very thin, and the external collector region immediately below the intrinsic collector region has a high resistance. The current flows to the external collector region on the side of the intrinsic collector region, and the same current concentration as in the first conventional example occurs.

[0010]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a thin film SOI layer having a thickness of about several tens to several hundreds of nm, in which an intrinsic emitter region, an intrinsic base region and an intrinsic collector region of a transistor are vertically arranged. Bipolar
It is an object of the present invention to reduce the collector resistance of a transistor and to prevent characteristic deterioration due to current concentration in the intrinsic collector region.

[0011]

According to a first aspect of the present invention, there is provided a semiconductor device provided on a semiconductor layer on an insulating film, wherein a current flows in a thickness direction of the semiconductor layer. A conductive layer embedded in an insulating film; and an electrode electrically connected to the conductive layer, wherein the current flows to the electrode via an interface between the semiconductor device and the conductive layer. Semiconductor device.

According to a second aspect of the present invention, there is provided a first conductive type second semiconductor layer provided in a first semiconductor layer on an insulating film and selectively formed on the insulating film side. A third semiconductor layer formed on the second semiconductor layer and having the same conductivity type as the second semiconductor layer and having a low impurity concentration;
A fourth semiconductor layer of a second conductivity type provided in the first semiconductor layer and formed on the third semiconductor layer; and a fourth semiconductor layer provided in the first semiconductor layer and provided on the fourth semiconductor layer. Contacting the first conductive type fifth semiconductor layer and the second semiconductor layer,
A semiconductor device including a conductive layer embedded in the insulating film and an electrode electrically connected to the conductive layer.

A third invention of the present application is the semiconductor device according to the second invention of the present application, characterized in that the first semiconductor layer has a thickness of several tens to several hundreds nm.

According to a fourth aspect of the present invention, there is provided the semiconductor device according to the second aspect, wherein the conductive layer comprises a composite layer of a silicon layer and tungsten.

According to a fifth aspect of the present invention, there is provided a sixth semiconductor provided in the first semiconductor layer, electrically connected to the fourth semiconductor layer, having the same conductivity type as the fourth semiconductor layer and having a high impurity concentration. A semiconductor device according to a second aspect of the present invention, comprising a layer.

The sixth invention of the present application is the semiconductor device according to the fifth invention, wherein a depletion layer extending from the sixth semiconductor layer is in contact with the insulating film.

According to a seventh aspect of the present invention, there is provided the semiconductor device according to the fifth aspect, wherein the sixth semiconductor layer is in contact with the insulating film.

According to an eighth aspect of the present invention, there is provided a step of forming a first semiconductor layer on an insulating film, and forming a second semiconductor layer of a first conductivity type and a third semiconductor layer of a second conductivity type on the first semiconductor layer in order from the bottom. Forming an intrinsic transistor portion composed of three layers of a semiconductor layer and a first conductive type fourth semiconductor layer; and etching a position of the first semiconductor layer different from the intrinsic transistor portion;
Exposing the insulating film, isotropically etching the exposed insulating film, exposing a lower surface of the fourth semiconductor layer, and contacting the lower surface of the fourth semiconductor layer.
Embedding a conductive layer in the isotropically etched insulating film; and forming a fifth semiconductor layer having the same conductivity type and a high impurity concentration as the fourth semiconductor layer below the fourth semiconductor layer. And a step of forming an electrode electrically connected to the conductive layer.

The present invention relates to the above-mentioned USP-508758.
0, which is provided in the lateral (planar) direction with respect to the intrinsic regions of the emitter, base, and collector formed on the thin film SOI, and An external base provided so that the bottom or a depletion layer extending from the bottom reaches the buried insulating layer, and an intrinsic region is provided so that at least a part thereof has an overlapping region in the thickness direction, and the external base is in the thickness direction. And an external collector provided so as not to have an overlap.

In order to enable the above structure, an external collector is provided in a self-aligned manner with respect to the intrinsic region of the transistor, and a part of the conductor is buried in a region of the SOI substrate where the buried insulating film is etched. It is formed by using.

According to the present invention, since the external collector is disposed so as to overlap with the intrinsic region in the depth direction, problems such as an increase in the collector resistance and an increase in the Kirk effect occur from the intrinsic collector to the external collector. Does not occur. Further, the advantage of the structure that can reduce the external base, the external collector, and the parasitic capacitance between them is not lost. Further, by forming a part of the external collector region buried in the buried insulating film, the thickness of the external collector region in the SOI layer can be reduced to the minimum necessary. B is suppressed to several hundred nm level
It can be formed without any problem with the compatibility with the MOS process when iCMOS is used. Thus, a chip with high speed, low power consumption and low cost can be realized.

[0022]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view showing an embodiment of the present invention. That is, the SOI layers having the same thickness are used for the MOS transistor portion and the bipolar transistor portion. Here, the silicon layer provided on the buried insulating film (hereinafter, simply referred to as an insulating film) 1 is called an SOI layer. The thickness of the SOI layer will be described later. The source region 19 and the drain region 20 of the MOS transistor and the n-type external base region 25 of the bipolar transistor are formed so as to reach the insulating film 1 and the parasitic capacitance is reduced. Further, as a feature, the collector buried region 17 of the bipolar transistor is formed in a laterally self-aligned manner with respect to the n-type intrinsic emitter 8, the p-type intrinsic base 6, and the n-type intrinsic collector 5, which are the intrinsic regions of the transistor. As described above, the conductor made of poly silicon or the like buried so as to make contact from the back surface of the SOI layer exposed by removing the insulating film 1 by etching, and the diffusion layer n formed by impurity diffusion from the back surface. It is formed by the mold external collector region 18. Since the external collector region 18 is immediately below the intrinsic region of the transistor, the current flowing from the intrinsic region of the transistor to the external collector region 18 flows straight in the thickness direction of the SOI layer. That is, the current flowing through the intrinsic region of the transistor passes through the interface between the external collector region 18 and the collector buried region 17 so that the collector extraction electrode 2
9, the structure is such that current concentration hardly occurs in the intrinsic collector region. Also, the distance between the base for determining the breakdown voltage and the n-type collector buried region 17 can be set uniformly without any deviation in the lateral direction. If the external collector region 18 covers at least half of the lower surface of the intrinsic region of the transistor, the current flowing from the intrinsic region to the external collector region flows perpendicular to the insulating film 1.

FIG. 2 is a graph showing simulation results of performance comparison between the bipolar transistor described with reference to FIG. 1 and the bipolar transistor of the conventional example 1 shown in FIG. n ⁺ type intrinsic emitter (film thickness 30n
m) (E in FIG. 2), p-type intrinsic base (film thickness 110 n)
m), the concentration of the n-type intrinsic collector (film thickness 250 nm), the concentration of the n ⁺ -type external collector (film thickness 30 nm) (C in FIG. 2) and the concentration of the external base (B in FIG. 2) are 5 × 10 ²¹ and 2 ×, respectively. 1
0 ¹⁸ , 1 × 10 ¹⁷ , 5 × 10 ²⁰ and 5 × 10 ²⁰ cm ⁻³ . The depth of the junction between the intrinsic emitter and the intrinsic base and the junction between the intrinsic base and the intrinsic collector was 30 nm and 110 nm from the surface of the semiconductor layer, respectively, as in the case of a conventional bipolar transistor with a bulk semiconductor layer (1 μm thick). . In addition, the minimum distance between the intrinsic base and the external collector was set to 250 nm in order to make the breakdown voltage of both of them equal. As a result, the SOI film thickness is about 400 nm. The SOI film thickness is SOI-MOSFET
Is preferably several tens to 500 nm in view of compatibility with the process. In addition, simulation was performed assuming two types of intrinsic emitters (E in FIG. 2) having an emitter width We of 0.15 μm and 0.3 μm.

In the conventional example 1 in which the external collector is drawn laterally, the cut-off frequency f _T drops at a low current due to an increase in the collector resistance and the Kirk effect, and the situation fluctuates greatly depending on the emitter width. You can see that In contrast, in the structure of the present invention, the conventional example 1 to about 1 digit f _T to a large collector current region nearly continues to rise with respect to only the emitter width We can be varied simply the current level parallel shift in, f _T, it can be seen that almost unchanging high performance is obtained.

Next, a manufacturing process of the bipolar transistor according to the present embodiment will be described with reference to FIGS.
When the effect of reducing the parasitic capacitance is used, the SOI film thickness is desirably within the thickness of the diffusion layer of the source / drain or the external base. MOS transistors are nMOS or pMO
Both S are conceivable, and are not specified here. Although the process conditions are shown assuming the npn type for the bipolar transistor, it is clear that the pnp type or both can be formed identically by changing the ion species.

First, as shown in FIG. 3, a known STI (S
A silicon oxide film, a silicon nitride film, or a composite film with a silicon oxide film such as poly silicon is buried in a groove portion where the SOI layer on the insulating layer 1 is selectively etched and removed by using, for example, a hallow trench isolation method. Region 2 is formed. Next, an impurity layer having the same impurity concentration as the intrinsic collector region 5 and an impurity layer having the same impurity concentration as the intrinsic base region 6 are formed by a desired method. The collector 5 can be formed to have a desired profile in the depth direction by ion-implanting n-type impurities such as phosphorus, arsenic, and antimony under a plurality of conditions as necessary. Can be formed using the low accelerating voltage. MOS
Can also be performed at this timing, and the process can be shortened by partially sharing it with a collector or the like. Next, a gate insulating film 3 having a thickness of several nm to several tens nm.
And a gate electrode 11 are formed. At this time, by using poly silicon having a thickness of several hundred nm as the gate electrode material, the emitter poly structure serving as the external emitter region 10 of the bipolar portion can be formed simultaneously with the gate electrode.
However, usually, in order to reduce the parasitic capacitance between the emitter poly and the base diffusion layer, in the bipolar region, it is necessary to form the emitter poly through the thick insulating film 7 of several tens nm or more. In addition to forming a thicker insulating film in the bipolar region, an emitter opening is also formed in order to form the intrinsic emitter region 8. NMOS to gate poly and emitter poly
, PMOS or npn bipolar and pnp bipolar, etc., and then ion-implanting the necessary impurities, respectively, and then doping. Then, a silicon nitride film required in a later step of forming a collector hole and a step of forming a buried layer poly described later. Of protective films 11 and 12 are laminated and patterned together with poly silicon. In the present embodiment, the case where the MOS transistor is an LDD transistor is described. Therefore, the impurity layer 13 is formed by ion-implanting impurities. The impurity layer 13 may be formed after the etching of the SOI layer described with reference to FIG.

Next, as shown in FIG. 4, the resist pattern 1 partially overlaps the external emitter region.
By performing anisotropic etching of the SOI layer with the use of 5, a hole for taking out the collector is formed in the SOI layer in a self-aligned manner with respect to the external emitter region, and the insulating film 1 is exposed. The silicon nitride film 12 previously formed on the gate electrode
Thereby, the external emitter region 10 is protected. That is,
In this case, the protective film needs to be a silicon nitride film or a silicon oxide film having a large selectivity to silicon etching.

Next, as shown in FIG. 5, a sidewall insulating film 14 such as a silicon nitride film is deposited on the entire surface. Then, FIG.
As shown in FIG. 7, anisotropic etching is performed using the resist 15 'as a mask to expose the buried insulating film 1 at the bottom of the collector hole again. Thereafter, using the protective film 12 and the sidewall insulating films 14 and 16 on the partially exposed external emitter region as a mask, the hole bottom is formed by isotropic etching such as an ammonium fluoride solution or a hydrofluoric acid solution by wet etching. The back surface of the SOI layer immediately below the intrinsic region is exposed by isotropically etching the exposed buried insulating film (the oxide film in this embodiment). When a normal ammonium fluoride solution is used, the etching rate is 100 nm / min.
It is possible to easily expose the necessary back surface area in about 5 minutes. In this case, in order to protect the side surface of the external emitter region with a sidewall insulating film and the upper portion with a protective film or a sidewall insulating film, it is necessary to use a film which is not etched by an ammonium fluoride solution such as a silicon nitride film. .

Further, by depositing n-type doped poly silicon or doping the deposited poly silicon with n-type impurities such as arsenic, phosphorus, and antimony by ion implantation or the like and applying a thermal process, the intrinsic silicon from the back surface of the SOI layer can be formed. The external collector region 18 extending to the region side is formed, and the poly is etched back to form the buried layer p.
The poly can be embedded in the collector hole (FIG. 7). At this time, SOI is performed using selective epitaxial technology.
It is also possible to grow an epitaxial layer from the backside of the layer over the buried insulating film etching region to the collector hole.

After that, as shown in FIG.
Similarly to the S process, the side wall insulating film 14 is anisotropically etched to leave the side walls, and the source / drain diffusion layers 19 and 20 are formed. The external base region 25 of the bipolar transistor also has a p
A mold diffusion layer is formed. At this time, the source and drain of the pMOS can also be used as a process. The source / drain regions are made of TiSi ₂ using a salicide process or the like.
It is possible to reduce the resistance by silicide (21, 22) such as CoSi ₂ or CoSi _{2. In} this case, the salicide process is similarly applied to both surfaces of the external base region and the polycrystalline silicon buried in the external collector portion. 23, 24) can be formed to reduce the resistance. After this, the conventional interlayer insulating film 26 process, contact and wiring process (2
7, 28, 29, 30), the main part of the BiCMOS device can be formed.

As described above, a high performance vertical bipolar transistor on a thin film SOI can be formed by a process having good matching with the MOS transistor.

In this embodiment, although the thickness of the thin film SOI is not particularly mentioned, the recent gate length is 0.25 μm.
In the case of a fine MOS transistor having a thickness of about 0.15 μm or less, the depth of the source / drain diffusion layer is generally about 0.15 μm or less.
For example, the 400 nm film thickness setting used in the simulation of FIG. 3 is necessary to form an intrinsic region of a bipolar transistor, but may not be practical at the same time to realize a low parasitic capacitance of a MOS transistor. .
In such a case, it is usually conceivable to perform a process of selectively thinning only the MOS transistor portion. However, here, other methods will be described.

FIG. 9 shows a case where the thickness of the SOI layer is larger than the depth of the source / drain diffusion layers. However, SOI
The growth of the depletion layer 41 from the source / drain is made to be 0.2 μm or more by using a high resistance substrate having a low impurity concentration or adjusting the layer by doping. However, by doping the channel region of the transistor to a desired concentration, the transistor characteristics do not deteriorate.
For example, in the case of a general high-resistance substrate having a specific resistance of about 1000 Ω · cm, the impurity concentration is 1 × 10 ¹⁴ cm ⁻³ or less, and a depletion layer of about 1 μm extends. Low capacity can be maintained without any problem. In such a case, since the depletion layer 42 from the external base extends similarly to the depletion layer 41, the external base diffusion layer does not need to be a deep diffusion layer reaching the buried insulating film.

FIG. 10 shows that the thickness of the SOI layer is MOS.
The source / drain of the part is set to the value that reaches the buried insulating film, but in the bipolar transistor part, in order to secure the breakdown voltage between the emitter and collector and between the base and collector
It is necessary to further increase the film thickness, and it is additionally formed by using an epitaxial growth layer or the like. At this time, SO
As to which region is to be formed in the I layer and which region is to be additionally formed in the epitaxial layer or the like, a predetermined SOI
Various combinations are conceivable depending on the thickness of the layer.
Here, the external base region is formed using an epitaxial growth layer from the front surface, and a part of the external collector region or the intrinsic collector region is formed on an epitaxial growth layer (silicon growth layer) 54 provided on the back side of the SOI layer.
Formed. As a result, the difference in surface height from the MOS portion on the front surface side can be reduced, and thus the contact portion and the wiring process can be formed without any change from the usual. In addition, formation of a base region with a SiGe layer (not shown) by an epi technique can be appropriately performed.

Further, in the bipolar transistor of the present embodiment in which the epitaxial layer can be formed from the front surface and the back surface, as shown in FIG. 11, the front side of the SOI layer is the external collector region 65 and the back side is the intrinsic emitter region. 62
Is also possible. In this case, the external base 67
In order to reduce the base resistance, it is preferable to shorten the distance from the intrinsic base. For this reason, for example, as shown in the figure, it is preferable that the profile becomes closer to the intrinsic region as the depth increases. This can be formed by oblique ion implantation (from the right side in the drawing) or the like.

The collector buried region is po
Not limited to the ly silicon layer, a low-resistance material can be used as long as the film is formed by a growth method with good coverage such as a CVD method or a plating method. For example, a conductive layer such as tungsten by a CVD method or a composite film of a silicon layer and tungsten can be used. In this case, the doped Si
It is desirable to form an external collector in advance using a layer selective growth technique or the like.

According to the above-described embodiment of the present invention, the performance of MOS and bipolar transistors is improved by utilizing the low parasitic capacitance of the thin film SOI, and the process matching is improved.・
A low-cost communication LSI can be realized.

[0038]

According to the present invention, the thickness is several tens nm to several tens.
The collector resistance of the bipolar transistor in which the intrinsic emitter region, the intrinsic base region and the intrinsic collector region of the transistor are vertically arranged in the thin film SOI layer of about 00 nm, and the current concentration in the intrinsic collector region Characteristics deterioration can be prevented.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view of a bipolar transistor according to an embodiment of the present invention.

FIG. 2 is a graph showing the relationship between the collector current and the cutoff frequency of the bipolar transistor according to the embodiment of the present invention and the bipolar transistor of Conventional Example 1;

FIG. 3 is a schematic cross-sectional view of a manufacturing process of the bipolar transistor according to the embodiment of the present invention.

FIG. 4 is a schematic cross-sectional view of a manufacturing process of the bipolar transistor according to the embodiment of the present invention.

FIG. 5 is a schematic cross-sectional view of a manufacturing process of the bipolar transistor according to the embodiment of the present invention.

FIG. 6 is a schematic cross-sectional view of a manufacturing process of the bipolar transistor according to the embodiment of the present invention.

FIG. 7 is a schematic cross-sectional view of a manufacturing process of the bipolar transistor according to the embodiment of the present invention.

FIG. 8 is a schematic cross-sectional view of a manufacturing process of the bipolar transistor according to the embodiment of the present invention.

FIG. 9 is a schematic cross-sectional view of a bipolar transistor according to an embodiment of the present invention.

FIG. 10 is a schematic cross-sectional view showing a manufacturing process of the bipolar transistor according to the first modification of the embodiment of the present invention.

FIG. 11 is a schematic cross-sectional view of a manufacturing process of a bipolar transistor according to Modification 2 of the embodiment of the present invention.

FIG. 12 is a schematic cross-sectional view of a bipolar transistor of Conventional Example 1.

FIG. 13 is a schematic cross-sectional view of a bipolar transistor of Conventional Example 2.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 (embedded) insulating film 2 element isolation region 3 gate insulating film 4 channel region 5 intrinsic collector region 6 intrinsic base region 7 insulating film 8 intrinsic emitter region 9 gate electrode 10 external emitter region 11 gate electrode forming mask 12 external emitter region formation Mask 13 n ^- Impurity layer 14 Side wall insulating film 15, 15 ′ Resist 16 Side wall insulating film 17 Collector buried region 18 External collector region 19 Source region 20 Drain region 21, 22, 23, 24 Silicide such as TiSi ₂ or CoSi ₂ 25 External base region 26 Interlayer insulating film 27 Source extraction electrode 28 Drain extraction electrode 29 Collector extraction electrode 30 Base extraction electrode 41 Depletion layer extending from source / drain 42 Depletion layer extending from external base region 52 External base region 53 Collector filling Write area 54 silicon growth layer 55,56,57,58,59 TiSi2 and CoSi
Silicide 61 Emitter buried region 62 Intrinsic emitter region 63 Intrinsic base region 64 Intrinsic collector region 65 External collector region 66 Collector electrode 67 External base region 71, 81 External base region 72, 82 Intrinsic base region 73, 83 External emitter region 74, 84 Intrinsic emitter region 75, 85 External collector region 76, 86 Intrinsic collector region

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H01L 21/8249 H01L 29/44 B 27/12 29/50 B 29/41 29/78 613Z 29/417 29 / 786 (72) Inventor Tomoaki Shino 8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Prefecture F-term in the Toshiba Yokohama Office (Reference) 4M104 AA09 BB01 BB18 BB20 BB25 CC01 DD04 DD15 DD16 DD43 DD50 DD52 DD53 DD55 DD65 DD82 DD84 EE09 EE17 FF02 FF04 FF21 GG06 GG09 GG10 GG14 GG15 HH16 5F003 AP01 AP05 AZ03 BA27 BA29 BA91 BA96 BB08 BC01 BC02 BC05 BC07 BC08 BE07 BG03 BG10 BH11 BH18 BJ15 BP31 BP93 BP94 BP97 CA08 BF97 A0815F07A08 AA06 AA10 AA33 BA06 BA21 BA22 BA26 BA39 BA47 BA50 BC09 DA03 DA10 EA15 EA16 EA22 5F110 AA02 AA03 AA09 CC02 DD05 DD13 EE09 EE32 GG02 GG25 HK05 HM15 NN62 NN71 QQ 08

Claims (8)

[Claims] 1. A semiconductor device provided on a semiconductor layer on an insulating film, wherein current flows in a thickness direction of the semiconductor layer, wherein the conductive layer is in contact with the semiconductor device and embedded in the insulating film; A semiconductor device having an electrode electrically connected to a conductive layer, wherein the current flows to the electrode via an interface between the semiconductor device and the conductive layer. 2. A semiconductor device comprising: a first semiconductor layer on an insulating film;
A second semiconductor layer of a first conductivity type selectively formed on the insulating film side; a second semiconductor layer provided in the first semiconductor layer and formed on the second semiconductor layer and having the same conductivity as the second semiconductor layer; A third semiconductor layer having a low impurity concentration, a fourth semiconductor layer of a second conductivity type provided in the first semiconductor layer and formed on the third semiconductor layer; A fifth semiconductor layer of the first conductivity type provided on the fourth semiconductor layer; a conductive layer in contact with the second semiconductor layer and embedded in the insulating film; A semiconductor device comprising an electrode connected to the semiconductor device. 3. The method according to claim 1, wherein the first semiconductor layer has a thickness of several tens to several tens.
3. The semiconductor device according to claim 2, wherein the thickness is 00 nm. 4. The semiconductor device according to claim 2, wherein said conductive layer comprises a composite layer of a silicon layer and tungsten. 5. A semiconductor device comprising: a sixth semiconductor layer provided in the first semiconductor layer, electrically connected to the fourth semiconductor layer, having the same conductivity type as the fourth semiconductor layer and having a high impurity concentration. 3. The semiconductor device according to claim 2, wherein: 6. The semiconductor device according to claim 5, wherein a depletion layer extending from said sixth semiconductor layer is in contact with said insulating film. 7. The semiconductor device according to claim 5, wherein said sixth semiconductor layer is in contact with said insulating film. 8. A step of forming a first semiconductor layer on an insulating film; and forming a first conductive type second semiconductor layer, a second conductive type third semiconductor layer, and a first conductive layer on the first semiconductor layer in order from the bottom. 4th of conductivity type
Forming a three-layer intrinsic transistor portion of a semiconductor layer; etching a portion of the first semiconductor layer different from the intrinsic transistor portion to expose the insulating film; Isotropically etched, said fourth
Exposing a lower surface of the semiconductor layer; burying a conductive layer in the isotropically etched insulating film so as to be in contact with the lower surface of the fourth semiconductor layer; A method of manufacturing a semiconductor device, comprising: forming a fifth semiconductor layer having the same conductivity type as the fourth semiconductor layer and having a high impurity concentration; and forming an electrode electrically connected to the conductive layer.