JP2001265592A - Information processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an information processor for operating based on the result of comparing fast in an SIMD instruction for storing plural pieces of data on a register and batch operating the plural pieces of data. SOLUTION: On performing a condition performing instruction, data designated by an operand is divided into the plural pieced of data by each specific number of bits, and the corresponding verifying result of a state holding means corresponding to each of the divided plural pieces of data is examined. The processor is controlled to perform operation designated in the instruction to corresponding divided data when a condition is formed, and to avoid performing the operation designated in the instruction to the corresponding divided data when the condition is not formed. Thus, with respect to the respective data divided plurally, the condition performing instruction can operate only to data where the condition is formed based on the verifying result held by the state holding means and can operate fast.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus having a flag register and having a SIMD operation instruction for performing an operation on a plurality of data in accordance with the contents of the flag register reflecting an instruction execution result.

[0002]

2. Description of the Related Art In recent years, the processing capability of information processing apparatuses such as microcomputers has been dramatically improved, and they have been used in various fields.

In particular, in recent information processing apparatuses, a plurality of data are stored in a register, and a SIMD (Single Instruction Multiple Data) instruction for calculating the plurality of data at a time is implemented, thereby increasing the data processing capability. (For example, “Intel Architecture Software
Developer's Manual Volume 1: Basic Architectur
e ", published by Intel Corporation, pp. 6-9 to pp. 6-11).

FIG. 20 shows a conventional information processing apparatus "Pe
ntium (R) II "processor SIMD
FIG. 11 is a diagram of a first conventional example showing specifications of some comparison instructions of an instruction (hereinafter, referred to as an MMX instruction).

In FIG. 1, operands "sd", "d"
"d" is a 64-bit length register, and "[]" indicates a range from which bit position to which bit position of the register, for example, "sd [15:
0] "," sd [31:16] "," sd [47: 3
2] ”and“ sd [63:48] ”are“ 16 bits from bit 0 (LSB) to bit 15 of register sd ”,“ 16 bits from bit 16 to bit 31 of register sd ”, and“ register sd 16 bits from bit 32 to bit 47 of the register sd ”and“ 16 bits from bit 48 to bit 63 (MSB) of the register sd ”. In addition, the numerical value with “0x” represents a hexadecimal number,
“←” indicates that the value on the right side is stored in the left side.

In this information processing apparatus, the register is divided for every 16 bits, and they are compared with each other.
0xffff ”is set to“ 0x0000 ”when the condition is not satisfied.
It is stored in the corresponding 16-bit position of d. "PCMP
The "EQW instruction" determines whether the corresponding 16 bits of the register dd and the register sd are equal, and the "PCMPGTW instruction"
The comparison condition is whether or not the corresponding 16 bits of the register dd and the register sd are larger in the register dd.

In the first conventional example, all the corresponding 16 bits are set to 0 or 1 according to the comparison result for every 16 bits.
However, there are information processing devices that reflect only one bit (for example, "Ultra SPARC-IIi User's Manual",
un Microsystems, Inc., pp. 135-180.

FIG. 21 shows a conventional information processing apparatus "Ultr
a SPARC-IIi ”processor SIMD instruction (hereafter VI
FIG. 11 is a diagram of a second conventional example showing the specifications of some comparison instructions (referred to as an S instruction).

In FIG. 1, operands “rs1”, “
“rs2” and “rd” are 64-bit registers, and the meanings of “[]”, “0x”, and “←” are the same as those in the first conventional example, and the description is omitted. When only one numerical value is described in [] ”, the bit position of the register is indicated. For example,“ rd [0] ”,“ rd [1] ”,“ rd ”
[2] ”and“ rd [3] ”are“ one bit of bit 0 of register rd ”and“ one bit of bit 1 of register rd ”, respectively.
Bit, 1 bit of bit 2 of register rd,
"1 bit of bit 3 of register rd" is shown.

[0010] Also, regarding the bit position, "Ultr
The bit arrangement of the "a SPARC-IIi" processor is in big endian format (MSB is bit 0, LSB is bit 63)
However, for ease of comparison with other conventional examples, the data is represented in the little endian format (MSB is bit 63, LSB is bit 0) in the figure.

In this information processing apparatus, the register is divided every 16 bits, and each is compared.
When "0x1" is not satisfied, "0x0" is stored in the lower 4 bits of the register rd, one bit at a time.

As a result, in the first and second conventional examples, four 16-bit data can be stored in one register and compared at a time, so that a plurality of data can be collectively processed. Processing capacity can be improved. For example, it is possible to store RGB data of one pixel in one register by image processing or the like, and to use it when extracting only specific RGB data.

In the first and second conventional examples, a comparison instruction in which a comparison result is reflected in 16 bits or 1 bit of a register is implemented.
Some implement maximum or minimum instructions that select the larger or smaller of the numbers (e.g.,
"Alpha Architecture Handbook", Digital Equipment
Corporation, p.4-151 to p.4-156).

FIG. 22 shows a conventional information processing apparatus "Alph
FIG. 14 is a diagram of a third conventional example showing the specification of a part of the minimum value instruction of the SIMD instruction (hereinafter referred to as the MVI instruction) of the “a” processor.

In FIG. 1, operands "Ra", "R"
“b” and “Rc” are 64-bit registers.The meanings of “[]” and “←” are the same as those in the first conventional example, and a description thereof is omitted. ”min (A, B) "Selects the smaller value of A and B.
For example, “C ← min (A, B)” indicates “store the smaller value of A and B in C”.

In this information processing apparatus, the register is divided every 16 bits, and each is compared, and the smaller value is stored in the register Rc.

As another instruction specification of the information processing apparatus which implements the maximum value instruction or the minimum value instruction similar to the third conventional example, the SIMD instruction of the "V830R / AV" processor (hereinafter referred to as MIX2 instruction) ) (For example, "NEC technology"
Vol.51 No.3 / 1998 '', NEC Corporation, p.50-p.54
reference).

Thus, in the third conventional example, 1
Four 16-bit data can be stored in one register, and the maximum value or the minimum value can be obtained at a time, so that the processing capability when processing a plurality of data at once can be improved.

In the first and second conventional examples, a comparison instruction is implemented, and in the third embodiment, a maximum value instruction or a minimum value instruction is implemented. (For example, “AltiVec Technology Programming E
nvironments Manual '', published by Motorola Inc., pp. 4-1 to p.
4-41).

FIG. 23 shows a conventional information processing apparatus "Powe
rPC ”processor SIMD instruction (hereinafter referred to as“ AltiVe ”)
FIG. 13 is a diagram of a fourth conventional example showing the specifications of a part of the comparison instruction and the minimum value instruction (hereinafter referred to as c instruction).

In the figure, operands "A", "A"
B ”and“ C ”are 128-bit registers, and“ C ”
R6 "is a 4-bit condition register." [] "," 0x "," ← "," min (A,
B) "is the same as in the first and third conventional examples, and a description thereof will be omitted.

In this information processing apparatus, the register is divided for every 32 bits, and they are compared with each other.
When “0xffffffff” is not satisfied, “0x00000000” is stored in the corresponding 32-bit position of the register D.
Further, the register is divided for every 32 bits, and each is compared, and the smaller value is stored in the register D.

As a result, in the fourth conventional example, four 32-bit data can be stored in one register and compared at a time, or a maximum value or a minimum value can be obtained. It is possible to improve the processing capacity when processing all at once.

[0024]

However, according to the above prior art, "operation is performed based on the comparison result".
If you want to execute such processing, many instructions are required.

For example, a1 and a2 are stored in two registers A and B, respectively.
2, 4 each of a3, a4 and b1, b2, b3, b4
Data are stored, and the magnitude relation of each data is a1 <b1, a2> b2, a3> b3, a4 <b
4 is assumed. At this time, the data of A and B are compared, and if the data of register A is smaller, the data of register B is added, and finally a1 + b1, a2, a
3. Consider a process often used in image processing such as image synthesis, such as obtaining data of a4 + b4.

In the case of the information processing apparatus that executes the MMX instruction, a bit corresponding to small data is set by comparing the registers A and B, so that “0xffff0000” is set.
0000ffff "is stored. The data is logically ANDed with the register B to generate data b1, 0, 0, and b4, and this is added to the register A, so that a1 + b1, a2, The data a3 and a4 + b4 are obtained, and the same applies to an information processing apparatus that executes the above-mentioned Altivec instruction.

In the case of an information processing apparatus that executes the VIS instruction, when the registers A and B are compared,
The lower 4 bits are “1001”
Is stored. This data is analyzed by a normal comparison instruction, the data of the register B corresponding to the set bit is taken out from the register B, and the data of the register A
SIM to add the program to the corresponding data
By writing with a normal operation instruction other than the D instruction, data a1 + b1, a2, a3, and a4 + b4 to be finally obtained can be obtained.

In the case of an information processing apparatus which executes the MVI instruction and the MIX2 instruction, there is only a maximum value instruction or a minimum value instruction, and the comparison result for obtaining the maximum value or the minimum value is not stored anywhere. The four data stored in the registers A and B are sequentially compared using a comparison instruction. If the data in the register A is smaller, the corresponding data in the register B is extracted and added to the corresponding data in the register A. A1 + b which is finally obtained by writing with a normal operation instruction other than the SIMD instruction
Data of 1, a2, a3, and a4 + b4 are obtained.

As described above, when an operation is performed based on a comparison result often used in image processing, there is a problem that the processing speed becomes extremely slow.

In view of the foregoing, the present invention provides an information processing apparatus that stores a plurality of data in a register and performs an arithmetic operation based on a result of high-speed comparison in a SIMD instruction for operating the plurality of data collectively. The purpose is to do.

[0031]

In order to solve this problem, a processor according to the present invention uses a data designated by an operand as one data to verify that a condition is satisfied.
And a second instruction for verifying that a condition is satisfied by using the data specified by the operand as a plurality of data, and an operation specifying the data specified by the operand as a plurality of data only when the condition is satisfied Instruction decoding means for decoding a machine language instruction including a condition execution instruction for executing the instruction, instruction execution means for executing an instruction in accordance with the instruction decoding means, and a condition specified as a result of verification by the first instruction is satisfied And a second state holding means for indicating that a specified condition is satisfied as a result of verification by the second instruction. Is decoded, the condition specified by the operand is verified as one data, and if the condition is satisfied, the first state holding means indicates that the condition is satisfied, and the second instruction is When read, the data specified by the operand is divided into a plurality of data for each specific number of bits, the condition of each of the divided data is verified for each data, and if the condition is satisfied, the condition is stored in the second state holding means. Is established for each data, and when the conditional execution instruction is decoded, the data specified by the operand is divided into a plurality of data for each specific number of bits, and the second data corresponding to each of the plurality of divided data is divided. Examining the corresponding verification result of the state holding means, and when the condition is satisfied, the instruction execution means performs the operation specified in the instruction on the corresponding divided data, and the condition is satisfied. If not, the instruction execution means controls the corresponding divided data so that the operation specified in the instruction is not performed.

Thus, for each of the plurality of divided data, the condition execution instruction can perform an operation only on the data for which the condition is satisfied, based on the verification result held in the state holding means. , And can be operated at high speed.

Here, the condition execution instruction in the processor may be an instruction to perform a transfer or an instruction to perform an operation when the second state holding means indicates that the condition is satisfied.

Further, the condition execution instruction is used to execute the first operation when the second state holding means indicates that the condition is satisfied, and to execute the first operation when the second state holding means indicates that the condition is not satisfied. A second operation different from the first operation may be performed.

[0035]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an information processing apparatus (hereinafter referred to as a processor) according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment 1) FIG. 1 is a diagram showing a bit configuration of a SIMD operation flag register SFR provided in a processor according to a first embodiment of the present invention.

As shown in the figure, the SIMD operation flag register SFR stores C0 flag, C1 flag, C2 flag, C3 flag.
It consists of a 4-bit flag. This 4
The bit flag is updated when a comparison instruction is executed in the SIMD instruction. The C0 flag is used for comparing 16-bit data from bit 48 to bit 63 (MSB). In comparison of 16-bit data up to bit 47, C
The 2 flag is used for comparing 16-bit data from bit 16 to bit 31 and the C3 flag is used for comparing bit 0 (L
In the comparison of 16-bit data from SB) to bit 15, each bit is set when a comparison condition is satisfied.

The C0, C1, C2, and C3 flags may be provided in one register as shown in FIG. 1, or may be provided in different registers.

Further, in the first embodiment of the present invention, a flag register for normal operation also exists, but is omitted for the sake of simplicity.

The SIMD operation flag register is
It may be provided separately from the normal operation flag register, or may be provided in the same register.

FIG. 2 is a diagram showing an SI according to the first embodiment of the present invention.
FIG. 4 is a diagram illustrating an instruction specification of a comparison instruction in an MD instruction.
In the figure, “vccmpeh Rm, Rn”, “vc”
mpgh Rm, Rn "," vcmpgeh Rm, R
"n" is a machine language instruction for comparing each of the four data stored in the register, and is expressed in a mnemonic format. The operation is also shown for each instruction.

"Vcmpeh", "vcmpgh", "
“vcmpgeh” is an OP code.
Rn "is an operand and a 32-bit register R
m and a register Rn.

"[]" Indicates a range from which bit position to which bit position of the register. For example, “Rm [15: 0]”, “Rm [31: 1]
6] ”,“ Rm [47:32] ”,“ Rm [63: 4
8] is “bit 0 (LSB) of register Rm
16 bits from bit 16 to bit 31 of register Rm "," 16 bits from bit 32 to bit 47 of register Rm ", and" bit 16 to bit 63 of register Rm (M
16) up to SB). Also, "C
“0”, “C1”, “C2”, and “C3” indicate the C0 flag, C1 flag, C2 flag, and C3 flag of the flag register.

"Vcmpeh Rm, Rn" is a comparison instruction for judging "equal", compares four 16-bit data stored in the registers Rm and Rn, and outputs Rm [15: 0] and Rn [ 15: 0] are equal, the C3 flag is set to Rm [31:16] and Rn [31:
16] are equal, the C2 flag is set to Rm [47:32].
And Rn [47:32] are equal, the C1 flag is set to Rm
If [63:48] and Rn [63:48] are equal, C0
Set a flag.

“Vcmpgeh Rm, Rn” is a comparison instruction for determining “large”, compares four 16-bit data stored in the registers Rm and Rn, and finds that Rm [15: 0] is Rn [ 15: 0], the C3 flag is set, and Rm [31:16] is set to Rn [3
1:16], the C2 flag is set, and Rm [47:
32] is larger than Rn [47:32], the C1 flag is set. If Rm [63:48] is larger than Rn [63:48], the C0 flag is set.

"Vcmpgeh Rm, Rn" is a comparison instruction for judging "equal to or greater than", and the four 16 bits stored in the register Rm and the register Rn.
The bit data is compared, and Rm [15: 0] and Rn [1
5: 0] are equal or Rm [15: 0] is Rn [1
5: 0], the C3 flag is set to Rm [31: 1].
6] and Rn [31:16] are equal or Rm [3
1:16] is larger than Rn [31:16], the C2 flag is set, and Rm [47:32] is equal to Rn [47:32] or Rm [47:32] is Rn [47:32].
If larger, the C1 flag is set to Rm [63:48] and R
n [63:48] is equal or Rm [63:48]
Is larger than Rn [63:48], the C0 flag is set.

FIG. 3 is a block diagram showing the SI according to the first embodiment of the present invention.
FIG. 5 is a diagram illustrating an instruction specification of a conditional instruction in an MD instruction. In the figure, “vmovh Rm, Rn”, “v
swap Rm, Rn "," vaddh Rm, R
"n" is a machine language instruction for calculating each of the four data stored in the register based on the contents of the SIMD operation flag register SFR, and is expressed in a mnemonic format as in FIG. The operation for each instruction is also shown in the same manner as in FIG.

"Vmovh", "vswaph", "v
"addh" is an OP code. "Rm", "R"
n "," [] "," C0 "," C1 "," C2 "," C
3 ″ is the same as FIG. 2 and will not be described.

"Vmovh Rm, Rn" is an instruction to "transfer" the contents of the SIMD operation flag register SFR based on the contents of the register.
The content of n [15: 0] is set to Rm [15: 0], and when the C2 flag is 1, the content of Rn [31:16] is set to Rm [31:
16], the content of Rn [47:32] is set to Rm [47:32] when the C1 flag is 1, and Rn [47:32] is set when the C0 flag is 1.
The contents of n [63:48] are transferred to Rm [63:48]. When the flag is 0, the corresponding 16-bit data is not transferred.

"Vswap Rm, Rn" is SIMD
This is an instruction to “swap” the register contents based on the contents of the operation flag register SFR. When the C3 flag is 1, the contents of Rn [15: 0] and Rm [15: 0] are set, and the C2 flag is set to 1 When the C1 flag is 1, the contents of Rn [31:16] and the contents of Rm [31:16] are stored.
The contents of n [47:32] and Rm [47:32] are exchanged. When the C0 flag is 1, the contents of Rn [63:48] and Rm [63:48] are exchanged. If the flag is 0, the corresponding 16-bit data is not replaced.

"Vaddh Rm, Rn" is an instruction for "adding" the contents of the SIMD operation flag register SFR based on the contents of the SIMD operation flag register SFR.
The contents of n [15: 0] and the contents of Rm [15: 0] are added and stored in Rn [15: 0]. When the C2 flag is 1, the contents of Rn [31:16] and the contents of Rm [31:16] are added and stored in Rn [31:16]. When the C1 flag is 1, the contents of Rn [47:32] and Rm [47: 3]
2] is added and stored in Rn [47:32]. C
When the 0 flag is 1, the contents of Rn [63:48] and Rm
The contents of [63:48] are added and stored in Rn [63:48]. If the flag is 0, the corresponding 16-bit data is not added.

FIG. 4 is a block diagram showing a configuration of a main part of the processor according to the first embodiment of the present invention.

The present processor comprises an instruction register 101, an instruction decoder 102, a register file 103, a 64-bit operation unit 104, 16-bit operation units 105 to 108, an SI
MD operation control unit 109, register write control unit 110, S
IMD operation flag storage unit 111, latches 112 to 12
1. It is composed of buses 122 to 125.

The instruction register 101 sequentially holds instructions fetched from the memory.

The instruction decoder 102 includes an instruction register 101
And outputs various control signals for controlling the execution of the instruction. In particular, the command decoder 102
Is SIMD if the vcmpeg instruction, vcmpgh instruction, and vcmpgeh instruction shown in FIG.
In order to request that the operation flag register SFR be updated, the flag update request signal 620 output to the SIMD operation flag storage unit 111 is made valid.

The register file 103 is composed of a plurality of general-purpose registers having a length of 64 bits.
Write request signals 606 and 607 output from
And S output from the SIMD operation flag storage unit 111.
Based on the IMD operation flag information 608 to 611, register data is output to the buses 122 and 123 according to the register write control signal generated by the register write control unit 110, and the data on the buses 124 and 125 is taken into the register.

The 64-bit arithmetic unit 104 is a scalar arithmetic unit that performs scalar data operation that treats 64-bit data as one data.
Data on buses 122 and 123 are latched 112 and 113
And performs the operation specified by the OP code of the instruction.

The 16-bit arithmetic units 105 to 108 have 64
An arithmetic unit (hereinafter, referred to as four 16 bits) that performs an operation on SIMD data that handles bit data divided into four 16 bit data
The bit arithmetic units 105 to 108 are collectively expressed as a SIMD arithmetic unit.) Based on the SIMD operation request signal 601 output from the instruction decoder 102 and the SIMD operation flag information 608 to 611 output from the SIMD operation flag storage unit 111, the SIMD operation control unit 1
In accordance with the SIMD operation control signals 602 to 605 generated in step 09, the data on the buses 122 and 123 are latched 114
To 121, perform the operation specified by the OP code of the instruction, and execute SIMD based on the operation result.
It outputs SIMD flag generation information 621 to 628 necessary for generating the operation flag.

The SIMD operation control unit 109 includes: a SIMD operation request signal 601 output from the instruction decoder 102;
SIM output from SIMD operation flag storage unit 111
It outputs SIMD operation control signals 602 to 605 for controlling the 16-bit operation units 105 to 108 based on the D operation flag information 608 to 611.

Register write control section 110 outputs register write request signals 606 and 6 output from instruction decoder 102.
07 and the SIMD operation flag information 608 to 611 output from the SIMD operation flag storage unit 111, the data on the buses 124 and 125 are stored in the register file 103.
, And outputs register write control signals 612 to 619 for controlling writing to the register.

The SIMD operation flag storage unit 111 stores a flag update request signal 620 output from the instruction decoder 102.
And updates the SIMD operation flag register SFR based on the SIMD flag generation information 621 to 628 output from the SIMD operation unit.

FIG. 5 shows the instruction decoder 102 of FIG.
FIG. 4 is an explanatory diagram (truth value table) showing input / output logic when the SIMD instruction shown in FIG. 3 is input.

In the figure, both input and output are represented by binary numbers, and “vcmpeh”, “vcmpgh”, “vc”
mpgeh "," vmovh "," vswaph ","
SIMD when the machine language command “vaddh” is input
Operation request signal 601, register write request signals 606 and 6
07 and the flag update request signal 620 are shown. “000” of the SIMD operation request signal 601
0 "," 0001 "," 0010 "," 0100 ","
1000 ”are“ nop ”,“ mov ”, and“ sw ”, respectively.
“ap”, “add”, and “cmp”, and requests the SIMD arithmetic unit to execute “do nothing”, “transfer”, “swap”, and “add” in order. However, “0011”, “0101” to “0111”, “1”
001 ”to“ 1111 ”are“ reserved ”and are not output.
Reference numerals 607 each correspond to writing to one register, and indicate requests for writing to a total of two registers. The case of "1" requests writing to the register. However, in the case other than the SIMD instruction, the register write request signals 606 and 60 depend on each instruction.
7 is output, and is described as "depending on the instruction" in the figure. For example, in the case of a normal addition instruction, since the operation result is written into only one register, the register write request signal 606 becomes “1” and the register write request signal 607 becomes “0”. “00”, “01”, “1” of the flag update request signal 620
0 ”and“ 11 ”are“ nop ”,“ eq ”, and“ g ”, respectively.
t "," ge ", and" do not update ",
This indicates that the user requests "determine and update equality", "determine and update largeness", and "determine and update equality or greater".

FIG. 6 shows the SIMD operation control unit 109 of FIG.
FIG. 2 is a block diagram showing an internal configuration of the device.

The SIMD operation control unit 109 includes flip-flops 201 to 204 and logic gates 205 to 20
7 is comprised. The portions enclosed by the dotted line are all the same circuit, and are omitted in the figure.

The flip-flops 201 to 204 are for adjusting timing, and the instruction decoder 102
Latches the SIMD operation request signal 601 output from. Logic gates 205 to 207 are connected to flip-flop 2
SIMD operation control signals 602 to 605 are output based on the contents latched in 01 to 204 and the contents of SIMD operation flag information 608 to 611 output from the SIMD operation flag storage unit 111. SIMD operation control signal 60
2 is an operation for bits 63 to 48, and a SIMD operation control signal 603 is an operation for bits 47 to 32.
The MD operation control signal 604 is a control signal for operations on bits 31 to 16, and the SIMD operation control signal 605 is a control signal for operations on bits 15 to 0.

FIG. 7 is an explanatory diagram (truth value table) showing the input / output logic of the logic gates 205 to 207. In the figure, both input and output are represented by binary numbers.

In the figure, SIMD operation request signal 60
1 and the meaning of the SIMD operation control signal 602 are shown in FIG.
Therefore, the description is omitted. However, SIMD
In the operation control signal 602, “0000”, “000”
Values other than “1”, “0010”, “0100”, and “1000” are “reserved” and are not output.
The IMD operation flag information 608 is an output of the SIMD operation flag storage unit 111 and is the content of the C0 flag of the SIMD operation flag register SFR. Here, since the SIMD operation control signals 603 to 605 have the same logic as the SIMD operation control signal 602, the truth table is omitted.

When the SIMD operation flag information 608 to 611 is “1”, the SIMD operation control
The D operation request signal 601 is output as it is to the SIMD operation control signals 602 to 605. If the signal is "0", the lower 3 bits are set to "0" and SIMD other than "1000 (cmp)".
Set the operation request signal 601 to “0000 (nop)” and set S
The IMD operation control signals 602 to 605 are output.

FIG. 8 shows the register write control unit 110 of FIG.
FIG. 2 is a block diagram showing an internal configuration of the device.

The register write control unit 110 includes flip-flops 202 to 204 and 301 to 306, and logic gates 307 to 310. The portions enclosed by the dotted line are all the same circuit, and are omitted in the figure.

The flip-flops 202 to 204 are shown in FIG.
And latches the lower 3 bits of the SIMD operation request signal 601 output from the instruction decoder 102. The flip-flops 301 to 306 are for adjusting timing, and latch register write request signals 606 and 607 output from the instruction decoder 102. The flip-flops 301 to 304 latch at the rising edge of the clock, and
6 latches at the falling edge of the clock. In this embodiment, since writing to the register is performed at the rising edge of the clock, the signal is latched by the flip-flops 305 to 306 at the falling edge of the clock so that the signal is stable at that time. I have to. The ethics gates 307 to 310 determine the contents latched by the flip-flops 301 and 302 and the SIMD
The operation request signal 601 is supplied to the flip-flops 202 to 204.
And the SIMD operation flag storage unit 11
SIMD operation flag information 608 to 61 output from 1
1 to output register write control signals 612 to 619. Register write control signals 612 and 613 are register write control signals 61 for writing to bits 63 to 48.
4 and 615 are control signals for writing to bits 47 to 32, register write control signals 616 and 617 are control signals for writing to bits 31 to 16, and register write control signals 618 and 619 are control signals for writing to bits 15 to 0. It is. Also, register write control signals 612, 614, 616, 618
, Writing to the same register is controlled, and writing to another register is controlled by register write control signals 613, 615, 617, and 619.

FIG. 9 is an explanatory diagram (truth table) showing the input / output logic of the logic gates 307 to 310. In the figure, both input and output are represented by binary numbers.

In the figure, SIMD operation request signal 60
1, register write request signals 606 and 607, and SI
The meaning of the MD operation flag information 608 is described in FIGS.
Therefore, the description is omitted. Here, since the register write control signals 614 to 619 have the same logic as the register write control signals 612 and 613, the truth table is omitted.

When the SIMD operation flag information 608 to 611 is “1”, the register write control unit 110 outputs the register write request signals 606 and 607 as they are, and outputs “0”. In the case of “”, the register write control signals 612 and 619 indicate that the SIMD operation request signal 601 is “0000 (nop)” and “1000”.
(Cmp) ", the register request signals 606 and 607 are left as they are, and" 0001 (mov) "and" 0010 (sw
ap) ”and“ 0100 (add) ”, the register write request signals 606 and 607 are output as“ 0 ”.

FIG. 10 is a block diagram showing the internal configuration of the SIMD operation flag storage unit 111 of FIG.

The SIMD operation flag storage unit 111 stores
Flip-flops 401 to 407 and a logic gate 408
To 413. The portions enclosed by the dotted line are all the same circuit, and are omitted in the figure.

The flip-flops 401 to 404 are connected to the SI
The flag generated by the MD operation is latched. The SIMD operation flag register SFR in FIG.
Correspond to the C0, C1, C2, and C3 flags. The flip-flops 405 to 407 are for adjusting timing, and the flip-flop 4
05 and 406 latch the flag update request signal 620 output from the instruction decoder 102, and
7 latches the signal generated by the logic gate 408 and outputs a flag update control signal 629. Flip-flop 40
5, 406 latch at the rising edge of the clock, and the flip-flop 407 latches at the falling edge of the clock. In this embodiment, since the update of the SIMD operation flag register is performed at the rising edge of the clock, the signal is latched at the falling edge of the clock by the flip-flop 407 so that the signal is stable at that time. I have to. Logic gate 408
Generates a flag update control signal 629 that becomes "1" when updating the flag, based on the content latched by the flip-flops 405 and 406. Specifically, the logic gate 408 outputs “1” when either bit of the flag update request signal 620 is “1”. This allows
The flag request signal 620 is "determined equality and updated" 01 (eq) "", "determined large and updated" 10 (gt) "", "determined equality or greater and updated" 11 (Ge) At the time of "", the flag is latched in the flip-flops 401 to 404.
The logic gates 409 to 413 are connected to the flip-flop 40
5, the contents latched in 406 and the 16-bit arithmetic unit 1
SIMD flag generation information 621 output from 05 to 108
628 based on SIMD operation flag register SFR
The flag to be stored in the C0, C1, C2, and C3 flags is generated. SIMD flag generation information 6
21 and 622 are in bits 63 to 48, and the SIMD flag generation information 623 and 624 are in bits 47 to 32.
The flag generation information 625 and 626 are bits 31 to 16,
The SIMD flag generation information 627 to 628 includes bits 15 to
This is flag generation information corresponding to 0. The SIMD flag generation information 621, 623, 625, and 627 indicate that the comparison result is “equal” for each 16-bit data.
In this case, it becomes “1” and SIMD flag generation information 622,
624, 626, and 628 become "1" when the comparison result is "large" in the respective 16-bit data.
The logic of the logic gates 409 to 413 is
Serves as a selector, so that the flag update request signal 62
When 0 is "00 (nop)", logic gates 409-41
Since 1 outputs “0”, the logic gate 412
Neither the D flag generation information 621 or 622 nor the output of the logic gate 413 is selected. Flag update request signal 620
Is "01 (eq)", the logic gate 409 outputs "1", and the logic gate 412 selects the SIMD flag generation information 621. When the flag update request signal 620 is "1"
When "0 (gt)", the logic gate 410 outputs "1", so that the logic gate 412 outputs the SIMD flag generation information 62.
Select 2. When the flag update request signal 620 is "11 (g
In the case of “e)”, the logic gate 411 outputs “1”, so that the logic gate 412 selects the output of the logic gate 413 (the logical sum of the SIMD flag generation information 621 and 622), whereby the flag request signal 620 becomes “1”. SIMD flag generation information 621, 62 that becomes “1” when “equal” when “01 (eq)” is determined and updated to determine that they are equal
3, 625, and 627 are "1" when "large" when "judgment and update is large" (10 (gt) "")
SIMD flag generation information 622, 624, 62
When the values of 6 and 628 are "11 (ge) to judge that they are equal or greater and updated", the contents obtained by logically ORing the SIMD flag generation information 621 to 628 corresponding to the same 16-bit data are flip-flopped. Step 40
1 to 404.

FIG. 11 shows the register file 103 of FIG.
FIG. 3 is a block diagram showing a configuration of one register in FIG.

This register has a flip-flop 501
To 508 and logic gates 509 to 540. In the figure, since the circuits of the bits 63 to 48 are the same, the bits 62 to 49 are omitted and only the bits 63 and 48 are shown. Similarly, bits 47 to 32, bits 31 to 16, bit 15
Since the circuit of each bit is the same for .about.0, the bits of bits 46 to 33, bits 30 to 17, and bits 14 to 1 are omitted.

The flip-flops 501 to 508 correspond to each bit of one register and transfer any data on the bus 124 or the bus 125 to the logic gates 517 to 52.
Latch via 4. The logic gates 509 to 516
Based on register write control signals 612 to 619 and a write target register selection signal which becomes "1" when this register is a write target, a signal (enable signal) for permitting latching to flip-flops 501 to 508 is provided. Generate. Specifically, when either of the register write control signals 612 and 613 is “1” and the write target register selection signal is “1”, the flip-flops 503 and 504 output the register write data. Control signal 61
4 or 615 is “1” and the write target register selection signal is “1”, the flip-flop 505,
Reference numeral 506 denotes a case where one of the register write control signals 616 and 617 is “1” and the register selection signal to be written is “1”, and the flip-flops 507 and 508 output one of the register write control signals 618 and 619. Is "1" and the write target register selection signal is "1".
The logic gates 517 to 524 generate data to be written to the flip-flops 501 to 508 (register) based on the data on the buses 124 and 125 and the register write control signals 612 to 619. Since each of the logic gates 517 to 524 functions as a selector, the logic gate 51
7, 518, the register write control signal 612
Is "1", the bus 124 is selected, and when the register write control signal 613 is "1", the bus 125 is selected. The logic gates 519 and 520 select the bus 124 when the register write control signal 614 is “1”, and select the bus 125 when the register write control signal 615 is “1”.
The logic gates 521 and 522 select the bus 124 when the register write control signal 616 is “1”, and select the bus 125 when the register write control signal 617 is “1”. In the logic gates 523 to 524, the bus 124 is used when the register write control signal 618 is "1", and the bus 125 is used when the register write control signal 619 is "1".
Select Thereby, the flip-flops 501 to 5
08 (register) is a register write control signal 612,6
When the bits 14, 616 and 618 are "1", the data on the bus 124 is transferred to the register write control signals 613, 615 and 6
When 17 and 619 are "1", the data on the bus 125 is fetched and latched. Logic gate 525
Reference numeral 540 denotes a tri-state buffer which outputs data stored in the flip-flops 501 to 508 (register) to the bus 122 or the bus 123.

The operation of the processor configured as described above will be described.

FIG. 12 is a block diagram of the present processor.
4 shows a time chart when the instruction shown in FIG. 3 is executed.

FIG. 14 shows the operation when the following instruction is executed.

Vcmpeh Rm, Rn vmovh Rm, Rn ... vcmpgh Rm, Rn vsswap Rm, Rn ... vcmpgeh Rm, Rn vaddh Rm, Rn T1 to T10 in FIG. T2, T3, T in order from T1
4, T5, T6, T7, T8, T9, and T10.

First, the operation when the vcmpeh instruction is executed will be described.

In the machine cycle T 1, the vcmpeh instruction latched in the instruction register 101 is decoded by the instruction decoder 102. The OP code of the instruction is "vcmpe
h ”, the instruction decoder 102 sets the SIMD operation control unit 109 to“ 1 ”as the SIMD operation request signal 601 so as to“ perform comparison every 16 bits at T2 ”.
000 (cmp) ”as“ 0 ”and“ 0 ”, respectively, as register write request signals 606 and 607 so that the register write control unit 110“ does not write to the register ”.
Is output to the SIMD operation flag storage unit 111 as “01 (eq)” so as to “determine that they are equal and update them”. Since the operands of the instruction are “Rm” and “Rn”, the instruction decoder 102
3, "Read out the register Rm and the register Rn, and transfer the respective data via the buses 122 and 123.
At T2, the latches are latched by the latches 114 to 121 and input to the 16-bit arithmetic units 105 to 108, and the arithmetic unit control signal is output.

In machine cycle T 2, SIMD operation control section 109 transmits SIMD operation request signal 601 to SIMD operation request signal 601.
MD operation flag information 608 to 611 is input, and SIMD operation control signals 602 to 605 for controlling the 16-bit operation units 105 to 108 are output. Since the SIMD operation request signal is “1000”, the SIMD operation flag information 6
No matter what value 02-605 is, the logic gate 205
To 207 are "0", and the SIMD operation control signals 602 to 605 are "1000". As a result, the 16-bit operation units 105 to 108 cause the latches 114 to 12 to operate according to the SIMD operation control signals 602 to 605.
The data latched at 1 is compared, and SIMD flag generation information 621 to 628 is output. Here, if it is determined that the 16-bit arithmetic units 105 and 107 are equal, the SIMD flag generation information 621 to 628 are “1”, “0”, “0”, “0”, “1”, “1”.
0 ”,“ 0 ”,“ 0. ”Also, since the flag update request signal 620 was“ 10 ”in the machine cycle T1, the SIMD operation flag storage unit 111 sets the flag to“ update the flag ”. As the update control signal 629,
1 ”. The register write control unit 110 outputs
Since the register write request signals 606 and 607 were “0” and “0” in the machine cycle T1, the register write control signals 612 to 612 are set so as not to write the register.
As "619", all "0" are output.

In machine cycle T 3, SIMD operation flag storage section 111 stores flag update control signal 629
Is “1”, the SIMD flag generation information 621 to
628 to the SIMD operation flag register SFR
Are updated. In the machine cycle T2, if the flag update request signal 620 is "01" and the SI
MD flag generation information 621 to 628 is "1", "
0 "," 0 "," 0 "," 1 "," 0 "," 0 ","
0 ”, the C0 to C3 flags are respectively“
1 "," 0 "," 1 ", and" 0 ", and the register file 103 stores the register write control signal 612.
Since 619 are all “0”, writing to the register is not performed.

Next, the operation when the vmovh instruction is executed will be described.

In the machine cycle T2, the vmovh instruction latched in the instruction register 101 is
02 is decrypted. The OP code of the instruction is "vmovh"
Therefore, the instruction decoder 102 instructs the SIMD operation control unit 109 to “16 when the C0 to C3 flags of the SIMD operation flag register SFR are“ 1 ”at T3.
SIMD operation request signal 6
"0001 (mov)" as 01, "1" and "0" as register write request signals 606 and 607, respectively, so that the register write control unit 110 "writes to one register". Storage unit 111
To “00 (no)
p) ”, and the operand of the instruction is“ Rm ”.
Therefore, the instruction decoder 102 reads the register file 1
03, the register Rm is read, and the respective data is latched at T3 via the bus 122 at T3.
4 to 117, 16-bit arithmetic units 105 to 10
8 to output an arithmetic unit control signal.

In the machine cycle T3, the SIMD operation control unit 109 sends the SIMD operation request signal
MD operation flag information 608 to 611 is input, and SIMD operation control signals 602 to 605 for controlling the 16-bit operation units 105 to 108 are output. Since the SIMD operation flag information 608 and 610 are “1”, the logic gate 205
207 output the input data as they are,
The MD operation control signals 602 and 604 become "0001". Since the SIMD operation flag information 609 to 611 is “0”, the outputs of the logic gates 205 to 207 are “0”, and the SIMD operation control signals 603 and 605 are “000”.
0 (nop) ". The 16-bit operation units 105 to 108 output the SIMD operation control signal 602.
The data latched by the latches 114 and 116 is output to the bus 124 as it is according to. Also,
Since the flag update request signal 620 was “00” in the machine cycle T2, the SIMD operation flag storage unit 111 outputs “0” as the flag update control signal 629 so as to “do not update the flag”. Further, register write control section 110 outputs register write request signals 606, 60
7 are “1” and “0” in the machine cycle T2, so that “1” and “1” are respectively set as the register write control signals 612 to 619 so as to “write to one register”.
0 "," 1 "," 0 "," 0 "," 0 "," 0 ","
0 "is output.

In machine cycle T4, SIMD operation flag storage section 111 stores flag update control signal 629
Is “0”, the SIMD operation flag register SF
The C0 to C3 flags of R are not updated. The register file 103 stores the register write control signals 612 and 616
Is "1", the logic gates 509 and 511 corresponding to the register to be written become "1", and the data on the bus 124 is flip-flops 501, 502 and 50.
5, 506, and writing to the register is performed.

Thereafter, the vcmpgh instruction, vswaph instruction, vcmpgeh instruction, and vaddh instruction are executed. However, since the operation is basically the same as the above-mentioned vcmpeh instruction and vmovh instruction, the description is omitted here.

(Embodiment 2) In the above embodiment, S
When the C0 to C3 flags of the IMD operation flag register SFR are “0”, no operation is performed (nop), but another operation may be performed instead.

FIG. 13 is a diagram showing an instruction specification of an instruction added to the instruction specification of the first embodiment as a second embodiment of the present invention. In the figure, “vswmvh
Rm, Rn "," vmvadh Rm, Rn "," vs
wad Rm, Rn ”indicates that the C0 to C3 flags are“ 0 ”.
Is a machine language instruction of an instruction for performing an operation different from that of "1", and is expressed in a mnemonic format. Also,
The operation for each instruction is also shown.

FIG. 14, FIG. 15, FIG. 16, FIG. 17, FIG.
Is a part different from the first embodiment of the present invention in order to realize this instruction specification. FIG. 14 is an explanatory diagram (truth table) showing input / output logic when the SIMD instruction shown in FIGS. 2, 3, and 13 is input to the instruction decoder 102 of FIG. 4, and FIG. FIG. 16 is a block diagram showing the internal configuration of the SIMD operation control unit 109. FIG.
FIG. 17 is a block diagram showing the internal configuration of the register write control unit 110 in FIG. 4, and FIG. 18 is a logic gate 807 to 813.
FIG. 2 is an explanatory diagram (truth value table) showing the input / output logic of FIG.

FIG. 19 is a block diagram of the processor shown in FIG.
FIG. 14 shows a time chart when the instructions shown in FIGS. 3 and 13 are executed.

FIG. 14 shows the operation when the following instruction is executed.

Vcmpeh Rm, Rn vswmvh Rm, Rn... Vcmpgh Rm, Rn vmvadh Rm, Rn. Yes, C in SIMD operation flag register SRF
When the 0 to C3 flags are "0", only operations different from those in the case of "1" are performed, and the description is omitted here.

[0101]

As is apparent from the above description, the processor of the present invention uses the data specified by the operand as one data, the first instruction for verifying that the condition is satisfied, and the data specified by the operand. A machine including a second instruction for verifying that a condition is satisfied as a plurality of data, and a condition execution instruction for executing an operation specified by the data specified by the operand as the plurality of data only when the condition is satisfied; Instruction decoding means for decoding a word instruction; instruction execution means for executing an instruction in accordance with the instruction decoding means; first state holding means for indicating that a condition specified as a result of verification by the first instruction is satisfied; And a second state holding means indicating that a condition specified as a result of verification by the second instruction is satisfied, wherein the instruction decoding means decodes the first instruction, The specified data to verify the condition as one data operand, the satisfies the condition first
When the second instruction is decoded, the data specified by the operand is divided into a plurality of data for each specific number of bits, and the divided plurality of data is For each condition, the condition is verified, and if the condition is satisfied, the second state holding means is made to indicate for each data that the condition is satisfied. When the condition execution instruction is decoded, the data specified by the operand is changed to a specific number of bits. Each of the data is divided into a plurality of data, and the verification result of the second state holding means corresponding to each of the plurality of divided data is examined. When the condition is satisfied, the corresponding divided data is Performing the operation specified in the instruction by the instruction execution means,
When the condition is not satisfied, the instruction execution means controls the corresponding divided data so that the operation specified in the instruction is not performed.

Thus, for each of the plurality of divided data, the condition execution instruction performs an operation only on the data for which the condition is satisfied, based on the verification result held in the second state holding means. And high-speed operation can be performed.

Also, apart from the first state holding means for holding the result of verifying the condition (normal comparison operation) with the data specified by the operand as one data, the data specified by the operand is defined as a plurality of data. Verification (SI
MD data comparison operation) by having the second state holding means for holding the result of the
Since the data comparison operation can be performed independently, there is an effect that the flexibility of the program is increased.

As described above, the practical value of the technology of the present invention is great.

[Brief description of the drawings]

FIG. 1 is a diagram showing a bit configuration of a SIMD operation flag register SFR provided in a processor according to a first embodiment of the present invention.

FIG. 2 is a view showing an instruction specification of a comparison instruction in the SIMD instruction of the embodiment.

FIG. 3 is a view showing an instruction specification of a conditional instruction in the SIMD instruction of the embodiment.

FIG. 4 is a block diagram showing a configuration of a main part of a processor according to the embodiment of the present invention.

FIG. 5 is an explanatory diagram (truth value table) showing input / output logic when a SIMD instruction is input to the instruction decoder 102 of the embodiment.

FIG. 6 is a block diagram showing an internal configuration of a SIMD operation control unit 109 according to the embodiment;

FIG. 7 is an explanatory diagram (truth value table) showing input / output logic of logic gates 205 to 207 of the SIMD operation control unit 109 according to the embodiment.

FIG. 8 is a block diagram showing an internal configuration of a register write control unit 110 according to the embodiment;

FIG. 9 is an explanatory diagram (truth value table) showing input / output logic of logic gates 307 to 310 of register write control unit 110 of the embodiment.

FIG. 10 is a SIMD operation flag storage unit 1 according to the embodiment.
11 is a block diagram showing the internal configuration of the eleventh embodiment.

FIG. 11 is a block diagram showing the configuration of one register in a register file 103 according to the embodiment;

FIG. 12 is a time chart when the SIMD instruction is executed in the embodiment.

FIG. 13 is a diagram showing an instruction specification of an instruction added to the instruction specification of the first embodiment as a second embodiment of the present invention;

FIG. 14 is an explanatory diagram (truth value table) showing input / output logic when a SIMD instruction is input to the instruction decoder 102 in the embodiment.

FIG. 15 is a block diagram showing an internal configuration of a SIMD operation control unit 109 according to the embodiment;

FIG. 16 is an explanatory diagram (truth table) showing input / output logic of logic gates 707 to 714 of the SIMD operation control unit 109 according to the embodiment.

FIG. 17 is a block diagram showing an internal configuration of a register write control unit 110 according to the embodiment;

FIG. 18 is an explanatory diagram (truth value table) showing input / output logic of logic gates 807 to 813 of register write control unit 110 according to the embodiment;

FIG. 19 is a time chart when an SIMD instruction is executed in the embodiment.

FIG. 20 is a diagram showing the specifications of some comparison instructions of SIMD instructions of a “Pentium II” processor, which is a conventional information processing apparatus.

FIG. 21 shows a conventional information processing apparatus “Ultra SPARC-II”.
Diagram showing specifications of some comparison instructions of SIMD instruction of "i" processor

FIG. 22 is a diagram showing the specification of a part of a minimum value instruction of a SIMD instruction of an “Alpha” processor which is a conventional information processing apparatus.

FIG. 23 is a diagram showing specifications of a part of a comparison instruction and a minimum value instruction of a SIMD instruction of a “PowerPC” processor which is a conventional information processing apparatus.

[Explanation of symbols]

 101 Instruction register 102 Instruction decoder 103 Register file 104 64-bit operation unit 105-108 16-bit operation unit 109 SIMD operation control unit 110 Register writing control unit 111 SIMD operation flag storage unit 112-121 Latch 122-125 Bus 201-204 Flip-flops 205 to 207 Logic gates 301 to 306 Flip-flops 307 to 310 Logic gates 401 to 407 Flip-flops 408 to 413 Logic gates 501 to 508 Flip-flops 509 to 540 Logic gate 601 SIMD operation request signal 602 to 605 SIMD operation control signal 606 , 607 register write request signal 608 to 611 SIMD operation flag information 612 to 619 register write control signal 620 flag update request signal 621 628 SIMD flag generation information 701 to 706 flip-flops 707 to 714 logic gates 801 to 806 flip-flops 807 to 813 logic gates

Claims (8)

[Claims] 1. A first instruction for verifying that a condition is satisfied by using data specified by an operand as one data, and a second instruction for verifying that the condition is satisfied by using data specified by an operand as a plurality of data. Instruction decoding means for decoding a machine language instruction including an instruction, instruction execution means for executing an instruction in accordance with the instruction decoding means, and a first indicating that a specified condition is satisfied as a result of verification by the first instruction State holding means, and second state holding means indicating that a specified condition is satisfied as a result of verification by the second instruction, wherein the instruction decoding means decodes the first instruction, The condition specified is verified as one data, and the condition is verified. If the condition is satisfied, the first state holding means is made to show that the condition is satisfied. When the second instruction is decoded, the operation is performed. The data specified by the land is divided into a plurality of data for each specific number of bits, and a condition is verified for each of the plurality of divided data. If the condition is satisfied, the condition is satisfied in the second state holding means. Characterized in that the control is performed so as to indicate this for each data. 2. The processor according to claim 1, wherein said plurality of divided data all have the same number of bits. 3. A first instruction for verifying that a condition is satisfied by using data specified by an operand as one data, and a second instruction for verifying that the condition is satisfied by using data specified by an operand as a plurality of data. Instruction decoding means for decoding a machine language instruction including an instruction, instruction execution means for executing an instruction in accordance with the instruction decoding means, and state holding means for indicating that a specified condition is satisfied as a result of the verification. When the instruction decoding means decodes the first instruction, it verifies the condition using the data specified by the operand as one data, and if the condition is satisfied, causes the state holding means to indicate that the condition has been satisfied; When the instruction is decoded, the data specified by the operand is divided into a plurality of data for each specific number of bits, and the conditions for each of the divided data are verified for each data. Processor, characterized in that said conditions are controlled so as to indicate that established for each of the data to the state holding means satisfies a. 4. The processor according to claim 3, wherein said plurality of divided data all have the same number of bits. 5. A first instruction for verifying that a condition is satisfied by using data specified by an operand as one data, and a second instruction for verifying that the condition is satisfied by using data specified by an operand as a plurality of data. An instruction decoding unit that decodes a machine language instruction including an instruction and a condition execution instruction that executes an operation specified as a plurality of pieces of data specified by the operand only when a condition is satisfied; and Instruction execution means for executing an instruction; first state holding means indicating that a condition specified as a result of verification by the first instruction is satisfied; and a condition specified as a result of verification by the second instruction. And second state holding means for indicating that the condition has been satisfied. The instruction decoding means, when decoding the first instruction, sets data designated by an operand as one data as a condition. When the condition is satisfied, the first state holding means is made to show that the condition is satisfied. When the second instruction is decoded, the data specified by the operand is converted into a plurality of data for each specific number of bits. Dividing a plurality of divided data, verifying a condition for each data, and, if the condition is satisfied, causing the second state holding unit to indicate that the condition is satisfied for each data; decoding the condition execution instruction Then, the data specified by the operand is divided into a plurality of data for each specific number of bits, and the corresponding verification result of the second state holding means corresponding to each of the plurality of divided data is examined, and the condition is satisfied. When the condition is satisfied, the instruction execution means performs the operation specified in the instruction on the corresponding divided data, and when the condition is not satisfied, the instruction execution means performs the operation on the corresponding divided data. During the order Processor and controlling so as not to perform the specified operation. 6. The processor according to claim 5, wherein the condition execution instruction is an instruction for the second state holding unit to perform a transfer when a condition is satisfied. 7. The processor according to claim 5, wherein the condition execution instruction is an instruction for the second state holding means to perform an operation when a condition is satisfied. 8. A first instruction for verifying that a condition is satisfied by using data specified by an operand as one data, and a second instruction for verifying that the condition is satisfied by using data specified by an operand as a plurality of data. An instruction decoding unit that decodes a machine language instruction including an instruction and a condition execution instruction that executes an operation specified as a plurality of pieces of data specified by the operand only when a condition is satisfied; and Instruction execution means for executing an instruction; first state holding means indicating that a condition specified as a result of verification by the first instruction is satisfied; and a condition specified as a result of verification by the second instruction. And second state holding means for indicating that the condition has been satisfied. The instruction decoding means, when decoding the first instruction, sets data designated by an operand as one data as a condition. When the condition is satisfied, the first state holding means is made to show that the condition is satisfied. When the second instruction is decoded, the data specified by the operand is converted into a plurality of data for each specific number of bits. Dividing a plurality of divided data, verifying a condition for each data, and, if the condition is satisfied, causing the second state holding unit to indicate that the condition is satisfied for each data; decoding the condition execution instruction Then, the data specified by the operand is divided into a plurality of data for each specific number of bits, and the corresponding verification result of the second state holding means corresponding to each of the plurality of divided data is examined, and the condition is satisfied. When the condition is satisfied, the first operation specified in the instruction is performed by the instruction execution means on the corresponding divided data. When the condition is not satisfied, the instruction is executed on the corresponding divided data. Execution means Processor and controlling so as not to perform the second operation specified in the decree.