JP2001257380A - Light-emitting diode array and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an inexpensive light-emitting diode array whose chip size is small, even if a common cathode electrode or a common anode electrode is installed, and to provide its manufacturing method. SOLUTION: A light-emitting diode array is provided wit a plurality of light- emitting diodes, arranged in a column, a cathode bonding pad and an anode- bonding pad, which supplies power to the plurality of light emitting diodes, and a common cathode electrode or a common anode electrode connecting the cathode electrodes or the anode electrodes of the plurality of light-emitting diodes. The cathode-bonding pad or the anode-bonding pad is installed on the common cathode electrode or the common anode electrode via an insulating layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light emitting diode array used as a light source of an electrophotographic printer and a method of manufacturing the same.

[0002]

2. Description of the Related Art As a light source of an electrophotographic printer,
The laser method and the light emitting diode array method are mainly used. Above all, the light emitting diode array system does not require a long optical path length unlike the laser system, and therefore has the feature that the printer can be reduced in size and that large-size printing can be easily performed. The optical path length is, for example, n · l when light travels through a medium having a refractive index of n and a length of l. Particularly in recent years, colorization of printers has been advanced, and a light emitting diode array with higher definition and higher output has been demanded.

FIG. 4 is a plan view showing a first example of a conventional light emitting diode array. FIG. 5 is a cross-sectional view of the light emitting diode array of FIG. FIG. 6 is a cross-sectional view of the light emitting diode array of FIG. 4 taken along line BB. 60 is a light emitting unit,
71 is an n-type GaAs substrate, 72 is an n-type GaAs buffer layer, 73 is an n-type GaAlAs layer, 74 is a p-type GaAlA
s layer, 75 is a p-type GaAs layer, 76 is a cathode electrode, 7
7 is an anode electrode, 78 is an anode wiring, 79 is a wire bonding pad, 80 is a bonding portion, 81 is SiO2
The film 85 is a mesa etching groove.

[0004] A plurality of light emitting units 60 are arranged in a negative line on the chip. The cross-sectional structure is such that n-type GaAs substrate 71 has n
-Type GaAs buffer layer 72, n-type GaAlAs layer 73,
It has a double hetero structure in which a p-type GaAlAs layer 74 and a p-type GaAs layer 75 are sequentially provided.

The separation between the light emitting diodes is made by n-type GaAl.
This is performed by mesa etching up to the As layer 73. The mesa-etched groove 85 between the light emitting diodes has an inverted mesa shape as shown in FIG. 6, so that light separation between the light emitting diodes is clear.

The cathode electrode 76 is an n-type GaAs substrate 71
And the anode electrode 77 is provided on the p-type GaAs layer 75 by depositing a metal and alloying it. The anode electrode 77 and the wire bonding pad 79 are electrically connected by an anode wiring 78 made of Au. This anode wiring 78
Are formed in the forward mesa direction as shown in FIG. 5, so that there is no step disconnection.

[0007] The term “cut” means that when a metal film is applied to a plane composed of two planes forming an angle, the metal film is cut at a place where the two planes intersect at an angle. A state where conduction is lost.

An n-type GaAlAs layer 73 and a p-type GaAlA
Since light generated at the junction 80 of the s layer 74 cannot pass through the p-type GaAs layer 75, the light-emitting section 60 as a light extraction section is provided by removing the p-type GaAs layer 75 by etching.

However, when the density of the light emitting portion is increased by the above structure, the number of the wire bonding pads 79 increases, and there is a problem that the bonding wires are easily brought into contact with each other and the wire bonding becomes difficult.

Therefore, the present applicant has devised a light emitting diode array different from the light emitting diode array shown in FIGS. 4 and 5, and disclosed it in Japanese Patent Application No. 11-221297. Hereinafter, the light emitting diode array will be described in detail.

FIG. 7 is a circuit diagram of the light emitting diode array. A1 to Am are common anode electrodes, and B1 to Am
Bm is a block, C1 to Cn are common cathode electrodes, D
(1,1) to D (m, n) are light emitting diodes.

All the light emitting diodes D (1, 1), D (1, 2),..., D in the light emitting diode array chip
(1, n), D (2,1), D (2,2), ..., D
(2, n),..., D (m, 1), D (m, 2),.
.., D (m, n) are m blocks B1, B2,.
, Bm, and each block B1, B2,.
.., each light emitting diode D (1, 1) to D within Bm
(M, n) anode electrodes are m common anode electrodes A
1, A2,..., Am. , Bm, i-th light emitting diodes D (i, 1), D (i, 2),..., D of all blocks B1, B2,.
The cathode electrode of (i, n) has n common cathode electrodes C
, C2,..., Cn.

A method of driving such a light emitting diode array according to light emission information is as follows. First, the common cathode electrode C1 connected to the first cathode electrode is turned on (0 V: zero volt) and the other common cathode electrodes are turned on. OFF (5V)
And the common electrode A connected to each anode electrode
1 to Am. Turn on the anode electrode corresponding to the dot to emit light as a signal to each anode electrode
(For example, the driving voltage of the light emitting diode is 1.5 V)
The anode electrode corresponding to the dot that you do not want to emit light is OF
F (0 V).

Next, with the common cathode electrode C2 connected to the second cathode electrode turned on (0 V) and the other common cathode electrodes turned off (5 V), the common anode connected to each anode electrode is turned off. A signal is sent to the electrodes A1 to Am. As described above, as a signal to each anode electrode,
The anode electrode corresponding to the dot to emit light is turned ON (the driving voltage of the light emitting diode is, for example, 1.5 V), and the anode electrode corresponding to the dot not to emit light is turned OFF.
(0 V).

By performing the same operation up to the common cathode electrode Cn connected to the n-th cathode, light emission information of all dots can be transmitted.

According to the light emitting diode array of the present invention,
All the light emitting diodes D (1,1) to D (m, n) are divided into blocks B1 to Bm each including a fixed number of light emitting diodes, and each light emitting diode D is provided for each of the blocks B1 to Bm.
The anode electrodes (1, 1) to D (m, n) are connected to the common anode electrodes A1 to Am, and all the blocks B1 to
By connecting the cathode electrodes of the i-th light emitting diode D (m, i) of Bm to other common cathode electrodes C1 to Cn, the light emitting diodes D (1, 1) to D (m,
The matrix of n) is configured.

The common anode electrodes A1 to A1 of this matrix
Am and the number of the common cathode electrodes C1 to Cn are determined by connecting the cathode electrodes of all the light emitting diodes D (1, 1) to D (m, n) in common and setting the respective light emitting diodes D (1, 1) to D (m ,
n) It is possible to reduce the number compared to the first example of the conventional light emitting diode array in which a voltage is individually applied to each anode electrode, and it is possible to reduce the density of wire bonding.
Therefore, the light emitting diode D (1,
1) It is possible to increase the density of the light emitting portions of D (m, n).

Next, a light emitting diode array (second example of a conventional light emitting diode array) for realizing the circuit as described above and a method of manufacturing the same will be described in detail with reference to the drawings.

FIG. 8 is a plan view showing a second example of the conventional light emitting diode array. FIG. 9 is a cross-sectional view of the light emitting diode array of FIG. 8 taken along line EE. FIG. 10 is a sectional view taken along line FF of the light emitting diode array of FIG. 41 is a semi-insulating GaAs substrate, 42 is an undoped GaAs buffer layer, 43 is a p-type GaAs layer, 44 is p-type GaAlAs
Layer, 45 is an n-type GaAlAs layer, 46 is n-type GaAs
Layer, 47 is a first SiO2 film, 48 is a second SiO2 film, 5
0 is a cathode wiring, 51 is a light emitting section, 52 is a cathode electrode, 53 is an anode electrode, 54 is a common cathode electrode, 5
5 is a first mesa etching groove, 56 is a second mesa etching groove, 57 is a cathode through hole, 58 is a cathode bonding pad, and 59 is an anode bonding pad.

(1) (10) of the semi-insulating GaAs substrate 41
0) A high-resistance undoped GaAs buffer layer 42, a p-type GaAs layer 43, and a p-type G
aAlAs layer 44, n-type GaAlAs layer 45 and n-type G
The aAs layer 46 is sequentially grown.

(2) The uppermost n-type GaAs layer 46
Has a property of blocking light, the n-type GaAs layer 46 located in the light emitting section 51 is removed by wet etching.

(3) A first mesa etching groove (separation groove) 55 is formed by wet etching to separate the cathode electrode portion of each light emitting diode. At this time, the first mesa-etched groove 55 between each light emitting diode
Has an inverted mesa shape as shown in FIG. Note that the depth of the first mesa-etched groove 55 is set to such a depth that the p-type GaAs layer 43 is exposed.

(4) Each block B1, B2,..., B
A second mesa-etched groove 56 is formed by wet etching in order to electrically insulate the anode electrode between m. The depth of the second mesa etching groove 56 is p-type Ga
The depth is made deeper than the As layer 43.

(5) At this stage, C is applied so as to cover the entire surface.
The first SiO2 film 47 is grown by VD.

(6) In order to connect the cathode electrodes of the blocks B1 to Bm, the common cathode electrode 54 is formed by pattern etching after depositing gold (Au).

(7) A second SiO 2 film 48 is grown again by CVD so as to cover the entire surface.

(8) Anode electrode 53 and cathode electrode 5
2 is formed on the first SiO2 film 47 and the second Si
The O2 film 48 is removed with hydrofluoric acid. Anode electrode 53
Is formed by evaporating AuZn / Ni / Au on the p-type GaAs layer 43 and alloying it. The cathode electrode 52 is formed on the n-type GaAs layer 46 by AuGe / Ni /
It is formed by evaporating Au and alloying it.

(9) A line connecting the cathode electrode 52 and the bonding pad 58 for the cathode and a through hole 57 for connecting to the common cathode electrode 54 are formed by etching with hydrofluoric acid.

(10) After vapor-depositing Au on the entire surface, pattern etching is performed to form a cathode bonding pad 58, an anode bonding pad 59, and a line (cathode wiring 50) connecting the cathode electrode 52 and the cathode bonding pad 58. ) Is formed.

(11) The semi-insulating GaAs substrate 41 on which these layers 42 to 59 are formed is cut into chips by dicing and separated, and a high-density light emitting diode in which a plurality of light emitting portions 51 are arranged in a line in the longitudinal direction. An array chip is formed.

[0031]

The second example of the conventional light emitting diode array and the manufacturing method thereof have the following problems.

There is a problem that a region for the common cathode electrode is required, and the chip size is correspondingly increased, resulting in a high cost.

Accordingly, an object of the present invention is to solve the above-mentioned drawbacks of the prior art, and to provide an inexpensive light-emitting diode array having a small chip size even if a common cathode electrode or a common anode electrode is provided, and a method of manufacturing the same. It is in.

[0034]

According to the present invention, a plurality of light emitting diodes arranged in a row, a cathode bonding pad and an anode bonding pad for supplying electricity to the plurality of light emitting diodes are provided. In a light-emitting diode array including a common cathode electrode or a common anode electrode interconnecting the cathode electrodes or the anode electrodes of the plurality of light-emitting diodes, the cathode bonding pad or the anode bonding pad may be the common cathode electrode or the common cathode electrode. The structure was formed on the anode electrode via an insulating layer.

According to the present invention, in order to achieve the above object, a plurality of light emitting diodes arranged in a line on a semiconductor substrate are formed, and then a cathode bonding pad and an anode bonding pad for supplying electricity to the plurality of light emitting diodes are formed. Forming a light-emitting diode array by forming a common cathode electrode or a common anode electrode interconnecting the cathode electrodes or anode electrodes of the plurality of light-emitting diodes. A cathode bonding pad or an anode bonding pad is provided on the common cathode electrode or the common anode electrode via an insulating layer.

[0036]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view of a surface including one light emitting portion and an electrode according to an embodiment of the light emitting diode array of the present invention. FIG. 2 is a cross-sectional view of a surface including a plurality of light emitting units, related to the light emitting diode array of FIG. FIG. 3 is a plan view of the light emitting diode array of FIG. FIG.
3 is a sectional view taken along the line CC of FIG. 3, and FIG.
It is sectional drawing. 11 is a semi-insulating GaAs substrate, 12 is an undoped GaAs buffer layer, 13 is a p-type GaAs layer,
14 is a p-type GaAlAs layer, 15 is an n-type GaAlAs
Layer, 16 is an n-type GaAs layer, 17 is a first SiO 2 film, 1
8 is a second SiO2 film, 19 is an insulating layer (third SiO2 film).
, 21 is a light-emitting portion, 22 is a cathode electrode, 23 is an anode electrode, 24 is a common cathode electrode, and 25 is a first mesa electrode.
Etching groove, 26 is the second mesa etching groove, 27 is the first through hole for the cathode, 28 is the bonding pad for the cathode, 30 is the wiring for the cathode, 31 is the wiring for the anode, 32 is the second through hole for the cathode, 33 Is an anode through-hole and 34 is an anode bonding pad.

The circuit diagram of the light emitting diode array shown in FIG. 1 is the same as that of the circuit of FIG. 7 described in the prior art, and the driving method has already been described, so that the description is omitted.

Hereinafter, the manufacturing method will be described.

(1) (10) of the semi-insulating GaAs substrate 11
0) A high resistance undoped GaAs buffer layer 12, a p-type GaAs layer 13, and a p-type G
aAlAs layer 14, n-type GaAlAs layer 15, and n-type G
The aAs layer 16 is sequentially grown.

(2) The uppermost n-type GaAs layer 16
Has a property of blocking light, so that the n-type GaAs layer 16 located in the light emitting section 21 is removed by wet etching.

(3) A first mesa etching groove (separation groove) 25 is formed by wet etching to separate the cathode portion of each light emitting diode. At this time, the first mesa etching groove 25 between the light emitting diodes is
As shown in FIG. Note that the depth of the first mesa-etched groove 25 is set to such a depth that the p-type GaAs layer 13 is exposed.

(4) Each block B1, B2,..., B
A second mesa-etched groove 26 is formed by wet etching in order to electrically insulate the anode electrode between m. The depth of the second mesa etching groove 26 is p-type Ga
The depth is made deeper than the As layer 13.

(5) At this stage, C is applied so as to cover the entire surface.
The first SiO2 film 17 is grown by VD.

(6) In order to connect the cathode electrodes of the blocks B1 to Bm, the common cathode electrode 24 is formed by pattern etching after depositing Au.

(7) The second SiO 2 film 18 is grown again by CVD so as to cover the entire surface.

(8) Anode electrode 23 and cathode electrode 2
2 where the first SiO2 film 17 and the second Si
The O2 film 18 is removed with hydrofluoric acid. Anode electrode 23
Is formed by evaporating AuZn / Ni / Au on the p-type GaAs layer 13 and alloying it. The cathode electrode 22 is formed on the n-type GaAs layer 16 by AuGe / Ni /
It is formed by evaporating Au and alloying it.

(9) The first cathode through holes 27 for connecting the respective cathode electrodes 22 and the common cathode electrode 24 are formed by etching with hydrofluoric acid.

(10) After depositing Au on the entire surface, pattern etching is performed to draw the cathode electrode 22 to the cathode bonding pad 28 and to draw the anode electrode 23 to the anode bonding pad 34 by pattern etching. Anode wiring 3
Form one.

(11) CVD so as to cover the entire surface again
To grow an insulating film (third SiO 2 film) 19.

(12) Anode bonding pad 3
4 for connecting anode 4 to wiring 31 for anode and bonding pad 28 for cathode
The cathode second through-hole 32 for connecting the cathode wiring 30 is formed by etching the insulating layer 19 with hydrofluoric acid.

(13) After depositing Au on the entire surface, the cathode bonding pad 28 and the anode bonding pad 34 are formed by pattern etching.

(14) The semi-insulating GaAs substrate 11 on which these layers 12 to 34 are formed is cut into chips by dicing and separated, and a plurality of light emitting portions 21 are arranged in a line in the longitudinal direction. An array chip is formed.

The above embodiment has been described with respect to the case of the light emitting diode array in which the n-type is set up and the p-type is set down. However, the present invention can be similarly applied when the polarity of the light-emitting diode is reversed. In that case, an anode bonding pad is formed on the common anode electrode.

[0055]

According to the light emitting diode array and the method of manufacturing the same of the present invention, a plurality of light emitting diodes arranged in a line, a cathode bonding pad and an anode bonding pad for supplying electricity to the plurality of light emitting diodes, In a light-emitting diode array including a common cathode electrode or a common anode electrode interconnecting the cathode electrodes or anode electrodes of a plurality of light-emitting diodes, the cathode bonding pad or the anode bonding pad is replaced with the common cathode electrode or the common anode. Since the electrodes are provided on the electrodes with an insulating layer interposed therebetween, even if a common cathode electrode or a common anode electrode is provided, it is possible to provide an inexpensive light emitting diode array having a small chip size.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a surface including one light emitting unit and an electrode according to an embodiment of a light emitting diode array of the present invention.

FIG. 2 is a sectional view of a surface including a plurality of light emitting units of the light emitting diode array of FIG. 1;

FIG. 3 is a plan view of the light emitting diode array of FIG. 1;

FIG. 4 is a plan view showing a first example of a conventional light emitting diode array.

FIG. 5 is a cross-sectional view of the light emitting diode array of FIG. 4 along AA.

6 is a cross-sectional view of the light emitting diode array of FIG. 4 taken along line BB.

FIG. 7 is a circuit diagram of a conventional light emitting diode.

FIG. 8 is a plan view showing a second example of a conventional light emitting diode array.

FIG. 9 is a cross-sectional view of the light emitting diode array of FIG. 8 taken along the line EE.

FIG. 10 is a sectional view taken along line FF of the light emitting diode array of FIG. 8;

[Explanation of symbols]

 Reference Signs List 11 semi-insulating GaAs substrate 12 undoped GaAs buffer layer 13 p-type GaAs layer 14 p-type GaAlAs layer 15 n-type GaAlAs layer 16 n-type GaAs layer 17 first SiO2 film 18 second SiO2 film 19 insulating layer (third SiO2 film) DESCRIPTION OF SYMBOLS 21 Light-emitting part 22 Cathode electrode 23 Anode electrode 24 Common cathode electrode 25 First mesa etching groove 26 Second mesa etching groove 27 First through hole for cathode 28 Bonding pad for cathode 30 Wiring for cathode 31 Wiring for anode 32 For cathode 2nd through hole 33 anode through hole 34 anode bonding pad 41 semi-insulating GaAs substrate 42 undoped GaAs buffer layer 43 p-type GaAs layer 44 p-type GaAlAs layer 45 n-type GaAlAs layer 46 n-type Ga As layer 47 First SiO2 film 48 Second SiO2 film 50 Wiring for cathode 51 Light emitting unit 52 Cathode electrode 53 Anode electrode 54 Common cathode electrode 55 First mesa etching groove 56 Second mesa etching groove 57 Through hole for cathode 58 Cathode Bonding pad 59 anode bonding pad 60 light emitting section 71 n-type GaAs substrate 72 n-type GaAs buffer layer 73 n-type GaAlAs layer 74 p-type GaAlAs layer 75 p-type GaAs layer 76 cathode electrode 77 anode electrode 78 anode wiring 79 wire bonding Pad 80 Joint part 81 SiO2 film 85 Mesa etching groove A1-Am Common anode electrode B1-Bm Block C1-Cn Common cathode electrode D (1,1) -D (m, n) Light emitting diode

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F041 AA47 CA35 CA36 CA65 CA74 CA76 CA82 CA92 CA98 CB11 CB25 DA07 FF13

Claims (2)

[Claims] 1. A plurality of light emitting diodes arranged in a row, a cathode bonding pad and an anode bonding pad for supplying electricity to the plurality of light emitting diodes, and a cathode electrode or an anode electrode of the plurality of light emitting diodes are interconnected. A light emitting diode array having a common cathode electrode or a common anode electrode, wherein the cathode bonding pad or the anode bonding pad is provided on the common cathode electrode or the common anode electrode via an insulating layer. Characteristic light emitting diode array. 2. A plurality of light emitting diodes arranged in a row on a semiconductor substrate, and then a cathode bonding pad and an anode bonding pad for supplying electricity to the plurality of light emitting diodes are formed. In the method of manufacturing a light emitting diode array by forming a common cathode electrode or a common anode electrode for connecting a cathode electrode or an anode electrode of a light emitting diode to each other to form a light emitting diode array, the cathode bonding pad or the anode bonding pad Is provided on the common cathode electrode or the common anode electrode via an insulating layer.