JP2001251213A - Method and apparatus for calculating optimum dot product - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an efficient designing with respect to area and power. SOLUTION: A correlator conducts dot product arithmetic operation between bits of a pseudo-noise sequence and respective data words of a data stream. An inverting circuit receives one of the data words together with related pseudo- noise sequence bits and selectively inverts bits of the data word, in response to the respective pseudo-noise sequence bits. An adder tree consisting of a plurality of adders sums outputs of the inverting circuit. A carry-in bit input to each adder is combined with the pseudo-noise sequence bits.

Description

DETAILED DESCRIPTION OF THE INVENTION

TECHNICAL FIELD The present invention relates to code division multiple access (CDMA) devices, and more particularly, to a method and apparatus for calculating a dot product.

BACKGROUND OF THE INVENTION For many years, spread spectrum communication devices have been used in military and civilian settings. These devices use noise-like waves to spread (cover) the information bits, making the transmission bandwidth much wider than required for simple point-to-point communication. DS-CDMA
(Direct spreading code division multiple access) is a form of spread spectrum that uses conventional communication waveforms and pseudo-noise (PN) sequences to transmit information. The PN sequence is usually a linear feedback shift register (LFS).
R). Thus, the communication channels are separated by pseudo-random modulation applied and then removed in the digital domain, and not based on frequency as in frequency hopping CDMA.

[0003] CDMA has several important advantages in communication technology, and in particular, has improved capacity and quality as compared to low bandwidth multiple access wireless technology.

[0004] A direct sequence (DS) CDMA system must correlate two long data sequences in real time. With M being the data bit width, one of the sequences is 2xM bit wide complex data,
The other is a 2x1 bit complex PN sequence. In the correlation calculation, PN bit equal “0” is mapped to “1”, and PN bit equal “1” is mapped to “−”.
1 ". At a specific offset,
The correlation becomes a complex dot product calculation, which is
Formulated as:

(Equation 1) Where D (k) = D (k) _I + jD (k) _Q ) and the pseudo noise sequence

(Equation 2) Is a complex conjugate operator, and N is the vector length of the complex data and the PN vector.

In a high-quality DS-CDMA system,
To perform the correlation operation quickly and efficiently, a parallel dot product operator is required. Usually, N is a very large number, so the parallel dot product operators must be parallel one by one. Therefore, a large circuit area is required for calculating dot products.

Therefore, there is a need for an efficient method and apparatus for calculating dot products with large integral lengths.

SUMMARY OF THE INVENTION The present invention provides a correlator (corr) for performing dot product operations on bits of a pseudo-noise sequence and on respective data words of a data stream.
elator). Each of the inverting circuits receives one of the data words together with the associated pseudo-noise sequence bits and selectively inverts the bits of the data word according to the respective pseudo-noise sequence bits. An adder tree of adders sums the outputs of the inverting circuits. The carry-in bit input of the adder is combined with the bits of the pseudo noise sequence bit.

The present invention offers significant advantages over the prior art. To obtain a dot product of two vectors, L multiplication and L-1 addition are generally required, whereas the present invention requires the expensive 2D correlator.
Does not require a complement multiplier. Adder carry import saves the overall level of L adders by performing two's complement arithmetic. Thus, gate calculations and power consumption are reduced.

DETAILED DESCRIPTION OF THE INVENTION The present invention can be better understood with reference to the accompanying drawings, FIGS. In the figures, the same components have the same reference numerals.

[0010] As mentioned above, DS-CDMA systems require a correlation operation that can be expressed as:

(Equation 3) Where D (k) = D (k) _I + jD (k) _Q ) and the pseudo noise sequence

(Equation 4) Is a complex conjugate operator, and N is the complex data and PN vector length. D (k) _I is the real part of D (k) and D (k) _Q is the imaginary part of D (k). D (k) _I and D (k) _Q are each M bits wide. Similarly, PN (k) _I is the real part of PN (k) and PN (k) _Q is the imaginary part of PN (k). PN
(K) _I and PN (k) _Q are each 1 bit wide.

The above equation can be expressed as follows.

(Equation 5) .., N / L is the number for completing the integration of N lengths, and L is the width of the parallel dot product generator.

[0012] As described above, PN _I and PN _Q is, LFSR
Is a 1-bit value generated as a stream of “0” and “1”. These binary numbers are
Usually mapped to "1" and "-1". Therefore, A
_{Taking i} as an example, PN _I (k) = 1 (that is, PN _I (k)
Is mapped to -1), then PN _I (k) D _I (k)
Is equal to the two's complement of D _I (k). M-bit number D _I
The two's complement of (k) is equal to 2 ^M -D _I (k), and each D _I
(K) It can also be calculated as bit inversion and addition of 1.

FIG. 1 shows an addition tree circuit 10 for calculating A _i , B _i , C _i , and D _i . Addition tree circuit 10
Comprises a first level exclusive OR gate 12, indicated by exclusive OR gates 12a through 12p, respectively. In this embodiment, L = 16. Each exclusive OR gate receives an M-bit value for D (k),
Each bit of D (k) is exclusive-ORed with PN (k). The D input and PN input of each gate are A _i , B _i ,
It depends on whether C _i and D _i are calculated. If A _i has been calculated, the D input of exclusive OR gate 12 is
From DI (1) to DI (L), receiving at i = 1, exclusive-OR gate 12 receives from PN _I (1) to PN _I (L). FIG. 2 illustrates such an exclusive OR circuit 12.
Indicates a. The input shown here is for i = 1, k = 1
This is for calculating A _i .

Returning to FIG. 1, the output of each exclusive OR gate 12 has an M-bit output. A pair of exclusive OR gates 12 is connected to the input of adder 14. In the illustrated embodiment, the outputs of gates 12a and 12b are connected to the input of adder 14a and gates 12c and 12b are connected.
The output of d is connected to the input of adder 14b and gate 12
The outputs of e and 12f are connected to the input of adder 14c, the outputs of gates 12g and 12h are connected to the input of adder 14d, the outputs of gates 12i and 12j are connected to the input of adder 14e, The outputs of the gates 12k and 12l are
4f, connected to the inputs of gates 12m and 12n,
The outputs of gates 12o and 12p are connected to the input of adder 14g and the outputs of gates 12o and 12p are connected to the input of adder 14h, but the addition may be performed in any order. Each adder is P
Receive one carry-in of N bits. In the illustrated embodiment, adder 14a has a bit PN (1)
Adder 14b receives bit PN (3), adder 14c receives bit PN (5), adder 14d receives bit PN (7), and adder 14e receives bit PN (9). , The adder 14f outputs the bit P
N (11), adder 14g receives bit PN (1
3), and the adder 14h receives the bit PN (15). Also in this case, as will be described in detail later,
The order in which the N bits are connected to the carry import is PN
There is no problem as long as the bits are received by the adder.

The next stage of the adder 16 receives the output of the pair of adders 14, each being referenced 16 a through 16 d. In the illustrated embodiment, adder 16a receives the M + 1 bit output from adders 14a and 14b, and adder 16b replaces adders 14c and 14d.
And the adder 16c receives the output from the adder 14e and the adder 14e.
4f, and the adder 16d receives the output from the adder 14g.
And the output from 14h. Each adder 16 also receives a unique PN bit. In the illustrated embodiment, adder 16a receives bit PN (2), adder 16b receives bit PN (6), adder 16c receives bit PN (10), and adder 16d receives bit PN (10). (14) is received.

The third-stage adder 18 includes 18a, 1
8b, and receives the output of the pair of adders 16. In the illustrated embodiment, adder 18
a receives the M + 2 bit outputs from adders 16a and 16b, and adder 18b receives the outputs from adders 16c and 16d. Each adder 18 also receives a unique PN bit. In the illustrated embodiment, adder 18a receives bit PN (4) and adder 18b
N (12) is received.

In the final stage, the adder 20 outputs the bit PN
Along with (8), the M + 3 outputs of the adders 18a and 18b are received. The output of the adder 20 is an M + 4 bit output. The remaining PN bits, ie, the bits not connected to one of the carry imports of adders 14-20, are passed to the adder shown in FIG. 3 described below.

In operation, the exclusive OR gate 12
Multiply (1's complement) by ± 1 according to the value of the associated PN bit. If the PN bit is 0, the D bit passes through the exclusive OR gate 12 unchanged. That is, D is multiplied by "1". If P
If the N bit is "1", the D bit is inverted.

After performing the ± 1 multiplication in exclusive OR gate 12, adder 14-20 performs the addition as in the equation for A _{i ,} B _i, C _{i, and} D _i and performs two's complement. Is converted. As mentioned above, a number's two's complement is determined in two steps. (1) invert that number of bits,
(2) Add “1” to the inverted bit. The circuit 10 is
Using the carry import of the various adders 14-16, add a "1" to the appropriate place. If the PN bit is equal to "0", the carry-in will be zero and therefore a one
Is not added. If the PN bit is “1”, 2
Requires the associated D bit to be inverted (performed by an exclusive OR gate) and the associated adder 1
“1” is added by the carry import of 4-20.
Since the circuit has only L-1 adders (15 in the illustrated embodiment) and L PN bits, one of the PN bits (PN (16) in the illustrated embodiment) is: It is received by an adder outside the adder tree circuit 10 (as shown in FIG. 3).

FIG. 3 shows a circuit 30 for calculating S. The circuit 30 comprises four adder tree circuits 10
0a, 10b, 10c, given the 10d reference numbers, respectively _{A i, B i, C i} , to calculate the D _i. Adder tree circuit
a receives PN _I and D _I, adder tree circuit 10b
Receives PN _Q and D _Q, and receives the adder tree circuit 10 c
Receives PN _I and D _Q, the adder tree circuit 10d
It includes a PN _Q, via the inverter 31, receives a D _I. The outputs of these circuits are A _i, B _i, C _i, D _i ,
The exception is that when the associated PN (16) is "1", each output is
"1" is reduced. The outputs of adder trees 10a and 10b are connected to the input of adder 32. Adder tree 10
PN (16) from b is connected to the carry import of adder 32. The outputs from adder trees 10c and 10d are connected to the inputs of adder 34. Adder tree 1
PN (16) from 0d is connected to the carry import of adder 32. The output of the adder 32 is
Is connected to one input. PN (16) from adder tree 10a is connected to the carry import of adder 36. The output of the adder 36 is connected to the register 38. The output of register 38 is connected to one input of AND gate 40 and the second input of m-bit AND gate 40 is connected to ACC Connected to the CLEAR (accumulate clear) signal. Incidentally, m is the bit width of S _Q and S _I. The output of the AND gate 40 is connected to another input of the adder 36. The output of register 38 is the S _I value. The output of adder 34 is connected to one input of adder 42. PN (16) from adder tree 10c is connected to the carry import of adder 42. The output of the adder 42 is connected to the register 44. The output of register 44 is connected to one input of an m-bit AND gate 46, and the second input of the AND gate is ACC CLEAR
(accumulate clear) signal. AND gate 4
The output of 6 is connected to another input of the adder 42. The output of register 44 is the _SQ value.

The AND gates 40 and 46 are illustrated in detail in FIG. Each bit in the S _Q output for the AND gates 46, each bit in the S _I output, the AND gate 4
0, one input of the AND gate 50 is connected to the other input of the AND gate 50. CLEA
Connected to R signal. This is because the accumulation registers 38 and 44
It is provided to clear the contents of.

During operation, the circuits shown in FIG. 3 and FIG.
It works as follows. The adders 32 and 34 respectively
Compute A _i + B _i , C _i + D _i (the addition of PN (16) from adder trees 10a and 10c is not performed; they are added to the sum by adders 36 and 42). Adders 36 and 42, along with registers 38 and 44,
Accumulate the values of A _i + B _i and C _i + D _I for the cycle,
Calculate S _I and S _Q.

FIG. 5 is a block diagram of a spread spectrum device 58 including the circuit 30 of FIG. The pseudo noise generator 60 outputs a sequence of pseudo noise words PN (k) to the circuit 30 together with the data stream D (k). The data stream D (k) can be any digital data stream that would benefit from communication using spread spectrum technology, and for analog communication signals, an A / D (analog to digital) converter 62 It may be translated into a digital signal or it may be a native digital signal such as the output of a computing device. The digital data stream D (k) and the pseudo noise sequence PN (k) are combined to output S as described above.

The present invention offers advantages not found in the prior art. In general, two vector dot products are
While requiring L multiplications and L-1 additions, the present invention does not require the expensive two's complement multipliers required by ordinary correlators. By using the carry import of an adder to perform a two's complement operation, L M-bit wide addresses can be saved. Therefore, gate count and power consumption are significantly reduced.

Although a circuit using specific values L and M has been shown for the sake of explanation, the circuit can be easily expanded or reduced by changing the values of L and M. Further, in the embodiment, the explanation has been given by the power of 2 of N, but the value of N may be another value.

The detailed description of the present invention has been given in the specific embodiments. However, as will be understood by those skilled in the art, these embodiments can be variously modified, and Forms are also possible. The invention is intended to cover modifications and other embodiments falling within the scope of the appended claims.

With respect to the above description, the following items are further disclosed. (1) A correlator for performing a dot product operation on each word of a pseudo-noise sequence and a respective word of a data stream, the correlator receiving one of the data words and an associated pseudo-noise sequence; And a plurality of adders for summing the outputs of the inverting circuits in response to the carry-in bit input connected to said pseudo noise sequence bits. A correlator comprising an adder tree having (2) The correlator according to claim 1, wherein the inverting circuit includes an exclusive OR gate. (3) the inverting circuit comprises a plurality of exclusive OR gates, each gate inputting one respective bit of the data word and inputting an associated pseudo-noise sequence for each data word. The second term correlator. (4) The correlator according to any one of (1), (2) and (3), further comprising a storage for storing the output of the adder tree. (5) The correlator according to claim 4, wherein the accumulator includes a register connected to an input and an output of the adder. 6. The correlator of claim 5, wherein the adder has a carry-in bit connected to one of the pseudo-random sequence bits.

(7) A method of performing a dot product operation on bits of a pseudo-noise sequence and respective words of a data stream, wherein the bits of each data word are selected in response to the pseudo-noise sequence bits associated therewith. And inverting the selectively inverted data words with associated pseudo-noise sequence bits in an adder tree. The method of claim 7, wherein the step of selectively inverting comprises performing an exclusive-or operation on each bit of the data word and a bit of the pseudo-random sequence associated with the data word. (9) The method according to (7) or (8), further comprising accumulating an output of the adder tree. 10. The method of claim 9, wherein said storing step comprises storing the stored sum in a register and combining with an output of an adder tree. The method of claim 9, wherein the adder tree comprises a plurality of adders, each having a carry-in bit input for receiving one of the pseudo-random sequence bits.

(12) A spread spectrum apparatus,
A circuit for generating a stream of data words, a pseudo noise sequence generator for generating a pseudo noise sequence, and a correlator for performing a dot product operation on the bits of the pseudo noise sequence and each data word, A correlator receives one of said data words and associated pseudo noise sequence bits;
An inverting circuit for selectively inverting the bits of each data word according to each pseudo noise sequence bit;
A spread-spectrum apparatus comprising: a plurality of adders for summing the output of the inverting circuit, the adder having a carry-in bit input coupled to the pseudo noise sequence bits. 13. The spread spectrum apparatus according to claim 12, wherein said circuit for generating a stream of data words includes an analog-to-digital converter. (14) The spread spectrum apparatus according to the twelfth or thirteenth aspect, wherein the inverting circuit includes an exclusive OR gate. (15) The inverting circuits each include a plurality of exclusive OR gates, each gate receiving a respective bit of one of the data words, each receiving a pseudo noise sequence bit associated with the data word. 15. The spread spectrum apparatus according to claim 14, wherein: (16) A twelfth, thirteenth, or first feature comprising a storage circuit for storing the output of the adder tree.
16. A spread spectrum apparatus according to item 4 or 15. (17) The spread spectrum apparatus according to item 16, wherein the accumulator includes a register coupled to an input and an output of an adder. (18) The spread spectrum apparatus according to item 17, wherein the adder has a carry-in bit input coupled to one of the pseudo-random sequence bits.

The dot product computing unit (30) is an L-
Uses one adder tree (10) and no multiplier. L is the length of the parallel dot product operation unit. Exclusive OR gate 12 provides a +1 multiplication function. Adders (14, 16, 18, 20, 32, 3
The carry import of 4) is used to form the two's complement.

[Brief description of the drawings]

FIG. 1 is a diagram schematically showing an adder tree.

FIG. 2 is a schematic diagram of a multiple-bit exclusive OR circuit used in the adder tree of FIG. 1;

FIG. 3 shows a dot product calculation circuit.

FIG. 4 shows a multiple bit and gate used in the circuit of FIG.

5 shows a spread spectrum device using the dot product operation circuit of FIG.

[Explanation of symbols]

Reference Signs List 10 adder tree 12 exclusive OR gate 14, 16, 18, 20, 32, 34, 36, 42 adder 30 dot product calculator 38, 44 register 40, 46, 50 AND gate 60 pseudo noise generator 62 A / D converter

Claims (2)

[Claims] 1. A correlator for performing a dot product operation on a bit of a pseudo-noise sequence and a respective word of a data stream, the correlator receiving one of the data words and an associated pseudo-noise sequence; An inverting circuit for selectively inverting the bits of each data word in response to the sequence bits; and a plurality of adders for summing the outputs of the inverting circuits, the carry-in circuit being connected to the pseudo noise sequence bits. Correlator with adder tree having bit inputs 2. A method for performing a dot product operation on bits of a pseudo-noise sequence and respective words of a data stream, wherein the bits of each data word are selectively responsive to pseudo-noise sequence bits associated therewith. And summing the selectively inverted data words with associated pseudo-noise sequence bits in an adder tree.