JP2001251183A - Frequency oscillation device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a frequency oscillation device outputting a basic frequency which is accurately synchronized with the 1PPS signal of GPS. SOLUTION: A basic frequency accurately synchronized with a 1PPS signal showing accurate one second from GPS is obtained by PLL control and a highly precise oscillation frequency is maintained. A deviation counter (12) by a digital circuit which is reset at every PPS is used for a phase detector. A processor (15) inputs the deviation quantity, calculates a manipulated variable by a proportional/integral feedback control algorithm so that the value becomes zero and outputs the manipulated variable to a D/A converter (17). An analog output voltage from the D/A converter (17) is given as the control voltage of a voltage control oscillator (11) and the desired accurate basic frequency can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a frequency oscillating device.

[0002]

2. Description of the Related Art The accuracy of a normal crystal oscillator is ± 50 ppm.
In the conventional high-precision oscillator, a specially selected high-precision crystal was installed in a thermostat to maintain high accuracy.

[0003]

The conventional high-precision oscillator has a problem that even if the accuracy of about ± 1 ppm can be maintained in a short period of time, it cannot cope with a long-term change over time and the cost is high. Was.

[0004]

The conventional high-precision oscillator attempts to maintain the initially set high accuracy by an open loop. According to the present invention, a highly accurate Coordinated Universal Time (U.S.
1 PPS (1 P) indicating the exact one second based on TC)
The basic frequency synchronized with the signal (ulse Per Second) is obtained by feedback control to maintain the high-precision oscillator frequency.

[0005] This feedback control is performed by the PL shown in FIG.
This is shown by a block diagram of L (Phase-Locked Loop) control. Absolute time is GP
An accurate time can be known at one second intervals from the 1PPS signal of S, and the frequency error of the crystal oscillator can be corrected every one second. The frequency error can be detected as a phase error. This phase error detection and correction control uses P
Apply LL control.

Here, ω _c is the target angular velocity of the crystal oscillator,
φ _i indicates a phase deviation, and t indicates time. φ _i−1 is input to the transfer function G (z) (2), and its output is provided to the voltage controlled oscillator (3). Voltage controlled oscillator (3)
Denotes a crystal oscillator having a voltage control terminal capable of outputting a frequency proportional to the input voltage. Output ω _c t + φ _i of the voltage controlled oscillator (3) is the next step ω _c t + φ
_i-1 (z- ¹ (4) indicates the delay). This section is compared with the target frequency omega _{c t} comparator (1), the phase difference phi _i-1 loop are determined.

In the PLL feedback system shown in FIG. 1, the time t is 1 second (synchronous with 1 PPS), and the entire system is 2 seconds.
By dividing by π and normalizing, the whole system can be displayed in frequency. This block diagram is shown in FIG. Considering the input ω _c t + φ _i of the comparator (1), t = 1
From Is displayed as follows. Here, _{f c} is the target frequency of the crystal _{oscillator, φ i~1 / 2π = e i} -1 indicates the frequency deviation of 1 second. To determine the frequency deviation _{e i-1} specifically counts the frequency for accurate 1 second (1PPS), (1) formula, the value obtained by subtracting the _{f c} from the count value the deviation _{e i-1} Becomes

The main factor that determines the behavior of the PLL phase control shown in FIG. 2 is the characteristic of the transfer function G (z). In this system, the phase error correction has a long cycle of every second and the control amount is as small as about ± several ppm. As a transfer function characteristic of the system in such an environment, a long-term error is set to 0.
It is generally said that proportional-integral feedback control (hereinafter referred to as PI control) that can be controlled is effective. In particular, if the comparator (1) is constituted by a digital circuit, it is possible to control even the least significant bit, and control with extremely high precision can be expected.

If the transfer function G (z) is a linear function with respect to z, only the proportional control is performed, the deviation remains even if the gain is increased, and the phase error cannot be reduced to zero. PI control can be achieved by making the transfer function G (z) a quadratic function.

As an obvious method of determining the transfer function G (z), an approach is made from a difference equation. Now, assuming that the input of the transfer function G (z) is X (z) and the output is Y (z), in PI control, this difference equation can be expressed as follows. e (n) = e (n-1) + x (n) (2) y (n) = y (n-1)-{αx (n) + βe (n)} (3) where e (n) Denotes an error counter, and α and β denote PI control constants. From this, the transfer function G (z) of PI control
Is shown as follows:

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described based on embodiments with reference to the drawings. FIG. 3 shows a specific example of the frequency oscillation device. The frequency oscillating device includes a voltage controlled oscillator (11), a deviation counter (12), an input latch circuit (13), a GPS
(14), processor (15), output latch circuit (1
6) and a D / A converter (17). The fundamental frequency output from the voltage controlled oscillator (11) is input to a deviation counter (12), and the deviation amount of the deviation counter (12) is latched by an input latch circuit (13) at the timing of the 1PPS signal.

The processor (15) includes a CPU or D
SP is used. In the processor, the amount of deviation from the input latch circuit (13) is input, the amount of operation is calculated from the PI control algorithm shown in equations (2) and (3), and the amount of operation is output to the output latch circuit (16). Output to However,
In applying the PI control algorithm, it is also possible to omit the expression (2) according to the situation and to perform only the proportional control with β = 0 in the expression (3). Output latch circuit (16)
The operation amount output from is converted into an analog voltage by the D / A converter (17) and applied as a control voltage to the voltage controlled oscillator (11).

The deviation counter (12) is constituted by the maximum deviation range number of bits of the count value between 1PPS signals.
After the deviation amount is latched in the input latch circuit (13) at each timing of the PS signal, it is immediately cleared. Further, the deviation amount is represented by a two's complement expression. Set the deviation counter (12) to 1
By clearing for each PPS signal, the deviation amount indicates the frequency deviation at that point, and the deviation amount serving as a proportional control element is determined, which is a feature of the present invention.

With the above configuration and operation, the GPS (14)
1PPS (1 Pulse Per S
econd) A fundamental frequency of 1 MHz or more synchronized with the signal, and a plurality of desired divided frequencies can be output from the deviation counter (12) as needed, and at the same time, the exact Coordinated Universal Time (UTC) can be known.

[0015]

According to the present invention, an accurate frequency which is usually 100 times or more of the crystal frequency accuracy can be obtained, and the UTC can be known. Further, by the PI control, it is possible to obtain an accurate frequency even with disturbances such as a change with time and fluctuations in temperature and voltage. In a general system, a processor is incorporated, and according to the present invention, a calculation load is as small as once per second. Therefore, it is not necessary to add a new processor, and an economic effect can be expected.

[Brief description of the drawings]

FIG. 1 is a diagram showing a block diagram of PLL phase error detection and control.

FIG. 2 is a diagram showing a PLL frequency control block diagram.

FIG. 3 is a diagram showing a system configuration of a frequency oscillation device.

[Explanation of symbols]

 Reference Signs List 1 comparator 2 transfer function 3 voltage controlled oscillator 4 delay 11 voltage controlled oscillator 12 deviation counter 13 input latch circuit 14 GPS 15 processor 16 output latch circuit 17 D / A converter

Claims (6)

[Claims] The frequency oscillating device includes a voltage controlled oscillator (1).
1), deviation counter (12), input latch circuit (1
3) A device comprising a GPS (14), a processor (15), an output latch circuit (16), and a D / A converter (17). 2. 1PPS output from GPS (14)
(1 Pulse Per Second) The output of the fundamental frequency synchronized with the signal, and the output of a plurality of divided frequencies as required, can be performed at the same time with the correct universal time (UTC)
The device is provided with a means for knowing. 3. A fundamental frequency output from the voltage controlled oscillator (11) is inputted to a deviation counter (12), and a deviation amount of the deviation counter (12) is latched by an input latch circuit (14) at a timing of 1PPS signal. An apparatus characterized by the above. 4. A deviation counter (12) comprising a number of bits necessary for a maximum deviation range of a count value between 1PPS signals. The deviation counter latches the deviation amount in an input latch circuit (13) for each 1PPS signal timing. The device is characterized in that it is cleared immediately and restarted. 5. A processor (15) inputs a deviation amount from an input latch circuit (13) at each timing of a 1PPS signal, calculates an operation amount from a proportional-integral feedback control algorithm, and outputs the operation amount to an output latch. Circuit (1
(6) The apparatus is characterized in that it is output. 6. An operation amount output from an output latch circuit (16) is converted into an analog voltage by a D / A converter (17) and applied as a control voltage of a voltage controlled oscillator (11). Be a device.