JP2001250954A - Semiconductor device and liquid crystal display device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and a liquid crystal display device having high reliability at a lower cost. SOLUTION: In this semiconductor device, a thin film field effect transistor is formed on a substrate 1 including source/drain regions 4a, 4b and a gate electrode 9b. A lower interlayer insulating film 11 is formed so as to be brought into contact with the gate electrode 9b, while including a silicon oxide film. An upper interlayer insulating film 24 is formed on the lower interlayer insulating film. A contact hole 12c is formed in the lower interlayer insulating film and the upper interlayer insulating film. A lower conductive film 26 is formed so as to be brought into contact with the lower interlayer insulating film thereunder. An upper conductive film 13c is formed so as to extend from the inside of the contact hole to a region positioned on the upper surface of the upper interlayer insulating film, and at least either the source region or the drain region is connected thereto.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, a liquid crystal display device and a method of manufacturing the same, and more particularly, to a semiconductor device capable of preventing occurrence of dielectric breakdown in an interlayer insulating film. And a method of manufacturing the same, a liquid crystal display device, and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, as one type of liquid crystal display device, a liquid crystal display device using a polysilicon thin film field effect transistor has been developed. The liquid crystal display device using the polysilicon thin film field effect transistor has the following advantages over the conventional liquid crystal display device using the amorphous silicon thin film field effect transistor.
That is, as a first advantage, a liquid crystal display device using a polysilicon thin film field effect transistor can realize a high definition display screen. A second advantage is that the drive circuit and the display pixel can be integrally formed on the substrate, so that the drive circuit is prepared on another circuit board or the like, and the display portion of the liquid crystal and the drive circuit are connected later. Thus, the manufacturing process of the liquid crystal display device can be simplified. Further, since the manufacturing process can be simplified as described above, the cost of the liquid crystal display device can be reduced as a result. In addition, low-temperature polysilicon technology using laser crystallization technology is advantageous for cost reduction, and a glass substrate that can be easily enlarged can be used as a substrate. Liquid crystal display devices using thin film field effect transistors have also been actively developed.

A liquid crystal display device using the above-described polysilicon thin film field effect transistor has, for example, a structure as shown in FIG. FIG. 8 is a schematic cross-sectional view showing a conventional liquid crystal display device, and shows a glass substrate on which a thin film field effect transistor which is a part of the liquid crystal display device is formed. A conventional liquid crystal display device will be described with reference to FIG.

Referring to FIG. 8, the liquid crystal display device has a drive circuit area and a display pixel area. On the glass substrate 101, a p-type thin film field effect transistor 117 is formed in the drive circuit region, and an n-type thin film field effect transistor 118 and a storage capacitor 119 are formed in the display pixel region.
Are formed.

In the drive circuit area, the glass substrate 10
1, a base film 102 is formed. On the base film 102, the source / drain regions 106a and 106b of the p-type thin film field effect transistor 117 and the channel region 107 are formed by a polysilicon film as a semiconductor film of the same layer. This source / drain region 106a,
A p-type conductive impurity is implanted in 106b.
An insulating film 108 serving as a gate insulating film is formed over the source / drain regions 106a and 106b and the channel region 107. In a region above the channel region 107, a gate electrode 109a is formed over the insulating film. The protective film 1 is formed on the gate electrode 109a.
11 are formed. Source / drain region 106
a, 106b, the protective film 111 and the insulating film 108
The contact holes 112a and 112b are formed by removing part of these by etching. Protective film 11 is formed from inside contact holes 112a and 112b.
Electrodes 113a, 1b so as to extend over the upper surface of
13b is formed. An insulating film 114 is formed on the electrodes 113a and 113b and the protective film 111.

In a display pixel area of a liquid crystal display device,
A base film 102 is formed on a glass substrate 101.
On the base film 102, the source / drain regions 104a and 104b of the n-type thin film field effect transistor 118 and the channel region 105 are formed by a polysilicon film as a semiconductor film of the same layer. In addition, the base film 1
02, source / drain regions 104a, 104b
And lower electrode 10 of storage capacitor 119 using a semiconductor film of the same layer as the semiconductor film forming channel region 105.
3 are formed. Source / drain regions 104a,
An insulating film 108 is formed on 104b, the channel region 105, and the lower electrode 103. This insulating film 10
Reference numeral 8 includes a portion functioning as a gate insulating film of the n-type thin film field effect transistor 118 and a portion functioning as a dielectric film of the storage capacitor 119. That is, channel region 1
The insulating film 108 located on the area 05 acts as a gate insulating film, and the insulating film 118 located on the lower electrode 103 acts as a dielectric film. In a region located on the channel region 105, the gate electrode 109b is formed on the insulating film 108.
Are formed. In a region located on the lower electrode 103, a common electrode 110 is formed on an insulating film 108 as a dielectric film. A protective film 111 is formed on the gate electrode 109b and the common electrode 110. By removing a part of the protective film 111 and the insulating film 108 by etching, the contact hole 112c is removed.
To 112e. This contact hole 1
The electrodes 113 c to 113 e extend from the inside of 12 c to 112 e to the upper surface of the protective film 111, respectively.
e is formed. An insulating film 114 is formed on the electrodes 113c to 113e and the protective film 111. Thereafter, in the display pixel region, a transparent electrode or the like is formed according to a normal process to manufacture a liquid crystal display device.

Next, a method of manufacturing the liquid crystal display device shown in FIG. 8 will be briefly described. Referring to FIG. 8, first, PECVD (Plasma Enhanced Chemical Vap) is placed on glass substrate 101.
or Deposition) to form the base film 102. As the base film 102, a two-layer film of a silicon nitride film and a silicon oxide film can be used. An amorphous silicon film is formed on the base film 102. By annealing the amorphous silicon film using an excimer laser, a polysilicon film to be a channel region of the p-type thin film field effect transistor 117 and the n-type thin film field effect transistor 118 is formed. Thereafter, a resist film is formed on the formed polysilicon film. Using this resist film as a mask, a polysilicon film including the regions to be the channel regions 107 and 105 and a polysilicon film to be the lower electrode 103 are formed by dry etching. After that, the resist film is removed.

Next, an n-type conductive impurity is implanted into the polysilicon film to be the lower electrode 103 of the storage capacitor 119. Thus, the lower electrode 103 is formed. Next, an insulating film 108 serving as a gate insulating film and a dielectric film of the capacitor electrode 119 is formed. As the insulating film 108, for example, TEOS (Tetra Etyle Ortho Silicate)
Using TEOS as a source gas (hereinafter referred to as TEOS
A silicon oxide film formed by using PECVD can be used. A chromium film is formed on the insulating film 108 by using a sputtering method. A resist film is formed on the chromium film. Using this resist film as a mask, a part of the chromium film is removed by etching, so that gate electrodes 109a and 109b and common electrode 110 are formed. Thereafter, source / drain regions 104a and 104b are formed by injecting n-type conductive impurities into predetermined regions. Also, p
The source / drain regions 106a and 106b are formed by implanting the conductive impurities of the mold type. As the n-type conductive impurities, for example, phosphorus ions can be used, and as the p-type conductive impurities, for example, boron ions can be used. Thus, a p-type thin film field effect transistor 117 and an n-type thin film field effect transistor 118 are formed.

Next, a protective film 11 as an interlayer insulating film is formed on the gate electrodes 109a and 109b and the common electrode 110.
Form one. As the protective film 111, TEOS P
A silicon oxide film formed using ECVD can be used. Thereafter, activation annealing is performed at a heating temperature of 400 ° C. A resist film is formed on the protective film 111. By using the resist film as a mask, a part of the protective film 111 and the insulating film 108 is removed to form contact holes 112a to 112e. After that, the resist film is removed. Contact holes 112a to 112e
And a chromium film is formed on the upper surface of the protective film 111. The thickness of this chromium film is 100 nm. An aluminum alloy film is formed on the chromium film by a sputtering method. The thickness of this aluminum alloy film is 4
00 nm. A resist film is formed on the aluminum-based alloy film. By using the resist film as a mask, the aluminum-based alloy film and the chromium film are removed by etching to form electrodes 113a to 113e. After that, the resist film is removed. These electrodes 113a-
Reference numeral 113e includes the above-described chromium film and an aluminum-based alloy film.

Thereafter, the channel regions 105 and 107 are hydrogenated using hydrogen plasma to improve and stabilize the characteristics of the thin film field effect transistor.
Then, an insulating film 114 is formed over the electrodes 113a to 113e. Thus, a structure as shown in FIG. 8 can be obtained.

In the drive circuit region, an n-type thin film field effect transistor other than the illustrated p-type thin film field effect transistor 117 is simultaneously formed using the above-described method.
Then, these are combined to form a drive circuit. Also,
In the display pixel region, a display pixel is formed by electrically connecting the n-type thin film field effect transistor 118 and a separately formed transparent electrode. Further, the glass substrate 101 on which these elements are formed is bonded to another glass substrate on which a color filter and a counter electrode are formed. Then, a liquid crystal display device can be obtained by performing a predetermined process such as injecting and sealing liquid crystal into a gap formed between these glass substrates.

Here, TEOS used for the protective film 111 is used.
A silicon oxide film formed by PECVD has a low defect density and low interface state. Therefore, when a silicon oxide film formed by TEOS PECVD is used as the gate insulating film, the electrical characteristics of the transistor are improved. Also, as in the liquid crystal display device shown in FIG.
When a silicon oxide film formed by TEOS PECVD is used as described above, the silicon oxide film formed by TEOS PECVD has a low defect density and a small amount of unnecessary charge accumulation as described above. It is possible to prevent deterioration due to accumulation of a large amount of electric charge. Further, the coverage of the silicon oxide film by the TEOS PECVD is very good, and a step portion formed by the thin film field effect transistor can be easily flattened. For this reason, since a step portion is hardly formed on the upper surface of the protective film 111, it is possible to prevent the occurrence of disconnection or short circuit due to the presence of the step portion in a wiring, an electrode, or the like formed on the protective film 111. .

[0013]

As described above, the TEOS
A semiconductor device using a silicon oxide film formed by PECVD as an interlayer insulating film or a gate insulating film, or a liquid crystal display device using such a semiconductor device has the advantages described above. However, applying the silicon oxide film formed by TEOS PECVD to a semiconductor device has caused the following problems.

That is, when a silicon oxide film is formed using TEOS PECVD, TEOS PECVD
It is necessary to periodically perform a cleaning process on the reaction chamber of the film forming apparatus that performed the above in order to maintain the quality of the formed silicon oxide film. In this cleaning process, a large amount of NF ₃ gas having a relatively high unit price was consumed. As a result, the cost of forming a silicon oxide film formed by TEOS PECVD has been extremely high in consideration of the costs involved in such a cleaning process. In particular, when a silicon oxide film formed by TEOS PECVD is used as an interlayer insulating film, a certain thickness of the interlayer insulating film is required. Since the cleaning process is performed when the accumulated film thickness reaches a predetermined value, the frequency of performing the cleaning process in the reaction chamber increases. As a result, the cost associated with the cleaning process is increased, and the production cost of the final liquid crystal display device is increased.

Referring to FIG. 9, an n-type thin film field effect transistor 118 is provided in a display pixel region of the liquid crystal display device.
And display pixels composed of transparent ITO pixel electrodes 116 are arranged in a matrix. FIG. 9 is a partial circuit diagram of a display pixel region of the liquid crystal display device shown in FIG. The source region of the n-type thin film field effect transistor 118 is electrically connected to the source line 128. The gate electrode of the n-type thin film field effect transistor 118 is a gate line 129.
Is electrically connected to Further, a common wiring 126 is formed so as to extend substantially in parallel with the gate line 129. As described above, the source line 128, the common line 126, and the gate line 129 are formed to extend in different directions. Therefore, for example, the source line 12
8 and common wiring 126 overlap area 13
1, or a region 130 where the source line 128 and the gate line 129 overlap is formed. As shown in FIG. 10, the overlapping region 131 overlaps the common wiring 126 and the extending portion 127 of the electrode 113c corresponding to the source line 128 (see FIG. 9) via the protective film 111 (overlapping region). Wrap) area. Here, FIG. 10 is a schematic sectional view of another region of the liquid crystal display device shown in FIG. Referring to FIG. 10, common wiring 126
Is formed of a conductor film in the same layer as the gate electrode 109b.

In a region 131 where the extending portion 127 and the common wiring 126 overlap with each other via the protective film 111, if a defect caused by the presence of foreign matter such as dust occurs in the protective film 111, the electrode 113c A trouble such as a short circuit between the extension 127 and the common wiring 126 may occur.

In a conventional liquid crystal display device using an amorphous silicon thin film field effect transistor, a drive circuit is formed on a circuit board different from a substrate on which a display pixel region is formed. Therefore, it is necessary to carry out a step of connecting the display pixels on the substrate on which the display pixel region is formed and the drive circuits on the circuit substrate. When a defect such as a short circuit as described above occurs in the display pixel region, for example, when a short circuit occurs in the region 131, the defective liquid crystal display device is rescued by the following method. That is, first, the short-circuited portion is isolated by cutting the source line 128 where the short-circuit has occurred. Then, a redundant circuit is prepared on the drive circuit side, and wiring is performed so that a signal can be sent to the source line 128 from which the short-circuit portion has been newly separated by the redundant circuit. As a result, a signal can be sent to the pixel to a portion other than the short-circuit portion.

However, as described above, in a liquid crystal display device using a polysilicon thin film field effect transistor, a drive circuit is formed integrally on a glass substrate on which display pixels are formed. Therefore, in a liquid crystal display device using a polysilicon thin film field effect transistor, driving of a signal supplied to a display pixel region is performed so as to cope with an increase in wiring capacitance when transmitting a signal through the above-described redundant circuit. Increasing capacity was virtually difficult. As a result, as described above, the redundant circuit (repair wiring) is provided outside the display pixel area.
It is difficult to adopt a method of forming a liquid crystal display device to repair a short-circuited liquid crystal display device in a liquid crystal display device using a polysilicon thin film field effect transistor. As a result, when a short circuit occurs due to a defect or the like in the protective film 111 as described above, the liquid crystal display device in which the short circuit occurs is hardly remedied and becomes a defective product, and the yield in the manufacturing process of the liquid crystal display device is reduced. Was supposed to.

That is, in a conventional liquid crystal display device integrated with a drive circuit using a polysilicon thin film field effect transistor, cost reduction can be realized by integrally forming the drive circuit on a glass substrate. On the other hand, it is difficult to remedy a defect such as a short circuit caused by a defect in the interlayer insulating film, and thus, there has been a problem that the production cost increases due to a decrease in yield. Further, when a silicon oxide film formed by TEOS PECVD described above is used as an interlayer insulating film in order to reduce defects in the interlayer insulating film, the manufacturing cost also increases.

The present invention has been made to solve the above problems, and one object of the present invention is to
An object of the present invention is to provide a semiconductor device and a manufacturing method thereof capable of reducing the manufacturing cost.

Another object of the present invention is to provide a liquid crystal display device capable of reducing the manufacturing cost and a method for manufacturing the same.

[0022]

According to one aspect of the present invention, a semiconductor device includes a substrate, a thin film field effect transistor, a lower interlayer insulating film, an upper interlayer insulating film, a lower conductor film, and an upper conductor film. A thin film field effect transistor is formed on a substrate and includes source and drain regions and a gate electrode. The lower interlayer insulating film is formed on the thin film field effect transistor so as to be in contact with the gate electrode of the thin film field effect transistor, and includes a silicon oxide film. The upper interlayer insulating film is formed on the lower interlayer insulating film. A contact hole exposing at least one surface of the source and drain regions is formed in the lower interlayer insulating film and the upper interlayer insulating film. The lower conductor film is formed in a region located below the lower interlayer insulating film and is in contact with the lower interlayer insulating film. The upper conductor film is formed to extend from inside the contact hole to a region located on the lower conductor film on the upper surface of the upper interlayer insulating film, and is connected to at least one of the source and drain regions. (Claim 1).

With this configuration, the lower interlayer insulating film is provided between the gate electrode and the lower conductive film of the thin film field effect transistor and the upper conductive film extending to the upper surface of the upper interlayer insulating film. And at least two layers of insulating films, ie, an upper interlayer insulating film. If damage such as a crack occurs locally in the lower interlayer insulating film, a boundary surface exists between the upper interlayer insulating film and the lower interlayer insulating film. Propagation once stops at this interface. This can prevent the crack from propagating to the upper interlayer insulating film. As a result, the probability of occurrence of a defect penetrating the two layers of the lower interlayer insulating film and the upper interlayer insulating film is higher than when only one interlayer insulating film is formed on the gate electrode and the lower conductor film. Become smaller. For this reason, a decrease in the yield of the semiconductor device due to the occurrence of the above-described defects can be suppressed, and the manufacturing cost of the semiconductor device can be reduced.

When the interlayer insulating film is formed, a defect may occur in the interlayer insulating film from the beginning when the interlayer insulating film is formed. When only one interlayer insulating film is formed between the gate electrode and the upper conductive film, the existence of such a defect is immediately recognized by the upper conductive film formed on the upper surface of the interlayer insulating film and the gate electrode or the like. This causes a defect such as a short circuit with the lower conductive film. However, if the insulating film is composed of two or more layers of a lower interlayer insulating film and an upper interlayer insulating film as in the present invention, a defect caused by a foreign substance or the like may be generated when the lower interlayer insulating film is formed. Even if it occurs in the interlayer insulating film, the probability of occurrence of a defect in the upper interlayer insulating film is very low so that it overlaps substantially the same region as the region where such a defect has occurred. The probability of occurrence of defects that penetrate can be reduced. As a result, it is possible to prevent a short circuit from occurring between the gate electrode and the lower conductive film and the upper conductive film such as a wiring formed on the upper surface of the upper interlayer insulating film.

In the semiconductor device according to the first aspect, the silicon oxide film is preferably formed by a plasma enhanced chemical vapor deposition method using TEOS as a source gas.

In this case, it is used as a lower interlayer insulating film.
Silicon oxide film (TEOS P) by plasma enhanced chemical vapor deposition (PECVD) using TEOS as source gas
An ECVD silicon oxide film) is particularly excellent in film quality, such as having a low defect density and low charge accumulation. Therefore, it is possible to prevent the electric characteristics of the thin film field effect transistor immediately below the lower interlayer insulating film from deteriorating due to such charge accumulation. Further, insulation between the lower conductive film located below the lower interlayer insulating film and the upper conductive film located above the upper interlayer insulating film can be reliably performed.

Also, such a TEOS PECVD silicon oxide film has very good coverage,
The thin-film field-effect transistor can be reliably buried without forming a defect such as a void. In addition, the TEOS PEC
Since the flattening can be surely performed by the VD silicon oxide film, it is possible to prevent a step portion caused by the thin film field effect transistor from being formed on the upper interlayer insulating film. For this reason, it is possible to prevent a conductive layer such as a wiring formed on the upper interlayer insulating film from being disconnected due to a step portion caused by the thin film field effect transistor.

The total film thickness of the lower interlayer insulating film and the upper interlayer insulating film ensures the insulation between the thin film field effect transistor and the conductor film and at the same time reduces the influence of the step due to the thin film field effect transistor. Therefore, a certain thickness or more is required. In this case, when a TEOS PECVD silicon oxide film having the required film thickness is formed as an interlayer insulating film as in the prior art, the inside of a reaction chamber (chamber) of a film forming apparatus in which the TEOS PECVD silicon oxide film is formed is processed. Had to be cleaned at a high frequency. However, in the present invention, the lower interlayer insulating film is made of TE.
It is possible to apply an OS PECVD silicon oxide film and apply another lower-cost insulating film for the upper interlayer insulating film. Therefore, the thickness of the TEOS PECVD silicon oxide film can be reduced, so that the frequency of the cleaning process of the reaction chamber can be reduced. As a result, the manufacturing cost of the semiconductor device can be reduced.

In the semiconductor device according to one aspect of the present invention, it is preferable that the upper interlayer insulating film includes a silicon nitride film.

The cost of forming a silicon nitride film is lower than the cost of forming a TEOS PECVD silicon oxide film. This is because the cost of cleaning the reaction chamber is lower in the case of the silicon oxide film than in the case of the TEOS PECVD silicon oxide film. Therefore, the manufacturing cost of the semiconductor device can be reliably reduced.

In the semiconductor device according to the first aspect, it is preferable that the silicon nitride film is formed by using a plasma enhanced chemical vapor deposition method.

In this way, for example, when the silicon oxide film of the lower interlayer insulating film is formed by using the PECVD apparatus, the silicon nitride film can be formed by using the same apparatus. Therefore, it is not necessary to prepare a new film forming apparatus or the like in order to carry out the present invention, so that it is possible to prevent an increase in the manufacturing cost of the semiconductor device.

Further, if the silicon oxide film of the lower interlayer insulating film and the silicon nitride film of the upper interlayer insulating film are formed by the same plasma chemical vapor deposition method, the lower interlayer insulating film and the upper interlayer insulating film are continuously formed. Then, the semiconductor device can be formed using the same device, so that the manufacturing process of the semiconductor device can be simplified.

In the semiconductor device according to the first aspect, the ratio of the thickness of the upper interlayer insulating film to the thickness of the lower interlayer insulating film is preferably 0.5 or more and 6 or less.

In this case, if the above ratio is less than 0.5, the ratio of the thickness of the lower interlayer insulating film including the silicon oxide film to the total thickness of the upper interlayer insulating film and the lower interlayer insulating film becomes relatively large. When the TEOS PECVD silicon oxide film is used to form the lower interlayer insulating film, the cost reduction effect cannot be sufficiently obtained. On the other hand, when the above ratio exceeds 6, the thickness of the lower interlayer insulating film becomes thin. Therefore, when the TEOSPECVD silicon oxide film is used as the lower interlayer insulating film, the TEOSPECV
It becomes difficult to obtain a sufficient insulating effect and the like by the D silicon oxide film. Therefore, if the ratio is as described above,
High reliability due to the insulation effect of the silicon oxide film of the lower interlayer insulating film can be reliably obtained, and a sufficient cost reduction effect can be obtained.

A liquid crystal display according to another aspect of the present invention includes the semiconductor device according to the first aspect (claim 6).

In this way, the manufacturing cost of the liquid crystal display device can be reduced by applying the semiconductor device according to the present invention to the thin film field effect transistor formed in the display pixel region of the liquid crystal display device and its peripheral structure. At the same time, the reliability of the liquid crystal display device can be improved.

In a method of manufacturing a semiconductor device according to another aspect of the present invention, a thin film field effect transistor having source and drain regions and a gate electrode and a lower conductive film are formed on a substrate. A lower interlayer insulating film including a silicon oxide film is formed on the thin film field effect transistor and the lower conductor film so as to be in contact with the gate electrode and the lower conductor film of the thin film field effect transistor. An upper interlayer insulating film is formed on the lower interlayer insulating film. By partially removing the lower interlayer insulating film and the upper interlayer insulating film by etching, a contact hole is formed so as to expose at least one surface of the source and drain regions. A conductor film connected to at least one of the source and drain regions is formed so as to extend from inside the contact hole to a region located on the lower conductor film on the upper surface of the upper interlayer insulating film (claim Item 7).

With this configuration, the semiconductor device according to the first aspect of the present invention can be easily formed.

In the method of manufacturing a semiconductor device according to another aspect, the step of forming the lower interlayer insulating film may include the step of:
It is preferable to use a plasma enhanced chemical vapor deposition method using OS as a source gas (claim 8).

In this case, TEO is used as the lower interlayer insulating film.
An SPECVD silicon oxide film can be used.
Since the TEOS PECVD silicon oxide film has excellent film quality, insulation between the layer in which the thin-film field-effect transistor is formed and the upper conductor film formed on the upper interlayer insulating film can be reliably maintained. Also, TEOS PEC
Since the VD silicon oxide film has good coverage, it is possible to prevent the occurrence of a step on the upper interlayer insulating film due to the presence of the thin film field effect transistor. As a result, the reliability of the semiconductor device can be improved.

In the method of manufacturing a semiconductor device according to another aspect, it is preferable that the step of forming the upper interlayer insulating film includes a step of forming a silicon nitride film.

In this case, since the film formation cost of the silicon nitride film is lower than that of the TEOS PECVD silicon oxide film, the cost of the semiconductor device is smaller than when both the upper interlayer insulating film and the lower interlayer insulating film are formed by the TEOS PECVD silicon oxide film. Manufacturing costs can be reduced.

In the method for manufacturing a semiconductor device according to another aspect, it is preferable to use a plasma enhanced chemical vapor deposition method in the step of forming the silicon nitride film.
0).

In this case, when a TEOS PECVD silicon oxide film having excellent film quality is formed as the lower interlayer insulating film, the PE used to form the silicon oxide film is used.
The CVD apparatus can be directly applied to the formation of the silicon nitride film. Therefore, it is not necessary to newly prepare a film forming apparatus for forming the silicon nitride film. As a result, the reliability of the semiconductor device is improved by using the TEOS PECVD silicon oxide film having a good film quality as the lower interlayer insulating film, and at the same time, the increase in the manufacturing cost of the semiconductor device can be suppressed.

In the method of manufacturing a semiconductor device according to another aspect, in the step of forming the upper interlayer insulating film, the ratio of the thickness of the upper interlayer insulating film to the thickness of the lower interlayer insulating film may be 0.5 or more and 6 or less. It is preferable to form the upper interlayer insulating film so as to be as follows.

In this case, if the above ratio is less than 0.5, the ratio of the thickness of the lower interlayer insulating film to the total thickness of the upper interlayer insulating film and the lower interlayer insulating film becomes relatively large. Therefore, TEO is required to form a lower interlayer insulating film.
When an SPECVD silicon oxide film is used, a sufficient cost reduction effect cannot be obtained. On the other hand, when the above ratio is 6
Is exceeded, the thickness of the lower interlayer insulating film becomes thin, so that T
When an EOS PECVD silicon oxide film is used as a lower interlayer insulating film, it is difficult to obtain a sufficient insulating effect, a flattening effect, and the like by the TEOS PECVD silicon oxide film. As a result, if the ratio is as described above,
High reliability can be reliably obtained by the silicon oxide film of the lower interlayer insulating film, and a sufficient cost reduction effect can be obtained.

Preferably, the method for manufacturing a semiconductor device according to the above another aspect further includes a step of performing a hydrogen plasma treatment after the step of forming the lower interlayer insulating film and prior to the step of forming the upper interlayer insulating film. Item 12).

In this case, the lower interlayer insulating film functions as a protective film for protecting the thin film field effect transistor when performing the hydrogen plasma processing. Therefore, the thin film field effect transistor can be prevented from being damaged by the hydrogen plasma treatment.

Since the hydrogen plasma treatment is performed after the lower interlayer insulating film is formed, it is not necessary to consider the permeability of the hydrogen plasma in the hydrogen plasma treatment for the material used as the upper interlayer insulating film. Therefore, the degree of freedom in selecting the material of the upper interlayer insulating film can be further increased.

When a hydrogen plasma treatment is performed after an interlayer insulating film having a certain thickness is formed as in the prior art, the hydrogen plasma passes through the interlayer insulating film to reach the channel region of the thin film field effect transistor. Therefore, it is necessary to lengthen the processing time of the hydrogen plasma processing to some extent in proportion to the thickness of the interlayer insulating film. However, according to the present invention, if the thickness of the lower interlayer insulating film is made sufficiently smaller than the thickness of the conventional interlayer insulating film, the processing time of the hydrogen plasma processing can be greatly reduced. As a result, the time required for the manufacturing process of the semiconductor device can be reduced, so that the manufacturing cost of the semiconductor device can be reduced.

The method of manufacturing a semiconductor device according to the above another aspect preferably further includes a step of performing an annealing process prior to the step of performing a hydrogen plasma process.

As described above, since the annealing process for activating the impurities implanted into the source and drain regions is performed prior to the hydrogen plasma process, the hydrogen atoms implanted into the channel region and the like by the hydrogen plasma process are performed. Can be prevented from diffusing from the channel region to other regions due to heat or the like in this annealing process.
As a result, a highly reliable semiconductor device can be easily obtained.

In the method of manufacturing a semiconductor device according to the above another aspect, it is preferable that a step of forming an upper interlayer insulating film by using a plasma chemical vapor deposition method is performed continuously with the step of performing the hydrogen plasma treatment. Item 13).

In this case, if the hydrogen plasma processing is performed by using a PECVD apparatus for performing the plasma enhanced chemical vapor deposition, the hydrogen plasma processing and the step of forming the upper interlayer insulating film are performed continuously. be able to. As a result, the manufacturing process of the semiconductor device can be simplified, so that the time required for manufacturing the semiconductor device can be reduced.

In the method for manufacturing a semiconductor device according to the above another aspect, it is preferable that the upper interlayer insulating film includes a step of forming a silicon nitride film.

In this case, the silicon nitride film is TEOS P
Since the manufacturing cost is lower than the ECVD silicon oxide film,
The manufacturing cost of the semiconductor device can be reduced as compared with the conventional case where a TEOS PECVD silicon oxide film having a thickness substantially equal to the total thickness of the lower and upper interlayer insulating films is used as the interlayer insulating film.

In the method of manufacturing a semiconductor device according to the above another aspect, a cleaning step of removing foreign matter from the surface of the lower interlayer insulating film after the step of forming the lower interlayer insulating film and prior to the step of forming the upper interlayer insulating film. It is preferable to further provide (claim 15).

In this way, when foreign substances such as dust are attached to the surface of the lower interlayer insulating film, these foreign substances can be surely removed by this cleaning step. For this reason, it is possible to prevent the occurrence of defects in the upper interlayer insulating film due to such foreign matter. As a result, it is possible to reliably prevent a problem such as insulation failure due to a defect in the upper interlayer insulating film, and to improve the reliability of the semiconductor device.

In the method of manufacturing a semiconductor device according to the above another aspect, it is preferable to use at least one of a contact cleaning method and a non-contact cleaning method in the cleaning step.

In the method of manufacturing a semiconductor device according to the another aspect, it is preferable that the cleaning step further includes a step of performing wet etching.

In this case, it is possible to reliably remove a foreign substance which is fixed to the surface of the lower interlayer insulating film by wet etching or is buried to some extent in the lower interlayer insulating film. As a result, it is possible to reliably prevent the occurrence of defects in the upper interlayer insulating film due to the foreign matter present on the surface of the lower interlayer insulating film.

A method of manufacturing a liquid crystal display device according to another aspect of the present invention uses the method of manufacturing a semiconductor device according to the above another aspect.

This makes it possible to easily form a liquid crystal display device according to the other aspect.

[0065]

Embodiments of the present invention will be described below with reference to the drawings. In the drawings below, the same or corresponding portions have the same reference characters allotted, and description thereof will not be repeated.

FIG. 1 is a schematic sectional view showing a liquid crystal display device according to the present invention. The liquid crystal display will be described with reference to FIG.

Referring to FIG. 1, the liquid crystal display device includes a glass substrate 1 as a substrate, an upper glass substrate 21, and a liquid crystal 20 held between the glass substrate 1 and the upper glass substrate 21. A base film 2 is formed on a glass substrate 1. In the drive circuit area of the glass substrate 1, a p-type thin film field effect transistor 17 is formed on the underlayer 2. The p-type thin film field effect transistor 17 includes source / drain regions 6a and 6b, a channel region 7, an insulating film 8 acting as a gate insulating film, and a gate electrode 9a.

On the underlying film 2, source / drain regions 6 a and 6 b formed using a semiconductor film and a channel region 7 are formed.
Are formed. Source / drain regions 6a, 6b
Is implanted with a p-type conductive impurity such as boron (B). An insulating film 8 acting as a gate insulating film is formed on the channel region 7. In the region located on the channel region 7, a gate electrode 9 a made of a chromium film is formed on the insulating film 8. On the gate electrode 9a and the insulating film 8, a lower interlayer insulating film 11 made of a TEOS PECVD silicon oxide film is formed. On the lower interlayer insulating film 11, an upper interlayer insulating film 24 made of a silicon nitride film is formed. The film thickness T1 of the lower interlayer insulating film 11 is 100 nm, and the film thickness T of the upper interlayer insulating film 24 is 100 nm.
2 is 400 nm. Source / drain regions 6a, 6
In the region located above b, contact holes 12a and 12b are formed by removing part of upper interlayer insulating film 24, lower interlayer insulating film 11 and insulating film 8. Electrodes 13a and 13b as conductor films are formed to extend from inside contact holes 12a and 12b to the upper surface of upper interlayer insulating film 24, respectively. The electrodes 13a and 13b are connected to the source / drain regions 6a and 6b, respectively. Electrodes 13a, 13b
An insulating film 14 is formed thereon.

In the display pixel area of the glass substrate 1,
As described above, the base film 2 is formed on the glass substrate 1, and the n-type thin film field effect transistor 18 and the storage capacitor 19 are formed on the base film 2. The n-type thin-film field-effect transistor 18 includes a source region 4a, a drain region 4b, a channel region 5, and an insulating film 8 acting as a gate insulating film.
And a gate electrode 9b. On the underlying film 2, a source region 4a, a drain region 4b, and a channel region 5 are formed using a semiconductor film. N-type conductive impurities such as phosphorus (P) ions are implanted into the source region 4a and the drain region 4b. On the channel region 5, an insulating film 8 acting as a gate insulating film is formed. In a region located on the channel region 5, a gate electrode 9b is formed on the insulating film 8. On the gate electrode 9b and the insulating film 8, a lower interlayer insulating film 11 is formed similarly to the drive circuit region. On the lower interlayer insulating film 11, an upper interlayer insulating film 24 is formed.
In regions located above source region 4a and drain region 4b, contact holes 12c and 12d are formed by removing a part of upper interlayer insulating film 24, lower interlayer insulating film 11, and insulating film 8. . An electrode 13 as an upper conductor film extending from inside the contact holes 12c and 12d to the upper surface of the upper interlayer insulating film and connected to the source region 4a and the drain region 4b, respectively.
c and 13d are formed.

The source region 4 a,
The lower electrode 3 formed of the same layer as the semiconductor film forming the drain region 4b and the channel region 5 is formed. On this lower electrode 3, an insulating film 8 as a dielectric film is formed. The portion of the insulating film 8 located on the lower electrode 3 functions as a dielectric film of the storage capacitor 19. Then, in a region located on the lower electrode 3,
The common electrode 10 is formed on the insulating film 8. A lower interlayer insulating film 11 is formed on the common electrode 10 and the insulating film 8. The upper interlayer insulating film 2 is formed on the lower interlayer insulating film 11.
4 are formed. By removing a part of the upper interlayer insulating film 24, the lower interlayer insulating film 11, and the insulating film 8, a contact hole 12e is formed. An electrode 13e is formed to extend from inside contact hole 12e to the upper surface of upper interlayer insulating film 24. An insulating film 14 is formed on the upper interlayer insulating film 24 and the electrodes 13c to 13e.

A contact hole 15 is formed in the insulating film 14 in a region located on the electrode 13d. An electrode Ia electrically connected to electrode 13a extends from inside contact hole 15 to the upper surface of insulating film 14.
A TO (tin-added indium oxide) pixel electrode 16 is formed. On the ITO pixel electrode 16 and the insulating film 14,
An alignment film 36a is formed.

The p-type thin film field effect transistor 17,
N-type thin film field effect transistor 18 and storage capacitor 19
The upper glass substrate 21 is arranged so as to face the surface of the glass substrate 1 on which is formed. A color filter 23 is formed on a surface of the upper glass substrate 21 facing the glass substrate 1. A counter electrode 22 is formed on a surface of the color filter 23 facing the glass substrate 1. An alignment film 36b is formed on the surface of the counter electrode 22 facing the glass substrate 1.
Are formed. The liquid crystal 20 is held between the alignment films 36a and 36b.

Here, in the display pixel region, a lower interlayer insulating film 11 and an upper interlayer insulating film 24 are formed on the gate electrode 9b of the n-type thin film field effect transistor 18. Then, the source region 4a and the drain region 4b
The electrodes 13c and 13d connected to are formed to extend from inside the contact holes 12c and 12d to the upper surface of the upper interlayer insulating film 24, respectively. As shown in FIG. 2, electrode 13c connected to source region 4a includes an extension 27 for connection to a source line (see FIG. 9). The gate electrode 9b is provided under the extension 27.
A common wiring 26 is formed as a lower conductive film formed as the same layer as the above. An interlayer insulating film composed of two layers, the lower interlayer insulating film 11 and the upper interlayer insulating film 24, exists between the common wiring 26 and the extending portion 27 of the electrode 13c. Here, FIG. 2 is a schematic cross-sectional view of another region of the liquid crystal display device shown in FIG. As described above, since the two-layer interlayer insulating film exists between the electrode 13c and the common wiring 26, only one interlayer insulating film is formed between the common wiring 26 and the electrode 13c. As compared with the case, the probability of occurrence of dielectric breakdown can be reduced. That is, in the lower interlayer insulating film 11,
Considering the case where a defect such as a local crack has occurred due to the influence of impurities or the like, when the upper interlayer insulating film 24 is formed, a crack or the like is similarly formed on the region where the defect has occurred in the lower interlayer insulating film 11. Is extremely low. Therefore, the probability of occurrence of a defect penetrating the lower interlayer insulating film 11 and the upper interlayer insulating film 22 can be reduced. Therefore, it is possible to prevent occurrence of a defect such as dielectric breakdown between the common wiring 26 and the extending portion 27 of the electrode 13c. As a result, an operation failure of the liquid crystal display device caused by such dielectric breakdown can be prevented, and a highly reliable liquid crystal display device can be obtained.

FIG. 2 shows a region where the extension portion 27 for connecting the electrode 13c to the source line and the common line 26 overlap (source line / common line overlap portion). However, as shown in FIG. 9, in the liquid crystal display device, the gate line and the source line electrically connected to the gate electrode 9b are composed of two layers, the lower interlayer insulating film 11 and the upper interlayer insulating film 24. A region overlapping with the interlayer insulating film (source line / gate line overlap portion) is formed in the same manner. Each of these overlap portions has the same number as the number of pixels of the liquid crystal display device. The total area of these overlapping portions is relatively larger than the area of the portion acting as the gate electrode of the thin film field effect transistor. In the interlayer insulating film of the overlap portion having a relatively large area, if a dielectric breakdown occurs even at one location, a defect such as a malfunction of the liquid crystal display device also occurs. Therefore, higher reliability is required for the interlayer insulating film in the overlap portion. In the present invention, since the lower interlayer insulating film 11 and the upper interlayer insulating film 24 are used as the interlayer insulating film, the probability of occurrence of dielectric breakdown can be reduced as described above. As a result, the occurrence of defects in the liquid crystal display device can be reliably prevented.

Further, as will be described in a later-described manufacturing process, the interlayer insulating film located between the common wiring 26 and the electrode 13c is made of a silicon oxide film as compared with a case where only one silicon oxide film is formed. Since the film thickness of the lower interlayer insulating film 11 can be reduced, if a material whose film formation cost is lower than that of the silicon oxide film forming the lower interlayer insulating film 11 is used for the upper interlayer insulating film 24, the liquid crystal display will end up. The manufacturing cost of the device can be reduced.

In the liquid crystal display device according to the present invention, a silicon oxide film formed by TEOS PECVD is used as the lower interlayer insulating film 11. When a silicon oxide film is formed by the TEOSPECVD method to a thickness equal to the total thickness of the lower interlayer insulating film 11 and the upper interlayer insulating film 24, a reaction chamber (chamber) of a CVD apparatus in which the TEOS PECVD is performed. It was necessary to frequently clean the inside. However, in the liquid crystal display device according to the present invention, the formed film thickness of the silicon oxide film using the TEOSPECVD method is the conventional film thickness (total film thickness of the upper interlayer insulating film 24 and the lower interlayer insulating film 11).
The frequency of this cleaning of the reaction chamber can be reduced because it is about one fifth of the above. As a result, the amount of expensive NF ₃ gas and the like required for cleaning the reaction chamber can be reduced. Therefore, the manufacturing cost of the liquid crystal display device can be reduced.

As the lower interlayer insulating film 11, TEO
Although a silicon oxide film formed by the SPECVD method is used, the coverage of the silicon oxide film formed by the TEOS PECVD method is very good, so that a step formed by the n-type thin film field effect transistor 18 or the like is formed with a gap or the like. Can be implanted without For this reason, it is possible to prevent the occurrence of a problem that the electrical characteristics of the n-type thin film field effect transistor 18 are degraded due to the generation of a gap between the lower interlayer insulating film 11 and the n-type thin film field effect transistor 18 and the like. it can. As a result, a highly reliable liquid crystal display device can be obtained.

Further, by using a silicon nitride film having a lower film forming cost than a silicon oxide film (TEOS PECVD silicon oxide film) by the TEOS PECVD method as the upper interlayer insulating film 24, the manufacturing cost of the liquid crystal display device can be reliably reduced. Can be reduced.

Further, since the TEOS PECVD silicon oxide film having a low defect density is used as the lower interlayer insulating film 11, the n-type thin film field effect transistor 18 and the p-type
The electrical characteristics of the thin film field effect transistor 17 are very good.

The T used as the lower interlayer insulating film 11
Since the coverage of the EOS PECVD silicon oxide film is very good as described above, the upper surface of the upper interlayer insulating film 24 is smooth by absorbing steps due to the gate electrodes 9a and 9b. Therefore, the electrodes 13a to 13e formed on the upper surface of the upper interlayer insulating film 24
Can be prevented from being broken due to the influence of steps on the upper surface of the upper interlayer insulating film 24. Here, when the lower interlayer insulating film 11 is not formed and only the upper interlayer insulating film 24 made of a silicon nitride film is formed, the influence of the step due to the gate electrodes 9a and 9b strongly appears on the upper surface of the upper interlayer insulating film 24. . As a result,
Gate electrodes 9a, 9 are formed on the upper surface of upper interlayer insulating film 24.
Since a step corresponding to b is formed, disconnection may occur in the electrodes 13a to 13e due to the step. That is, it is understood that the lower interlayer insulating film 11 made of the TEOS PECVD silicon oxide film has a high function as a flattening film.

Since the film quality of the TEOS PECVD silicon oxide film is good and the defect density is low as described above,
By forming the lower interlayer insulating film 11 made of such a TEOS PECVD silicon oxide film so as to cover the n-type thin film field effect transistor 18 and the like, the n-type thin film field effect transistor 18 and the like can be reliably insulated. As a result, a highly reliable liquid crystal display device can be obtained.

If the upper interlayer insulating film 24 is formed of a silicon nitride film using PECVD, the PECVD apparatus used for forming the lower interlayer insulating film 11 can be used. For this reason, since it is not necessary to prepare a new manufacturing apparatus for carrying out the present invention, it is possible to suppress an increase in the manufacturing cost of the semiconductor device.

Further, after the lower interlayer insulating film 11 is formed by using the TEOS PECVD method, hydrogen plasma processing or the like is continuously performed in the PECVD apparatus, and the upper interlayer insulating film 24 is further formed. And the step of transferring the same to another manufacturing apparatus can be omitted. As a result, the manufacturing process of the liquid crystal display device can be simplified.

Further, by forming the display pixels of the liquid crystal display device by such a highly reliable thin film field effect transistor, it is possible to prevent the occurrence of defects in the display section of the liquid crystal display device and to eliminate defects. Thus, a liquid crystal display device having uniform display characteristics can be obtained.

FIGS. 3 to 7 are schematic cross-sectional views for explaining a method of manufacturing the liquid crystal display device shown in FIG. Figures 3-7
With reference to, a method for manufacturing a liquid crystal display device will be described.

First, a base film 2 (see FIG. 3) is formed on a glass substrate 1 (see FIG. 3) by using, for example, PECVD. As a base film, a two-layer film of a silicon nitride film and a silicon oxide film is used. An amorphous silicon film is continuously formed on the base film 2. The amorphous silicon film is annealed using an excimer laser to generate a polysilicon film. Then, a resist film is formed on the polysilicon film. By using the resist film as a mask and partially removing the polysilicon film by dry etching, the source / drain regions 6a and 6b, the source region 4a, the drain region 4b, the channel regions 7, 5 and the lower electrode 3 ( (See FIG. 3). After that, the resist film is removed. Next, a resist film is formed in a region other than the region where the semiconductor film to be the lower electrode 3 is located. Then, phosphorus ions are implanted into the polysilicon film to be the lower electrode 3. Thus, the lower electrode 3 is formed. Then, the above-described resist film is removed. Next, an insulating film 8 (see FIG. 3) made of a silicon oxide film acting as a gate insulating film and a dielectric film is formed. This insulating film 8 is made of TE
It is formed by using the OS PECVD method. The thickness of the insulating film 8 is 70 nm. Thereafter, a chromium film is formed on the insulating film 8 by using a sputtering method or the like. The thickness of the chromium film is about 200 nm. A resist film is formed on the chromium film. By using the resist film as a mask, the chromium film is partially removed by etching to form gate electrodes 9a and 9b and common electrode 10 (see FIG. 3). A storage capacitor 19 is formed from the common electrode 10, the lower electrode 3, and the insulating film 8. Thereafter, phosphorus ions are implanted into predetermined regions of the semiconductor film using the gate electrode 9b as a mask, thereby forming the source region 4a and the drain region 4a.
b, a channel region 5 is formed. Also, the gate electrode 9a
Ions are implanted into predetermined regions of the semiconductor film using the mask as a mask, so that the source / drain regions 6a and 6b
And a channel region 7 is formed. Thus, FIG.
The structure shown in FIG.

Next, as shown in FIG.
A lower interlayer insulating film 11 is formed on a, 9b and the common electrode 10. The lower interlayer insulating film 11 is a silicon oxide film and is formed by using TEOS PECVD. The thickness T1 of the lower interlayer insulating film 11 is 100 nm.

The TEOS PECVD silicon oxide film has excellent film quality with very good coverage and very low defect density, so that the n-type thin film field effect transistor 18 and the p-type thin film field effect transistor 17 can be reliably used. Can be insulated. As a result, it is possible to reliably prevent the problem that the n-type thin film field effect transistor 18 and the like malfunction due to insulation failure, so that a highly reliable liquid crystal display device can be obtained.

Next, activation annealing is performed. The heating temperature in this activation annealing treatment is 400 ° C. Next, physical cleaning such as brush cleaning or ultrasonic cleaning is performed as a cleaning step in order to remove foreign matter from the lower interlayer insulating film 11. This physical cleaning removes foreign substances present on the lower interlayer insulating film 11 and inside the lower interlayer insulating film. It is preferable to perform wet etching using a hydrofluoric acid-based etchant prior to the physical cleaning. As an etchant, for example, HF: NH ₄ F
= 1:10 BHF solution can be used. The substrate 1 on which the lower interlayer insulating film 11 is formed is immersed in the etching solution for about 30 seconds. In this way, when foreign matter is buried in lower interlayer insulating film 11, lower interlayer insulating film 11 around the foreign matter can be selectively etched. For this reason, foreign substances buried in the lower interlayer insulating film 11 can be exposed, so that these foreign substances can be surely removed by the above-described physical cleaning.

By performing such a physical cleaning step, foreign substances can be surely removed from the upper surface and the inside of lower interlayer insulating film 11, so that upper interlayer insulating film 24 can be removed from lower interlayer insulating film 11. In this case, it is possible to prevent the occurrence of a problem such as peeling due to a foreign substance existing in the apparatus. As a result, the reliability of the liquid crystal display device can be improved.

After the lower interlayer insulating film 11 is formed as described above, a cleaning step is performed.
When forming 4, the probability that a defect occurs in the upper interlayer insulating film 24 due to a foreign substance existing on the lower interlayer insulating film 11 can be reduced. As a result, it is possible to prevent the occurrence of a defect that penetrates the upper interlayer insulating film 24 and the lower interlayer insulating film 11 due to such a defect. It is possible to prevent the occurrence of problems such as insulation breakdown or short circuit. Since the reliability of the interlayer insulating film can be improved in this manner, the yield of the liquid crystal display device can be improved. In particular, in a liquid crystal display device integrated with a drive circuit, as shown in FIGS. 1 and 2, in which it is difficult to rescue a defective product by bypassing the wiring of a defective portion by using a redundant circuit, the yield is particularly improved. The effect of improving is remarkable.

By performing the wet etching step prior to the cleaning step as described above, it is possible to reliably remove impurities buried in the lower interlayer insulating film 11. As a result, the reliability of the liquid crystal display device can be further improved.

Next, as shown in FIG.
The substrate 1 is held in a chamber of the VD apparatus, and hydrogen plasma 25 is generated in the chamber to perform hydrogen plasma processing on the substrate 1. The hydrogen plasma processing time is about 30 minutes. By this hydrogen plasma treatment, the channel region 5,
7 is hydrogenated. As a result, the electrical characteristics of the p-type thin film field effect transistor 17 and the n-type thin film field effect transistor 18 can be stabilized and improved.

Since the activation annealing process is performed prior to the hydrogen plasma process, the channel regions 5 and 7 subjected to the hydrogen plasma process are not heated by the activation annealing process. For this reason, it is possible to prevent the problem that the concentration of hydrogen atoms in the channel regions 5 and 7 is reduced due to the diffusion of the hydrogen atoms implanted into the channel regions 5 and 7 by the heat of the activation annealing.

The lower interlayer insulating film 11 is formed during the hydrogen plasma treatment.
Acts as a protective film of the thin film field effect transistor in hydrogen plasma processing.

The silicon nitride film hardly transmits hydrogen plasma. Therefore, in a state where the silicon nitride film is formed on the n-type thin film field effect transistor 18 and the like, it is substantially impossible to perform hydrogen plasma processing. Therefore, as in the present invention, the upper interlayer insulating film 24 is formed.
If the hydrogen plasma treatment is performed in the state where the lower interlayer insulating film 11 is formed before forming the film, the upper interlayer insulating film 24 such as a silicon nitride film or the like may be an obstacle to the hydrogen plasma treatment. Material can be used. That is, the degree of freedom in selecting the material used for the upper interlayer insulating film 24 can be increased.

Conventionally, an interlayer insulating film such as a silicon oxide film is formed on the n-type thin film field effect transistor
Hydrogen plasma treatment was performed after the formation of about nm. Since the hydrogen plasma processing is performed with such a thick interlayer insulating film formed, the processing time of the hydrogen plasma processing is about one hour. However, in the present invention, the hydrogen plasma treatment is performed in a state where the lower interlayer insulating film 11 having a thickness of about 100 nm, which is smaller than the conventional thickness (about 20% of the conventional thickness), is formed. Therefore, the processing time of the hydrogen plasma processing can be reduced to about 30 minutes. That is, the processing time of the hydrogen plasma processing can be significantly reduced as compared with the related art. Therefore, the time required for the manufacturing process of the liquid crystal display device can be reduced.

Next, following the hydrogen plasma treatment, silane gas and ammonia gas are continuously introduced into the reaction chamber without taking out the substrate 1 from the reaction chamber. In this way, as shown in FIG. 6, a silicon nitride film as upper interlayer insulating film 24 is formed on lower interlayer insulating film 11. The thickness of the upper interlayer insulating film 24 made of this silicon nitride film is 4
It is about 00 nm.

As described above, by performing the hydrogen plasma treatment and the step of forming the upper interlayer insulating film 24 continuously, the manufacturing steps of the liquid crystal display device can be simplified.

Although the hydrogen plasma treatment and the step of forming the upper interlayer insulating film 24 are continuously performed using the same PECVD apparatus, the process for forming the upper interlayer insulating film 24 made of the silicon nitride film is performed. The film formation time is much shorter than the shortening (30 minutes) of the hydrogen plasma processing as described above. For this reason, the total time required for the manufacturing process of the liquid crystal display device can be reduced. Further, as described above, the hydrogen plasma treatment and the upper interlayer insulating film 24 are performed.
And the step of forming the upper interlayer insulating film 24 as described above, the processing time required for the hydrogen plasma processing and the step of forming the upper interlayer insulating film 24 is shorter than before. PE per sheet of substrate
The occupation time of the CVD apparatus can be reduced as compared with the conventional case.

Since the silicon nitride film as the upper interlayer insulating film 24 is formed by using the PECVD apparatus used for the formation of the lower interlayer insulating film 11 and the hydrogen plasma treatment, the upper interlayer insulating film 24 is formed. Therefore, there is no need to prepare a new film forming apparatus. As a result, investment costs for implementing the present invention can be reduced.

Also, as described above, TEOS PECVD
In the case where a silicon nitride film is formed by a PECVD apparatus, the frequency of cleaning processing in a reaction chamber can be much lower than in the case where a TEOS PECVD silicon oxide film is formed, as compared with the case where a silicon oxide film is formed. As a result, the manufacturing cost of the semiconductor device can be reduced. In addition, when a silicon nitride film is formed by a PECVD apparatus, an expensive material is not particularly required, so that the manufacturing cost of the semiconductor device can be reduced in terms of material cost.

The upper interlayer insulating film 24 is formed as another layer on the lower interlayer insulating film 11.
In one film, the probability of occurrence of a defect at the same location is low. Therefore, the lower interlayer insulating film 11 and the upper interlayer insulating film 2
4, the possibility of dielectric breakdown due to the occurrence of defects such as cracks at the same location can be reduced.

Next, a resist film (not shown) is formed on the upper interlayer insulating film 24. Using this resist film as a mask, contact holes 12a to 12e (see FIG. 7) are formed by removing part of upper interlayer insulating film 24, lower interlayer insulating film 11 and insulating film 8 by dry etching. After that, the resist film is removed. Upper interlayer insulating film 24
A chromium film is formed on the upper surface of the substrate and inside the contact holes 12a to 12e by a sputtering method. The thickness of this chromium film is 100 nm. An aluminum alloy film having a thickness of 400 nm is formed on the chromium film by a sputtering method. An upper chromium film having a thickness of 100 nm is formed on this aluminum alloy film. A resist film is formed on the upper chromium film. By sequentially performing wet etching using this resist film as a mask, electrodes 13a to 13e composed of three layers of a chromium film, an aluminum-based alloy film, and an upper chromium film (see FIG. 7)
To form An insulating film 14 is formed on the electrodes 13a to 13e. As the insulating film 14, a silicon nitride film is used.

Thus, the p-type thin film field effect transistor 17 is formed in the drive circuit region of the glass substrate 1.
Further, an n-type thin film field effect transistor 1 is provided in the display pixel region.
8 and the storage capacitor 19 are formed. Further, in the drive circuit region, an n-type thin film field effect transistor may be formed in another region not shown. Further, a p-type thin film field effect transistor may be formed in another region in the display pixel region. Then, in the drive circuit area,
A drive circuit is constituted by combining the p-type thin film field effect transistor 17 and the n-type thin film field effect transistor. In the display pixel region, a display pixel is formed by combining the n-type thin film field effect transistor 18 with a transparent electrode such as the ITO pixel electrode 16 (see FIG. 1).

That is, after the step shown in FIG. 7, the upper surface of the insulating film 14 is flattened. Thereafter, a contact hole 15 (see FIG. 1) is formed in the insulating film 14 in a region located on the electrode 13d. Then, an ITO pixel electrode 16 is formed so as to extend from inside the contact hole 15 onto the upper surface of the insulating film 14. Then, ITO
An alignment film 36a is formed on the pixel electrode 16.

Further, as shown in FIG. 1, an upper glass substrate 21 on which a color filter 23, a counter electrode 22, and an alignment film 36b are formed is prepared. This upper glass substrate 21
And the glass substrate 1 are arranged and fixed so as to face each other. Then, by injecting and sealing the liquid crystal 20 between the glass substrate 1 and the upper glass substrate 21 (between the alignment films 36a and 36b), a liquid crystal display device as shown in FIG. 1 is obtained.

Thus, the liquid crystal display device according to the present invention can be easily obtained. In the method for manufacturing a liquid crystal display device according to the present invention, the electrical characteristics are good,
In addition, a highly reliable thin film field effect transistor can be formed, so that a liquid crystal display device having high durability can be obtained. Thus, according to the present invention, FIG.
In the liquid crystal display device integrated with a driving circuit as shown in (2), two problems of low cost and high yield can be simultaneously achieved.

The embodiments disclosed this time are to be considered in all respects as illustrative and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the embodiments described above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[0110]

According to the present invention, by forming a lower interlayer insulating film and an upper interlayer insulating film on a thin film field effect transistor, a conductor film on the upper interlayer insulating film and a conductive film on the lower interlayer insulating film can be formed. A semiconductor device and a liquid crystal display device capable of reliably preventing a short circuit with a conductive film such as a gate electrode or a common wiring, realizing high reliability and reducing manufacturing costs. be able to.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing a liquid crystal display device according to the present invention.

FIG. 2 is a schematic sectional view of another region of the liquid crystal display device shown in FIG.

FIG. 3 is a first view illustrating a method of manufacturing the liquid crystal display device shown in FIG. 1;
FIG. 4 is a schematic cross-sectional view for explaining a process.

FIG. 4 shows a second method of manufacturing the liquid crystal display device shown in FIG.
FIG. 4 is a schematic cross-sectional view for explaining a process.

FIG. 5 shows a third method of manufacturing the liquid crystal display device shown in FIG.
FIG. 4 is a schematic cross-sectional view for explaining a process.

FIG. 6 shows a fourth method of manufacturing the liquid crystal display device shown in FIG.
FIG. 4 is a schematic cross-sectional view for explaining a process.

FIG. 7 shows a fifth method of manufacturing the liquid crystal display device shown in FIG.
FIG. 4 is a schematic cross-sectional view for explaining a process.

FIG. 8 is a schematic sectional view showing a conventional liquid crystal display device.

9 is a partial circuit diagram of a display pixel region of the liquid crystal display device shown in FIG.

FIG. 10 is a schematic cross-sectional view of another region of the liquid crystal display device shown in FIG.

[Explanation of symbols]

1 glass substrate, 2 base film, 3 lower electrode, 4a source region, 4b drain region, 5, 7 channel region, 6a, 6b source / drain region, 8, 14 insulating film, 9a, 9b gate electrode, 10 common electrode, 11
Lower interlayer insulating film, 12a to 12e, 15 contact holes, 13a to 13e electrodes, 16 ITO pixel electrodes, 17 p-type thin film field effect transistor, 18 n-type thin film field effect transistor, 19 storage capacitor, 20 liquid crystal, 21 upper glass substrate , 22 opposing electrode, 23 color filter, 24 upper interlayer insulating film, 25 hydrogen plasma, 26 common wiring, 27 extension.

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Norio Komatsu 3-3-5 Yamato, Suwa-shi, Nagano F-term (reference) in Seiko Epson Corporation 2H092 HA04 JA24 JA34 JA46 JB57 JB58 KA04 KB25 MA08 MA18 NA27 NA29 PA04 PA06 PA08 5F033 GG04 HH08 HH17 JJ08 JJ17 KK04 MM08 QQ00 QQ08 QQ11 QQ19 QQ37 QQ65 QQ73 QQ83 QQ91 QQ98 RR04 RR06 SS04 SS15 TT02 VV15 WW02 XX00 XX02 XX34 5F043 AA33 BB22 ADD33A22 HJ23 HL04 HL06 HL12 HL23 NN03 NN04 NN23 NN24 NN35 NN40 NN72 PP03 QQ11 QQ19 QQ25

Claims (17)

[Claims] A thin film field effect transistor formed on the substrate and including source and drain regions and a gate electrode; and the thin film field effect transistor so as to contact the gate electrode of the thin film field effect transistor. A lower interlayer insulating film including a silicon oxide film formed thereon, and an upper interlayer insulating film formed on the lower interlayer insulating film, wherein the lower interlayer insulating film and the upper interlayer insulating film include the source And a contact hole exposing at least one surface of the drain region and a lower conductive film formed in a region located below the lower interlayer insulating film and in contact with the lower interlayer insulating film; Extending from the inside of the contact hole to a region located on the lower conductive film on the upper surface of the upper interlayer insulating film And an upper conductive film connected to at least one of the source and drain regions. 2. The semiconductor device according to claim 1, wherein said silicon oxide film is formed by plasma enhanced chemical vapor deposition using TEOS as a source gas. 3. The semiconductor device according to claim 1, wherein said upper interlayer insulating film includes a silicon nitride film. 4. The semiconductor device according to claim 3, wherein said silicon nitride film is formed by using a plasma enhanced chemical vapor deposition method. 5. The semiconductor device according to claim 1, wherein a ratio of a thickness of said upper interlayer insulating film to a thickness of said lower interlayer insulating film is 0.5 or more and 6 or less. . 6. A liquid crystal display device comprising the semiconductor device according to claim 1. 7. A step of forming a thin-film field-effect transistor having source and drain regions and a gate electrode on a substrate, and a lower conductor film; and forming the gate electrode and the lower conductor film of the thin-film field-effect transistor. Forming a lower interlayer insulating film including a silicon oxide film on the thin film field effect transistor and the lower conductive film so as to contact the thin film field effect transistor; and forming an upper interlayer insulating film on the lower interlayer insulating film. Forming a contact hole so as to expose at least one surface of the source and drain regions by partially removing the lower interlayer insulating film and the upper interlayer insulating film by etching. A region located on the lower conductive film on the upper surface of the upper interlayer insulating film from inside the contact hole In so as to extend, and forming a conductive film connected at least one and of the source and drain regions, a method of manufacturing a semiconductor device. 8. The method according to claim 7, wherein in the step of forming the lower interlayer insulating film, a plasma enhanced chemical vapor deposition method using TEOS as a source gas is used. 9. The method according to claim 7, wherein forming the upper interlayer insulating film includes forming a silicon nitride film.
13. The method for manufacturing a semiconductor device according to item 5. 10. The method according to claim 9, wherein the step of forming the silicon nitride film uses a plasma enhanced chemical vapor deposition method. 11. The step of forming the upper interlayer insulating film, wherein the ratio of the thickness of the upper interlayer insulating film to the thickness of the lower interlayer insulating film is 0.5 or more and 6 or less. The method for manufacturing a semiconductor device according to claim 7, wherein a film is formed. 12. The method of manufacturing a semiconductor device according to claim 7, further comprising a step of performing a hydrogen plasma process after the step of forming the lower interlayer insulating film and prior to the step of forming the upper interlayer insulating film. Method. 13. The method of manufacturing a semiconductor device according to claim 12, wherein a step of forming said upper interlayer insulating film by using a plasma enhanced chemical vapor deposition method is performed successively to said step of performing said hydrogen plasma treatment. 14. The method according to claim 12, wherein forming the upper interlayer insulating film includes forming a silicon nitride film. 15. The method according to claim 7, further comprising, after the step of forming the lower interlayer insulating film, a cleaning step of removing foreign matter from the surface of the lower interlayer insulating film before the step of forming the upper interlayer insulating film. 15. The method for manufacturing a semiconductor device according to any one of 14. 16. The method according to claim 15, wherein said cleaning step further includes a step of performing wet etching. 17. A method for manufacturing a liquid crystal display device using the method for manufacturing a semiconductor device according to claim 7. Description: