JP2001250865A - Method for layout and wiring - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for layout and wiring capable of reducing the timing error caused by the discrepancy between the wiring capacitance estimated in designing of layout and wiring and the wiring capacitance after the layout is completed, and capable of reducing the design time. SOLUTION: Maximum/minimum parameters are prepared in a parameter preparation step 11, wiring layers and wiring lengths used in each net are estimated in a wiring estimation step 12, maximum/minimum capacitances for each net are calculated in a wiring capacitance estimation step 13, maximum/ minimum delays corresponding to the maximum/minimum capacitances are calculated in a delay calculation step 14, a delay propagation route for each flip-flop is searched in a delay propagation route searching step 15, and timing analyses on whether any setup error and any hold error are present or not are carried out in timing analysis steps 16 and 17, respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a layout and wiring method for designing cell layout and wiring in a layout and wiring area regarded as a circuit formation area on a semiconductor chip.

[0002]

2. Description of the Related Art Conventionally, in the above-described placement and routing method, a wiring capacitance which can occur in actual wiring is extracted, and a cell delay amount and a wiring delay amount calculated based on the extracted wiring capacitance are applied to adjust the timing. An analysis is performed, and when a timing error occurs, the layout (layout) of the arrangement and wiring of the netlist and the cell is corrected.

[0003] In the current state of the art of miniaturization of semiconductor integrated circuits, the wiring capacitance used in the final timing analysis is extracted by a 3D (three-dimensional) extraction method. The 3D extraction method is a method of extracting a wiring capacity that can occur in an actual wiring at the time of completion of a layout. The 3D extraction method considers a situation around a wiring path having a wiring capacity to be extracted, that is, the same layer. This is a method of extracting the wiring capacitance in consideration of not only the wiring path in the wiring layer but also the wiring paths in the upper and lower wiring layers. The tendency is that the wiring capacitance is large in a region where the wirings are dense, and small in a region where the wirings are sparse.

When designing cell layout and wiring using this 3D extraction method, in order to extract wiring capacitance, all wiring paths and wiring layers to be used are determined, and the layout is completed. Need to be. Here, a timing analysis is performed using the cell delay amount and the wiring delay amount calculated based on the extracted wiring capacitance. If a timing error occurs as a result, the netlist and the layout are changed until the timing error is resolved. After each correction, the operation of extracting the wiring capacitance by the 3D extraction method is repeatedly performed. Therefore, a large amount of arithmetic processing time is required, and therefore, the design time (TAT:
(Turn Around Time) is long.

Therefore, the wiring capacity is estimated while designing the cell arrangement and wiring in the placement and wiring area, and the timing analysis is performed using the cell delay amount and the wiring delay amount calculated based on the estimated wiring capacity. , Change the location where the timing error occurs to a cell with different driving capability,
Alternatively, a placement and routing method that shortens the design time by optimizing the timing by adding a buffer or the like is widely adopted.

[0006]

However, the estimation of the wiring capacitance in the above-described placement and routing method is a simple one which is determined according to the wiring length and wiring area of the net to be extracted. In this case, the wiring capacity per unit area and the wiring capacity per unit length are prepared as parameters, and the wiring capacity is estimated using these parameters. Therefore, the wiring capacity can be estimated for all the wiring paths regardless of the density of the surrounding wiring. For example, if the wiring length is the same in the same wiring layer, the same wiring capacity is estimated. Therefore, an error occurs between the wiring capacitance estimated by the above placement and routing method and the wiring capacitance extracted when the layout is completed.

Therefore, in the above placement and routing method, even if optimization is performed at the time of placement and routing and timing can be satisfied, different wiring capacitances are used in timing analysis at the time of layout completion, and a timing error occurs. there is a possibility.

As a method for preventing this, a method of setting a parameter for estimating a wiring capacitance used for placement and routing to a relatively large value can be considered. However, some circuits require a signal to be transmitted within a certain delay time due to timing specifications, and conversely, a part require a signal to be transmitted over at least a certain delay time. It is not always necessary to set a large value. The former is related to data signal in setup error,
The latter relates to a data signal in a hold error.

FIG. 2 is a circuit diagram for explaining a setup error and a hold error, and FIG. 3 is a timing chart of a data signal and a clock signal input to flip-flop 2_2 shown in FIG.

The pad 4 shown in FIG.
LK is input. The delay of the data signal input to the data input pin of the flip-flop 2_2 is based on the rising edge of the clock signal CLK input to the pad 4, and the plurality of clock tree buffers 1_0, 1_1,
.., Are transmitted via the clock pin of the preceding flip-flop 2_1 and the combinational circuit 3 between the flip-flops.
On the other hand, the delay of the clock signal input to the clock pin of the flip-flop 2_2 is similarly propagated via the plurality of clock tree buffers 1_0, 1_2,... With the rising edge of the clock signal CLK input to the pad 4 as a base point. Is done.

First, a setup error will be described with reference to FIG.
This will be described with reference to FIG. In the flip-flop 2_2, as shown in FIG. 3 (a), the clock signal required to capture the data signal input to the terminal D at the rising edge of the clock signal input to the terminal CK starts from the transition of the data signal. A minimum time t _S (set-up time) until the start-up is defined. Here, for example, in the flip-flop 2_2, the periphery of the wiring of the delay propagation path of the data system to which the delay of the data signal is transmitted is congested and the wiring capacitance of the wiring of the delay propagation path of the data system is relatively large. However, in the above-described conventional placement and routing method, the wiring capacity per unit area and the wiring capacity per unit length are prepared as parameters regardless of the density of the surrounding wiring, and the wiring capacity is determined using these parameters. Therefore, a relatively small wiring capacitance is estimated for the delay propagation path of the data system. Therefore, the transition time of the data signal is not significantly delayed, and no setup error occurs. However, in the timing analysis at the end of the layout,
A relatively large wiring capacitance is extracted for the delay propagation path of the data system. Therefore, the transition time of the data signal is greatly delayed, and the specified setup time cannot be satisfied, and a setup error occurs.

Next, the hold error will be described with reference to FIG.
This will be described with reference to FIG. In the flip-flop 2_2, as shown in FIG. 3B, the minimum time t _H (hold time) for holding the data signal from the rising of the clock signal input to the terminal CK to the transition of the data signal is specified. Have been. Here, even if the periphery of the wiring of the delay propagation path of the clock system to which the delay of the clock signal is transmitted is congested and the wiring capacitance of the wiring of the delay propagation path of the clock system is relatively large, The wiring capacity of the delay propagation path is relatively small. Therefore, the rise time of the clock signal input to the terminal CK does not delay so much and no hold error occurs. However, in the timing analysis at the time when the layout is completed, a relatively large wiring capacitance is extracted for the wiring of the delay propagation path of the clock system. Therefore, the rise time of the clock signal input to the terminal CK is greatly delayed, and the specified hold time cannot be satisfied, and a hold error occurs.

The present invention has been made in view of the above circumstances, and is intended to reduce a timing error caused by an error between a wiring capacitance estimated at the time of layout and wiring and a wiring capacitance extracted at the time of completion of layout. It is another object of the present invention to provide a placement and routing method that can reduce the design time.

[0014]

According to a first aspect of the present invention, there is provided an arrangement and wiring method for designing cell arrangement and wiring in an arrangement and wiring area regarded as a circuit formation area on a semiconductor chip. Prepare both the maximum parameter for estimating the maximum wiring capacity that can occur in the actual wiring and the minimum parameter for estimating the minimum wiring capacity that can occur in the actual wiring. The maximum delay amount corresponding to the maximum wiring capacity estimated using the maximum parameter or the minimum delay amount according to the type of signal transmitted through each delay propagation path Apply the minimum delay amount corresponding to the minimum wiring capacity estimated using the parameter for each delay propagation path, and And performing a timing analysis.

Incidentally, the maximum parameter in the present invention is specifically estimated based on the wiring capacitance extracted when the maximum capacitance value is obtained by 3D extraction, that is, in a state where the wirings are densely surrounded. Means the wiring capacitance parameter. In addition, the minimum parameter is a case where the minimum capacity value is obtained by 3D extraction.
That is, it is a wiring capacitance parameter estimated based on the wiring capacitance extracted in a state where there is no wiring around.

According to the placement and routing method of the present invention, both a maximum parameter for estimating a maximum wiring capacity that can occur in actual wiring and a minimum parameter for estimating a minimum wiring capacity that can occur in actual wiring are prepared. In accordance with the type of signal transmitted via each delay propagation path obtained for each flip-flop in the circuit, the maximum delay amount corresponding to the maximum wiring capacity estimated using the maximum parameter or Since the minimum delay amount corresponding to the minimum wiring capacity estimated using the above minimum parameter is applied to each delay propagation path, and the timing analysis for the presence or absence of a timing error is performed, a setup error described below is performed. As in the case of the timing analysis for the presence / absence of a hold error, the wiring capacitance estimated during cell placement and wiring Out can be suppressed timing errors caused by errors of the wiring capacitance extracted upon completion. Therefore, the timing error in the final timing verification is reduced, and the design period of the semiconductor integrated circuit is shortened.

Here, the delay propagation path obtained for each flip-flop in the circuit is set to the first delay signal for data signal delay transmission.
And a second delay propagation path for transmitting a clock signal delay. For the first delay propagation path, the maximum delay amount corresponding to the maximum wiring capacity estimated using the maximum parameter is calculated. Apply and the second
It is preferable to apply the minimum delay amount corresponding to the minimum wiring capacity estimated using the above-described minimum parameter to perform the timing analysis for the presence or absence of the setup error.

The setup error due to the estimation error of the capacitance is caused, for example, by the fact that the wiring capacitance of the first delay propagation path through which the data signal input to the flip-flop is transmitted becomes larger than the estimated, and the second transmission of the clock signal. This occurs when the wiring capacitance of the delay propagation path is smaller than the estimated value. Therefore, for the first delay propagation path, the maximum delay amount corresponding to the maximum wiring capacity estimated using the maximum parameter is applied, and for the second delay propagation path, estimation is performed using the minimum parameter. Apply the minimum delay amount corresponding to the minimum wiring capacity,
Performing a timing analysis of the presence / absence of a setup error can prevent the occurrence of a setup error.

Further, the delay propagation paths obtained for each flip-flop in the circuit are classified into a first delay propagation path for data signal delay transmission and a second delay propagation path for clock signal delay transmission, For the first delay propagation path, the minimum delay amount corresponding to the minimum wiring capacity estimated using the minimum parameter is applied, and for the second delay propagation path, the maximum delay estimated using the maximum parameter is used. It is also a preferable embodiment to apply the maximum delay amount corresponding to the wiring capacitance of the above and perform a timing analysis for the presence or absence of a hold error.

A hold error due to a capacity estimation error is caused, for example, by the fact that the wiring capacity of the first delay propagation path through which the data signal input to the flip-flop is transmitted is smaller than the estimate, and the second delay through which the clock signal is transmitted. This occurs when the wiring capacity of the propagation path is larger than the estimated value. Therefore, for the first delay propagation path, the minimum delay amount corresponding to the minimum wiring capacity estimated using the minimum parameter is applied, and for the second delay propagation path, estimation is performed using the maximum parameter. When the timing analysis for the presence or absence of the hold error is performed by applying the minimum delay amount corresponding to the maximum wiring capacitance, the occurrence of the hold error can be prevented.

[0021]

Embodiments of the present invention will be described below.

FIG. 1 is a diagram showing each step of a placement and routing method according to an embodiment of the present invention.

In the placement and routing method of the present embodiment, first, in a parameter preparation step 11, a maximum parameter for estimating a maximum wiring capacity that can occur in actual wiring and a minimum parameter for estimating a minimum wiring capacity that can occur in actual wiring are provided. Prepare both the minimum parameters.

Next, in the wiring estimation step 12, when the automatic cell placement and the clock tree synthesis are completed, the wiring layers used and the length of each wiring are estimated from the placement information of each cell, and stored in a memory (not shown). Remember.

Further, the process proceeds to a wiring capacity estimation step 13, in which the information of the wiring layer is read from the memory, and the maximum capacity calculated using the maximum parameter and the minimum capacity calculated using the minimum parameter for each wiring. Respectively,
It is stored in a memory (not shown).

Then, the process proceeds to a delay calculation step 14, in which information of the above-mentioned capacity is read from the memory, the maximum cell delay of each cell and the maximum wiring delay of each wiring are obtained using the maximum capacity, and stored in a memory (not shown). Further, the minimum cell delay of each cell and the minimum wiring delay of each wiring are obtained using the minimum capacitance, and are stored in a memory (not shown).

Next, in a delay propagation path search step 15, a first delay propagation path for data signal delay transmission and a second delay propagation path for clock signal delay transmission are obtained for each flip-flop. Are stored in a memory (not shown).

Next, in a setup timing analysis step 16, the delay amount obtained in the delay calculation step 14 and the delay propagation path obtained in the delay propagation path search step 15 are read from the memory, and the data signal path in each flip-flop is read. In addition to applying the maximum delay amount, the minimum delay amount is applied to the clock signal path to verify whether there is a setup error. If it is determined that the setup error has occurred, the setup error is eliminated by changing to a cell having a different driving capability or adding a buffer in the combinational circuit on the flip-flop side.

Next, hold timing analysis step 17
, The delay amount obtained in the delay calculation step 14 and the delay propagation path obtained in the delay propagation path search step 15 are read from the memory, and the minimum delay amount is applied to the data signal path in each flip-flop, and the clock signal The maximum delay amount is applied to the route to verify the presence or absence of a hold error. If a hold error is determined, a delay buffer is added to the combinational circuit between the flip-flops to eliminate the hold error.

As described above, in this embodiment, in the timing analysis at the time of cell placement and wiring, the maximum parameter for estimating the maximum wiring capacity that can occur in the extraction after the actual wiring, and the By using the two parameters, the minimum parameter for estimating the minimum wiring capacity to be obtained, the timing error in the final timing verification is reduced and the design period of the semiconductor integrated circuit is shortened.

[0031]

As described above, according to the present invention,
Timing errors caused by errors between the wiring capacitance estimated at the time of placement and wiring and the wiring capacitance extracted at the time of completion of the layout are reduced, and the design time can be shortened.

[Brief description of the drawings]

FIG. 1 is a diagram showing each step of a placement and routing method according to an embodiment of the present invention.

FIG. 2 is a circuit diagram for explaining a setup error and a hold error.

FIG. 3 is a timing chart of a data signal and a clock signal input to a flip-flop 2_2 shown in FIG.

[Explanation of symbols]

 11 Parameter Preparation Step 12 Wiring Estimation Step 13 Wiring Capacity Estimation Step 14 Delay Calculation Step 15 Delay Propagation Path Search Step 16 Setup Timing Analysis Step 17 Hold Timing Analysis Step

Claims (3)

[Claims] In a placement and routing method for designing placement and routing of cells in a placement and routing area regarded as a circuit formation area on a semiconductor chip, a maximum parameter for estimating a maximum possible wiring capacity in actual wiring; Prepare both the minimum parameter for estimating the minimum wiring capacity that can occur in the actual wiring, and arrange and route the cells, and provide the delay propagation path for each flip-flop in the circuit.
Depending on the type of signal transmitted via each delay propagation path, the maximum wiring amount corresponding to the maximum wiring capacity estimated using the maximum parameter or the minimum wiring capacity estimated using the minimum parameter A placement and routing method, wherein a timing analysis for the presence or absence of a timing error is performed by applying a corresponding minimum delay amount to each delay propagation path. 2. A delay propagation path obtained for each flip-flop in the circuit is classified into a first delay propagation path for data signal delay transmission and a second delay propagation path for clock signal delay transmission, For the first delay propagation path, the maximum delay amount corresponding to the maximum wiring capacity estimated using the maximum parameter is applied, and for the second delay propagation path, the minimum delay estimated using the minimum parameter is used. 2. The placement and routing method according to claim 1, wherein a timing analysis for the presence / absence of a setup error is performed by applying a minimum delay amount corresponding to the wiring capacitance of (1). 3. The delay propagation paths determined for each flip-flop in the circuit are classified into a first delay propagation path for data signal delay transmission and a second delay propagation path for clock signal delay transmission, For the first delay propagation path, a minimum delay amount corresponding to the minimum wiring capacity estimated using the minimum parameter is applied, and for the second delay propagation path, the maximum delay estimated using the maximum parameter is used. 2. The placement and routing method according to claim 1, wherein a timing analysis for the presence / absence of a hold error is performed by applying a maximum delay amount corresponding to the wiring capacity of the first place.