JP2001249847A - マルチレベルキャッシュ転送時間の改善方法および装置 - Google Patents

マルチレベルキャッシュ転送時間の改善方法および装置

Info

Publication number
JP2001249847A
JP2001249847A JP2001040100A JP2001040100A JP2001249847A JP 2001249847 A JP2001249847 A JP 2001249847A JP 2001040100 A JP2001040100 A JP 2001040100A JP 2001040100 A JP2001040100 A JP 2001040100A JP 2001249847 A JP2001249847 A JP 2001249847A
Authority
JP
Japan
Prior art keywords
cache
memory
data
error
line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001040100A
Other languages
English (en)
Japanese (ja)
Other versions
JP2001249847A5 (https=
Inventor
Kenneth Walker Shawn
シャウン・ケネス・ウォーカー
Dean A Mulla
ディーン・エー・ムラ
Charles Soltis Donald Jr
ドナルド・チャールズ・ソルティス・ジュニア
L Ryon Terry
テリー・エル・リョン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HP Inc
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of JP2001249847A publication Critical patent/JP2001249847A/ja
Publication of JP2001249847A5 publication Critical patent/JP2001249847A5/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1064—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in cache or content addressable memories
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Detection And Correction Of Errors (AREA)
JP2001040100A 2000-02-18 2001-02-16 マルチレベルキャッシュ転送時間の改善方法および装置 Pending JP2001249847A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US507208 1990-04-09
US09/507,208 US6591393B1 (en) 2000-02-18 2000-02-18 Masking error detection/correction latency in multilevel cache transfers

Publications (2)

Publication Number Publication Date
JP2001249847A true JP2001249847A (ja) 2001-09-14
JP2001249847A5 JP2001249847A5 (https=) 2005-06-16

Family

ID=24017677

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001040100A Pending JP2001249847A (ja) 2000-02-18 2001-02-16 マルチレベルキャッシュ転送時間の改善方法および装置

Country Status (2)

Country Link
US (2) US6591393B1 (https=)
JP (1) JP2001249847A (https=)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6976204B1 (en) * 2001-06-15 2005-12-13 Advanced Micro Devices, Inc. Circuit and method for correcting erroneous data in memory for pipelined reads
US20040103255A1 (en) * 2002-11-25 2004-05-27 Howlett Warren Kurt Memory sub-array selection monitoring
US7363427B2 (en) * 2004-01-12 2008-04-22 Hewlett-Packard Development Company, L.P. Memory controller connection to RAM using buffer interface
US7437651B2 (en) * 2004-06-29 2008-10-14 Hewlett-Packard Development Company, L.P. System and method for controlling application of an error correction code (ECC) algorithm in a memory subsystem
US7627804B2 (en) * 2006-06-30 2009-12-01 Intel Corporation Memory device with speculative commands to memory core
US9176886B2 (en) * 2006-10-30 2015-11-03 Hewlett-Packard Development Company, L.P. Method and system for filling cache memory for cache memory initialization
JP2009053820A (ja) * 2007-08-24 2009-03-12 Nec Electronics Corp 階層型キャッシュメモリシステム
US8782348B2 (en) * 2008-09-09 2014-07-15 Via Technologies, Inc. Microprocessor cache line evict array
US8250435B2 (en) * 2009-09-15 2012-08-21 Intel Corporation Memory error detection and/or correction
US8533572B2 (en) * 2010-09-24 2013-09-10 Intel Corporation Error correcting code logic for processor caches that uses a common set of check bits
FR2993380B1 (fr) * 2012-07-10 2020-05-15 Morpho Procede pour proteger une carte a puce contre une attaque physique destinee a modifier le comportement logique d'un programme fonctionnel
US20140108705A1 (en) * 2012-10-12 2014-04-17 Sandisk Technologies Inc. Use of High Endurance Non-Volatile Memory for Read Acceleration
US9778982B2 (en) 2013-12-09 2017-10-03 Hewlett Packard Enterprise Development Lp Memory erasure information in cache lines
KR20170045806A (ko) 2015-10-20 2017-04-28 삼성전자주식회사 반도체 메모리 장치 및 이의 동작 방법
CN118737257B (zh) * 2024-08-29 2024-12-20 合肥康芯威存储技术有限公司 一种存储器的测试方法、系统、设备及介质

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5629950A (en) * 1992-04-24 1997-05-13 Digital Equipment Corporation Fault management scheme for a cache memory
US5444619A (en) 1993-09-27 1995-08-22 Schlumberger Technology Corporation System and method of predicting reservoir properties
US5604753A (en) * 1994-01-04 1997-02-18 Intel Corporation Method and apparatus for performing error correction on data from an external memory
US6161208A (en) * 1994-05-06 2000-12-12 International Business Machines Corporation Storage subsystem including an error correcting cache and means for performing memory to memory transfers
US5691958A (en) 1995-04-13 1997-11-25 Exxon Production Research Company Method for determining formation properties from seismic attributes
US5828981A (en) 1995-05-11 1998-10-27 Texaco Inc. Generating pore types and synthetic capillary pressure curves from wireline logs using neural networks
US5706194A (en) 1995-06-01 1998-01-06 Phillips Petroleum Company Non-unique seismic lithologic inversion for subterranean modeling
FR2738920B1 (fr) 1995-09-19 1997-11-14 Elf Aquitaine Methode de reconnaissance automatique de facies sismiques
US5860017A (en) 1996-06-28 1999-01-12 Intel Corporation Processor and method for speculatively executing instructions from multiple instruction streams indicated by a branch instruction
US5859999A (en) 1996-10-03 1999-01-12 Idea Corporation System for restoring predicate registers via a mask having at least a single bit corresponding to a plurality of registers
US6502218B1 (en) * 1999-12-16 2002-12-31 Intel Corporation Deferred correction of a single bit storage error in a cache tag array

Also Published As

Publication number Publication date
US6591393B1 (en) 2003-07-08
US20040025094A1 (en) 2004-02-05
US6874116B2 (en) 2005-03-29

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