JP2001244352A - Semiconductor device and fabrication method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce programming voltage and cell area of a floating gate type semiconductor storage device capable of writing and deleting electrically. SOLUTION: A double tunnel insulating layer is formed in a tunnel region to flow tunnel current, and a resonance tunnel effect, instead of FN tunnel effect, is used when charging and discharging electricity. This reduces operation voltage, flows tunnel current directly, prolongs the lifetime of a memory cell, better the holding ability of a memory since current does not flow without the voltage of resonance tunnel effect.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory, and more particularly to a memory cell (EEPROM cell) capable of electrically erasing written memory contents.

2. Description of the Related Art In this type of semiconductor memory such as an EEPROM, writing and erasing can be performed electrically by passing a tunnel current through an insulating thin film. As a tunnel insulating film, a silicon oxide film or a silicon nitride film is usually formed to a thickness of about 80 to 120 angstroms, and a voltage of several tens of volts is applied thereto.
The band gap of these tunnel insulating films is considerably larger than that of silicon. For example, the band gap of silicon is approximately 1.11 eV, while the band gap of silicon oxide film is approximately 9.0 eV. .

[0002] These insulator thin films can function as tunnel potential barriers for electrons and holes in silicon. When an electric field is applied to these insulator thin films, so-called Fowler = Nordheim tunneling (hereinafter referred to as FN tunneling). This phenomenon occurs, and a tunnel current flows through the tunnel insulating film. This is a phenomenon in which the application of an electric field causes the band of the tunnel insulating film to bend, which is the same as the case where the thickness of the insulator is reduced, and a tunnel current flows. The shape of the tunnel potential at this time is a triangular potential, which can be formally described by the same formula as the field electron emission in a metal.

However, in this method, when writing and erasing are repeated in the memory cell, electrons and holes are trapped in the tunnel insulating film, and the tunnel insulating film gradually deteriorates, and finally the tunnel insulating film is deteriorated. The dielectric breakdown of the insulating film occurs. This phenomenon is called dielectric breakdown with time, and the dielectric breakdown with time determines the life of the EEPROM as a memory element.

In recent years, there has been a demand for a reduction in device area due to a demand for miniaturization of a semiconductor device. To this end, it is desirable to reduce the voltage applied during programming as much as possible. This is because if the applied voltage can be reduced, the booster circuit can be simplified, the area can be reduced, and the withstand voltage of the select transistor for selecting the memory cell can be reduced, so that the area of the select transistor can be reduced as a result.

In order to reduce the voltage applied to the tunnel insulating film when writing and erasing data in the EEPROM, it is necessary to reduce the thickness of the tunnel insulating film. Because F
This is because the N tunnel current is determined by the electric field strength in the tunnel insulating film, and the same current flows at the same electric field strength.
In order to form the same electric field strength by lowering the applied voltage, it is necessary to reduce the film thickness.

However, when the thickness of the tunnel insulating film is reduced,
If the thickness is less than 50 angstroms, the tunnel current will flow directly instead of the FN tunnel current. The direct tunnel current is a tunnel current that flows without bending the band, and the current flows even when a high voltage is not applied. For this reason, there has been a problem that charges cannot be stably held in the floating gate, and information cannot be stably held for a long period of time. Therefore, there is a limit in reducing the thickness of the tunnel insulating film.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device capable of reducing the thickness of a tunnel insulating film, reducing the voltage applied to the tunnel insulating film, and stably retaining charges accumulated in a floating gate. It is to provide a manufacturing method.

[0007]

In a semiconductor device according to the present invention, in an electrically programmable memory cell, a tunnel region is formed by a double insulating film, and a tunnel current is generated by resonance instead of a conventional FN tunnel current. Tunnel current was used. Since the tunnel potential is formed doubly due to the formation of the double insulating film,
A quantum well is formed between two potential barriers,
There, energy levels of two-dimensional electrons are formed. When the energy of the electrons injected into the potential barrier is adjusted to this energy level, a tunnel current flows due to the resonance effect of the wave function of the electrons, while almost no current flows at other energies. This is called a resonance tunnel current. A specific voltage is applied to bring electrons into a predetermined energy state.

[0008]

In the structure formed by such a double insulating film,
Only when a specific voltage is applied, the resonance effect of the wave function occurs, so that electrons flow into or out of the floating gate through the double tunnel barrier. When no voltage is applied, the resonance tunnel effect does not occur, so that no tunnel current flows and no electrons flow out of the floating gate.

Therefore, unlike the conventional case of a tunnel insulating film having a single layer, even if the thickness of the tunnel insulating film is reduced, the holding characteristic does not deteriorate, and the voltage applied to the tunnel insulating film can be reduced. it can. Therefore, since it is not necessary to generate a high voltage, the boosting circuit can be simplified, and the device area can be reduced. Also, since the breakdown voltage of the select transistor for each cell can be kept low, the area of the select transistor can be reduced, and the risk of latch-up is greatly reduced because high voltage is not used. I do.

In general, the thickness of the tunnel oxide film is reduced,
When the component of the direct tunnel current in the tunnel current increases, the critical charge (hereinafter referred to as Qbd) for causing electrical breakdown of the oxide film increases. This is considered to be because, in the case of the direct tunnel current, unlike the FN tunnel current, it is not necessary to bend the band of the tunnel insulating film, so that the ratio of electrons passing near the conduction band where the electron trap density is high is reduced. ing. Therefore, the number of electrons trapped in the insulating film while passing through the tunnel barrier is reduced, and as a result, electrical breakdown of the tunnel insulating film is less likely to occur. Therefore, by reducing the thickness of the tunnel insulating film, the number of times of rewriting repeatedly can be increased.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 shows an FL according to an embodiment of the present invention.
1 is a sectional view of an OTOX type EEPROM. In FIG. 2, the structure other than the tunnel region 2 is the same as that of the conventional FLOTOX type EEPROM. FIG. 1 is an enlarged view of a cross section of the tunnel region 2 in FIG. EEPROM of the present invention
In the cell, a double tunnel insulating film is formed in the tunnel region 2.

FIG. 2 is a sectional view of a semiconductor device 1 (EEPROM cell) as one embodiment of the present invention. That is, a source region 10 and a drain region 12 forming an inter-channel region formed in the semiconductor substrate 8, a floating gate 14 formed on the channel region, and a control gate formed on the floating gate 14. FLOTOX type EE with 16
PROM.

The floating gate 14 is covered with an insulating film (not shown) at the periphery and is electrically isolated.
A tunnel region 2 is provided between the floating gate 14 and the drain region 12 formed in the semiconductor substrate 8 to allow a charge to flow into the floating gate 14 by using a tunnel current and to flow a charge from the floating gate 14.

The control gate 16 has an insulating film 22 between itself and the floating gate 14 and is electrically insulated. The capacitance of the insulating film 22 between the control gate 16 and the floating gate 14 is equal to the floating gate. Tunnel region 2 between 14 and drain region 12
It is set to be large compared to the capacity at.

The tunnel region 2 includes a first insulating film 4 and a second insulating film 6 on the front and back of a conductor 3 as shown in FIG.
It has a heavy insulating film structure. Since the tunnel region 2 has a double insulating film structure, the resonance tunnel effect can be used. The first insulating film 4 and the second insulating film 6 sandwich the conductor 3 made of a polysilicon layer. The thickness of the conductor 3 sandwiched between the first insulating film 4 and the second insulating film 6 is optimally designed so that the resonance tunnel effect in the tunnel region can be used to the maximum.

Control gate 16 and drain region 1
2 between the floating gate 14
Charge is applied between the floating gate 14 and the drain region 12 formed in the semiconductor substrate 8 by using a tunnel current.
, Or charge can be discharged from the floating gate 14. With this operation, the potential in the floating gate 14 is externally controlled, and the threshold voltage (hereinafter referred to as Vt) in the channel region is controlled.
), And the memory can be electrically erased.

The semiconductor device 1 of this type has a control gate 1 for applying a high voltage to the tunnel region 2.
The area between 6 and floating gate 14 is larger than tunnel area 2. The structure other than the tunnel region 2 is the same as that of the conventional FLOTOX type EEPROM cell.

An example of a process for realizing the structure of the tunnel region shown in FIG. 1 will be described below. First, normal EE
An element isolation region is formed by a field oxide film on a silicon substrate by a standard method used to form a PROM cell, and then an N-type or P-type impurity semiconductor region is formed. Next, a gate oxide film is formed thereon. This gate oxide film has the same thickness as the gate oxide film of a normal transistor.

Next, a process for forming the tunnel region 2 is started.
A photosensitive resist is applied on this oxide film, and is exposed and developed so that only the tunnel region does not leave the photosensitive resist. Thereafter, wet etching with hydrogen fluoride is performed to remove the gate oxide film only in the tunnel region 2.

Next, a first insulating film 4 is first formed in the tunnel region 2 by a thermal oxidation process similar to the process of forming a normal tunnel oxide film. The first insulating film 4 may be formed by a nitride film or an oxynitride film instead of the oxide film. A predetermined thickness of polysilicon is grown thereon by a chemical vapor deposition method to form a conductor 3. If necessary, an impurity such as phosphorus or arsenic may be introduced into the polysilicon by diffusion, ion implantation, or the like, or doped polysilicon may be deposited.

Further, a second insulating film 6 is formed on the polysilicon as the conductor 3 by using a thermal oxidation method or a thermal nitridation method. The second insulating film 6 does not necessarily need to be formed by the thermal oxidation method or the thermal nitridation method, but may be formed by the chemical vapor deposition method. Thus, the second insulating film 6 is formed to a predetermined thickness. The thickness of the first and second insulating films 4 and 6 is, for example, about 40 angstroms, at which a direct tunnel effect occurs.

Next, a resist is applied thereon, and the polysilicon and the oxide film thereon are removed by dry etching, leaving only the tunnel region 2 by patterning.

After the formation of the double-layered tunnel insulating film in this manner, polysilicon is deposited thereon by a chemical vapor deposition method, which is patterned and then etched to form the floating gate 14. I do. Furthermore, a three-layer insulating film of oxide / nitride / oxide is preferably formed thereon by a chemical vapor deposition method.
Polysilicon is deposited thereon as a control gate 16 by a chemical vapor deposition method, patterned and etched to form a control gate 16.
To form

Next, the operation of the semiconductor device 1 (EEPROM memory cell) having such a resonance tunnel effect will be described.

When writing to a memory cell, a predetermined voltage is applied between the control gate 16 and the drain region 12. Current vs. applied voltage of resonant tunneling structure
FIG. 3 shows the voltage characteristics. As shown in FIG. 3, when the bias voltage takes a specific value Vb, the current reaches a local maximum value, and the current decreases when the bias voltage is higher or lower. When the bias voltage V is at a certain value Vb, the resonance effect is maximized, and _JRT has a peak value.

In an actual memory device, for example, an EEPROM cell, this bias voltage is given by the product of the write voltage Vpp applied to the cell and the capacitance coupling ratio γ of the cell. The capacitance coupling ratio is the ratio of the capacitance in the tunnel region 2 to the sum of the capacitance between the electrodes of the floating gate 14 and the control gate 16 and the capacitance between the floating gate 14 and the drain region 12. Vpp is usually generated using a booster circuit such as a charge pump. As a result, the bias voltage Vb is given by the following equation. Vb = γ × Vpp Normally, γ is designed to be as large as possible (approximately 0.9) in order not to increase Vpp unnecessarily.

FIG. 4 shows a band diagram of a resonance tunnel insulating film having a double structure. V ₀ is the tunneling barrier height, Lb is the width of the tunnel barrier, is Lw is the width of the quantum well surrounded by the tunnel barrier. Tunnel barrier height V
₀ is given by the interface band discontinuity (band offset) between the material forming the tunnel insulating film (the first insulating film 4 or the second insulating film 6) and the material forming the quantum well.

The width of each of the first and second tunnel barriers is so thin that a direct tunnel current flows (4).
0 ° or less), and the width of the conductor region (quantum well) surrounded by the tunnel barrier is such that the energy of the quantized bound state (resonance state) in the potential valley matches the energy of the incident electron. Designed for

At this time, assuming that the width of the quantum well surrounded by both tunnel barriers is Lw, 2Lw is the wavelength λe of the incident electron.
When it is equal to an integral multiple of, the electron wave incident on the quantum well resonates and interferes with the bound level of the quantum well to reinforce it, and the transmission probability of the double tunnel barrier becomes 1 theoretically. This condition corresponds to the incident electron energy Ex matches the specific energy ^{Er (n) = (h 2} / 2m e *) (nπ / Lw) 2 quantum well, i.e. resonate. Here, h is Planck's constant and _me * is the effective mass of electrons. Overall tunneling current of this structure is given approximately by ^{_{J RT = q / (2π 2}} h) ∫dEx∫dk t T * T.F. Here, h is Planck's constant. T is the probability amplitude of the transmitted wave, and T * T is the transmission probability. F is a term collectively expressing a distribution function of electrons appearing during integration.

There is a current component other than the tunnel current, that is, a component J _EX in which thermally excited carriers serve as hot carriers and pass over the barrier. Therefore, the total current is given by J = J _RT + J _EX . Since the current component of J _EX strongly depends on temperature, it is necessary to suppress J _EX as much as possible in order to obtain good operating characteristics at room temperature.

The tunnel current is determined not only by the electron distribution but also by the shape of the transmission coefficient, that is, the amount of T * T peak height, peak energy Exp, and full width at half maximum ΔExp. These quantities can be designed according to the structural parameters of the double barrier structure. Since it is generally difficult to perform this integration analytically, the parameters must be numerically integrated or experimentally determined. From the calculation results and the results of past experimental studies, the following is known.

1. If only the barrier width L _B is increased, Exp does not change, and only ΔExp decreases almost exponentially.

2. When only the well width Lw is increased, Exp,
Both ΔExp decrease.

3. If only the barrier height V ₀ is increased, Exp
Increase and ΔExp decreases exponentially.

By manipulating these three parameters, a dual-structure resonant tunnel barrier of the desired performance will be obtained. The height V _{0 of the} barrier is determined by the band structure of the substance used for the insulating film and the substance used for the conductor. In order to increase the tunnel current component, it is better to increase the barrier as much as possible. However, when the barrier is increased, the half width ΔExp becomes narrow and J _RT decreases. It is sufficient to reduce the barrier width L _B in order to prevent this.

The well width Lw simultaneously changes Exp and ΔExp. Generally, the energy of electrons in a semiconductor is not constant, but is distributed according to a Fermi-Dirac distribution. At room temperature, the energy distribution of electrons serving as carriers may be regarded as approximately following the Maxwell-Boltzmann distribution. Therefore, in order to maximize the tunnel current, the well width Lw may be adjusted to match the peak value of the energy distribution of electrons.

Next, an operation method of the semiconductor device 1 will be described. When writing, it is necessary to extract electrons from the floating gate 14, so Vpp is applied to the control gate 16 and the drain region 12 is set to zero [V]. Then, the capacitance between the control gate 16 and the floating gate 14 becomes
A relatively high voltage is applied between the floating gate 14 and the drain region 12 than between the control gate 16 and the floating gate 14 because the capacitance is relatively large as compared with the capacitance between the floating gate 14 and the drain region 12. Since the floating gate 14 and the drain region 12 are electrically coupled to each other via the above-described double-structured tunnel region 2, a predetermined voltage is applied to generate a resonance effect of a wave function. A resonant tunneling current flows through the tunnel insulating film, and electrons flow out of the floating gate 14.

Vpp is calculated and set in advance so as to have a voltage at which the resonance effect of the wave function just occurs with respect to the resonance level of the quantum well sandwiched between the double tunnel insulating films. Also, in this operation mode, the source is left open so that it is not electrically connected to anywhere.

In performing the erasing operation, the direction of the voltage between the control gate 16 and the drain region 12 may be reversed. Therefore, the control gate 16 is set to zero.
[V], and applying Vpp to the drain region 12 causes a resonant tunneling current to flow in a direction opposite to that during writing, so that electrons are injected into the floating gate 14.

When performing a reading operation, a relatively small voltage (Vdd) is applied to the source region 10 and the drain region 12 is set to zero [V]. Control gate 1
When a control voltage is applied to No. 6, a certain threshold (hereinafter referred to as V
When a gate voltage of not less than t) is applied, a current flows from the source region 10 to the drain region 12 due to the effect of forming an inversion layer in the channel region as in a normal MOS transistor. This threshold value changes depending on how much electrons are stored in the floating gate 14. For example, when a relatively large number of electrons are accumulated in the floating gate 14, Vt becomes high,
Conversely, when electrons are accumulated in a relatively small amount, Vt becomes low. It is possible to identify whether the information written in the semiconductor device 1 is 1 or 0 based on this difference in Vt.

As described above, the operation of the semiconductor device 1 according to the present invention is performed by using the conventional FN tunneling current.
It suffices to apply a voltage in exactly the same mode as the operation of the EPROM, and the peripheral circuits can be completely compatible with the prior art.

[0043]

According to the semiconductor device of the present invention, since the tunnel region has the double tunnel structure, the resonance tunnel current flows through the tunnel region only at a predetermined voltage.
The applied voltage can be reduced by reducing the thickness of the tunnel insulating film, and the life of the cell can be prolonged because a tunnel current flows directly. Further, since the tunnel current does not easily flow at a voltage other than the applied voltage of the resonance current, it is possible to increase the memory retention ability.

[Brief description of the drawings]

FIG. 1 is a diagram showing one embodiment of a tunnel area of a storage device of the present invention.

FIG. 2 is a diagram showing one embodiment of a storage device according to the present invention.

FIG. 3 is a diagram showing a relationship between current and voltage applied to a tunnel region.

FIG. 4 is a diagram illustrating a double tunnel structure.

[Explanation of symbols]

 Reference Signs List 1 semiconductor device 2 tunnel region 3 conductor 4 first insulating film 6 second insulating film 8 semiconductor substrate 10 source region 12 drain region 14 floating gate 16 control gate 22 insulating film

Claims (3)

[Claims] A source / drain region formed in a semiconductor substrate; a floating gate formed on the source / drain region; a control gate formed on the floating gate; An electrically erasable semiconductor device, comprising: a tunnel region that allows a charge to flow into or out of the floating gate by using a tunnel current between a gate and the drain region. A semiconductor device, comprising: a double insulating film formed with a first insulating film and a second insulating film, wherein a resonant tunneling current is used as a tunneling current in the tunnel region. 2. The semiconductor device according to claim 1, wherein the first insulating film and the second insulating film have a thickness equal to or less than a thickness through which a tunnel current flows directly. 3. The tunnel region is formed by forming a first insulating film, growing a polysilicon film, oxidizing or nitriding the polysilicon film, and depositing an insulating film thereon to form a second insulating film. 2. A semiconductor device for manufacturing a semiconductor device according to claim 1, further comprising a step of forming a first insulating film, a second insulating film, and a conductor film between the first insulating film and the second insulating film. Device manufacturing method.