JP2001237689A - Mos logic circuit and semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce power consumption by suppressing the leak current in an MOSFET in an OFF state in an MOS logic circuit composed of a deep submicron MOS having a low threshold voltage, which can operate at high speed with a low power supply voltage, for example. SOLUTION: This circuit is provided with a first inverter circuit 15A to operate on power supply voltages VDD and VSS for ordinary operation, a second inverter circuit 15B which operates on power supply voltages VDDH and VSSL higher than the power supply voltages VDD and VSS for overdrive operation, having an output amplitude greater than that of the first inverter circuit 15A and time constant circuits R1 and R2 for delaying the operation of this second inverter circuit 15B and a first MOS logic circuit 15A and a second MOS logic circuit are parallel connected between common input and output nodes.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for reducing power consumption due to a sub-threshold current of a MOSFET in a MOS logic circuit, for example, a low threshold voltage MO formed by a deep sub-micron process.
The present invention relates to a technique which is particularly useful when applied to a MOS logic circuit using an SFET.

[0002]

2. Description of the Related Art As a basic logic gate circuit in a MOS logic integrated circuit, for example, a CMOS as shown in FIG.
There is an inverter circuit. In a normal inverter circuit, the source of the N-channel MOSFET N1 is connected to the power supply voltage VSS on the negative side, the source of the P-channel MOSFET P1 is connected to the power supply voltage VDD on the positive side, and each gate is connected to a common input node IN. Each drain is connected to a common output node OUT. When a low-level signal equal to the power supply voltage VSS on the negative electrode side is input to the input node IN, the P-channel MOSFET P1
Is turned on, the N-channel MOSFET N1 is turned off, and the power supply voltage VDD on the positive electrode side is output to the output node OUT. Conversely, the power supply voltage V on the positive side is applied to the input node IN.
When DD is input, the power supply voltage VSS on the negative electrode side is output to the output node OUT.

Incidentally, a MOSFE in a MOS integrated circuit designed to operate even at a low power supply voltage VDD.
As shown in FIG. 15, as shown in FIG. 15, even when the gate-source voltage is in a region smaller than the threshold voltage Vth, the drain current does not become completely zero, and a minute current (sub-threshold current) flows. There is a disadvantage that a leak current is generated between the source and the drain. The subthreshold current varies exponentially with the gate-source voltage,
And a conventional MOS operating at a power supply voltage of 3 to 5 V.
In the -LSI, the threshold voltage Vth of the MOSFET is set to be somewhat high, so that when the gate-source voltage is 0 V, the sub-threshold current becomes so small that it can be ignored. It didn't matter much.

[0004]

In recent years, MOS devices have been miniaturized, and a deep submicron MOS technology capable of high-speed operation at a low power supply voltage has been put to practical use.
MOSFE formed by deep submicron process
Since the threshold voltage Vth of T is set low in accordance with the drive voltage, a subthreshold current that cannot be ignored even when the gate-source voltage is 0 V flows.

When the above-described CMOS inverter circuit is formed by such a deep submicron process, as shown in FIG. 16, even when the operation of the inverter circuit is stopped for a long time, the gate-source voltage becomes 0V.
, A small sub-threshold current _IL0 flows through the MOSFET in the off state, and this sub-threshold current _IL0
As a result, DC power of (VDD-VSS) × _IL0 is consumed. Such power consumption cannot be ignored.

An object of the present invention is to provide an MO that is turned off.
Suppresses the leakage current between the source and drain of the SFET,
It is to provide a MOS logic circuit with low power consumption.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0008]

The outline of a typical invention among the inventions disclosed in the present application is as follows.

That is, a first MOS logic circuit operating on a first power supply system, and an output amplitude operating on a second power supply system larger than the first power supply system and larger than that of the first MOS logic circuit. A second MOS logic circuit and the second M
A time constant circuit for delaying a circuit operation of the OS logic circuit, wherein the first MOS logic circuit and the second MOS logic circuit are connected in parallel with each other between a common input node and an output node; When a first signal having an amplitude corresponding to the first power supply system and having a frequency higher than a predetermined frequency determined by the time constant of the time constant circuit is input, a current is supplied to the first MOS logic circuit. When a second signal having an amplitude corresponding to the second power supply system and having a frequency lower than the predetermined frequency is input, a current flowing through the first MOS logic circuit is cut off to perform a logical operation. The configuration is such that the logic operation is performed by two MOS logic circuits.

[0010] Further, the first MOS logic circuit is connected to the positive electrode of the second power supply system or the second power supply system.
And a diode for preventing a current from flowing from the negative electrode of the power supply system to the negative electrode of the first power supply system.

More preferably, the threshold voltage of the MOSFET constituting the second MOS logic circuit is set to a first threshold voltage.
Are designed to be larger in absolute value than the threshold voltage of the MOSFET constituting the MOS logic circuit.

According to such means, while the first MOS logic circuit is operating at a high speed to some extent, the first MO logic circuit is operated.
While the S logic circuit operates the circuit with the output amplitude of the first power supply system, the operation of the second MOS logic circuit is delayed by the delay circuit and does not affect the circuit operation. On the other hand, the first MO
When the S logic circuit does not operate for a long time, the second M
The OS logic circuit operates to make the voltage level of the output node higher than the level of the first power supply system (higher on the positive side and lower on the negative side). Then, the voltage level input to the subsequent MOS logic circuit increases, and the MO level of the logic circuit increases.
Since the SFET is overdriven, the gate of the MOSFET through which the subthreshold current is flowing is connected to the MOSFET.
A voltage sufficient to turn off the FET is applied, and the subthreshold current is significantly reduced. In other words, when the first MOS logic circuit can provide almost normal circuit operation with the output amplitude of the first power supply system while operating at a high speed to some extent, the operation can be stopped for a relatively long time. The second MOS logic circuit operates to overdrive the subsequent MOSFET and reduce its leakage current.

The MO in the second MOS logic circuit
By increasing the absolute value of the threshold voltage of the SFET as described above, the leakage current of the MOSFET can be eliminated, and the second MOS logic circuit operates only at low speed operation. It does not affect the operation speed of the logic circuit.

When the present invention is applied to a CMOS inverter circuit as a basic logic circuit, for example, a P-channel MO connected in series and operated by a first power supply system is used.
A first inverter circuit (first logic circuit) composed of an SFET and an N-channel MOSFET, and a P-channel MOSFET and an N-channel MOSFET connected in series and operated by a second power supply system larger than the first power supply system
And an input node and an output node commonly connected to the first inverter circuit.
Logic circuit), the output node and P of the second inverter circuit.
A resistor connected in series between the output node and the N-channel MOSFET of the second inverter circuit; a resistor connected between the output node and the P-channel MOSFET of the first inverter circuit;
A diode provided between the N-channel MOSFET of the inverter circuit and preventing a current from flowing from the positive electrode of the first power supply system to the positive electrode of the second power supply system or from the negative electrode of the second power supply system to the negative electrode of the first power supply system; It comprises.

Here, the above-described resistor is combined with the gate capacitance of the MOSFET disposed downstream of the output node to form a time constant circuit for delaying the operation of the second inverter circuit. The diode can be, for example, a PN junction diode or a Schottky barrier diode, or can be formed by short-circuiting the gate and source of the MOSFET.

Further, among the semiconductor integrated circuits constituted by a plurality of logic circuits, the above-described MOS logic circuit is provided on a signal path having a sufficient delay time to constitute a semiconductor integrated circuit.

With this configuration, the MOS design of the present invention can be performed without revising the timing design of the semiconductor integrated circuit.
By applying a logic circuit to a conventional logic circuit, power consumption of a semiconductor integrated circuit can be reduced.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of the present invention will be described below with reference to FIGS.

[First Embodiment] FIG. 1 is a block diagram showing one embodiment of a MOS logic circuit to which the present invention is applied.

In this MOS logic circuit, two signal paths are provided in parallel, and register 11A, 11B, 13A, 13A for signal synchronization is provided on the input side and the output side of each signal path, respectively.
B, a combinational logic circuit 12 in which various logic gates are combined in one signal path, and a plurality of inverter circuits 1 as buffer circuits in the other signal path.
5a, 15b, 15c and 15d are provided.

Of these MOS logic circuits, the part to which the present invention is applied is a plurality of inverter circuits 15a to 15d.
Are signal paths connected in a line. On both sides of this signal path, power supply lines 20A and 20B for supplying power supply voltages VDD and VSS for normal circuit operation and a power supply voltage V for overdrive used when high-speed operation is to be guaranteed.
Sub-power supply lines 21A and 20 for supplying DDH and VSSL
B is provided. The power supply voltages VDDH and VSSL for overdrive are the power supply voltages VDD and V for normal operation.
It has a voltage width larger than SS, and is higher than the power supply voltage VDD for normal operation on the positive electrode side and lower than the power supply voltage VSS for normal operation on the negative electrode side. Each of the inverter circuits 15 to which the present invention is applied is supplied with both of these power supply voltages.

In order to detect a leak path in the circuit during a circuit test, a power supply line for supplying a larger power supply voltage than usual to each logic cell and reducing a leak current due to a subthreshold current of each logic cell may be provided. In that case, the wiring is connected to the power supply voltages VDDH, VSS
By using the auxiliary power supply lines 21A and 20B for supplying L, it is not necessary to newly increase the number of wirings.

FIG. 2 is a circuit diagram showing a first embodiment of the inverter circuit 15 to which the present invention is applied.

The inverter circuit 15 includes a P series connected in series between the power supply voltages VDD and VSS for normal operation.
Channel MOSFET P1 and N-channel MOSF
Inverter circuit 15A for normal operation composed of ETN1
And an overdrive sub-inverter circuit 15B including a P-channel MOSFET P2 and an N-channel MOSFET N2 connected in series between the large power supply voltages VDDH and VSSL. The inverter circuit 15A for normal operation and the sub-inverter circuit 15B for overdrive are connected in parallel so that the input node IN and the output node OUT are common, and the inverter circuit 15A for normal operation is further connected. 2
The diodes D1 and D2 for backflow prevention are connected in series between the two MOSFETs P1 and N1 and the output node OUT, respectively, while the two MOSs of the sub-inverter circuit 15B are connected.
Time constant setting resistors R1 and R2 are respectively connected in series between the FETs P2 and N2 and the output node OUT.

The MOSFETs P1 and N1 forming the inverter circuit 15A for normal operation are configured to operate at high speed at a low power supply voltage of, for example, 1.0 to 1.5 V by a fine LSI manufacturing technique called a deep submicron process. The threshold voltage is designed to have a small absolute value.

On the other hand, the MOSFETs P2 and N2 of the overdrive sub-inverter circuit 15B are designed such that the threshold voltage has a large absolute value.

The resistors R1 and R2 are connected to the sub inverter circuit 15
B is an element constituting a time constant circuit for delaying the operation of B,
The time constant of the sub inverter circuit 15B is determined in combination with the gate capacitance and the wiring capacitance of T. For example, when the time constant RC is set to several hundred μs to several ms in order to reduce power consumption without affecting the circuit operation, if the gate capacitance and the wiring capacitance of the MOSFET at the subsequent stage are set to 0.1 p to 1 pF, the resistance value becomes It is about 100 kΩ to 100 GΩ. A resistor having such a large resistance value can be configured by, for example, connecting the sources and drains of a plurality of MOSFETs to which an appropriate gate bias has been applied in series.

The diodes D1 and D2 are connected to the two N-channel MOSFETs N of the inverter circuits 15A and 15B.
1 and N2 are both turned on and the power supply voltages VDD and V
When conduction is established between DDHs or when two P-channel MOs
When the SFETs P1 and P2 are turned on, the power supply voltage VS
This is a backflow prevention diode that prevents a current from flowing between both power supply voltages when S and VSSL are conducted. Although this diode will be described in detail later, the MOSF
It can be composed of an ET or a Schottky barrier diode.

FIG. 3 shows that power supply voltage VD is applied to input node IN.
FIG. 3 shows an equivalent circuit diagram when a high-level signal of D is input.

When a high-level signal of the power supply voltage VDD is input to the input node IN of the inverter circuit 15, the N-channel MOSFETs N1 and N2 are turned on, and the P-channel MOSFETs P1 and P2 are turned off. The N-channel MOSFET N1 is turned on, but no current flows because a reverse bias is applied to the diode D2. Low threshold voltage P-channel MOSFET
A subthreshold current _IL0 that cannot be ignored even when the gate-source voltage Vgs is zero flows through P1. Therefore, an equivalent circuit as shown in FIG.
Changes from the power supply voltage VSS to the power supply voltage VSSL for overdrive in a time (several hundred μs to several ms) according to a time constant determined by the resistance value of the resistor R2 and the like.

[0031] Note that a large leakage current _{I L0} P-channel MOSFET P1, resistance due to the leakage current R
2 cannot be ignored, the output node OU
Since the output voltage of the T has a (VSSL + I L0 · _R2) becomes the output voltage swing is reduced, it is necessary to reduce the resistance of the resistor R2 so that the output voltage range is not too small. The condition of this resistance value is determined by the inverter circuit 15a shown in FIG.
To 15d, only the first one of the inverter circuits 15a to 15d is set.
In the case of 5d, a leak current does not occur in the P-channel MOSFET P2 having a low threshold voltage as described below, so that this is an unnecessary condition.

FIG. 4 shows that power supply voltage VD is applied to input node IN.
FIG. 3 shows an equivalent circuit diagram when a DH high-level signal is input.

In the state where the signal does not change for a long time, as described above, the output of the inverter circuit 15 changes to the overdrive power supply voltages VDDH and VSSL, so that the inverter circuits 15b to 15b in the second and subsequent stages in FIG. 15d
Is supplied with a high-level signal of the power supply voltage VDDH.

When a high-level signal of the power supply voltage VDDH for overdrive is input to the input nodes IN of the inverter circuits 15b to 15d, an N-channel MOS
The FETs N1 and N2 are turned on, and the P-channel MOSF
ET P1 and P2 are turned off. N-channel MO
The SFET N1 is turned on, but no current flows because the diode D2 is reverse-biased. Since a negative voltage is applied to the gate-source voltage Vgs to the P-channel MOSFET P1 having a low threshold voltage,
Source-to-source voltage Vgs drops significantly below threshold voltage Vth, and its subthreshold current becomes negligible. Therefore, an equivalent circuit as shown in FIG. 4 is obtained, and the output of the output node OUT takes the power supply voltage V for a time (several hundred μs to several ms) corresponding to a time constant determined by the resistance value of the resistor R2 and the like.
The transition from SS to the power supply voltage VSSL for overdrive is performed.

Since the output of the preceding inverter circuit 15 is input to the input nodes IN of the second to fourth inverter circuits 15b to 15d in FIG. 1, the signal does not change for a long time. The second to fourth inverter circuits 15b to 15d at substantially the same timing as when the output of the first inverter circuit 15a changes from the power supply voltage VSS to the power supply voltage VSSL for overdrive.
Also changes from the power supply voltage VSS to the power supply voltage VSSL.

FIG. 5 is a time chart of the voltage Vin input to the second and subsequent inverter circuits in FIG. 1 and the drain currents Ip1, In1 flowing through the MOSFETs P1, N1 of the inverter circuit 15A for normal operation. .

As shown in the period T2 in FIG. 5, when the input signal IN2 does not switch for a long time,
As described above, the output of the first-stage inverter circuit 15a in FIG. 1 is the power supply voltage VDDH or VS for overdrive.
The current shifts to SL, and the leakage currents of the second to fourth inverter circuits 15b to 15d change to negligible levels. In addition, power consumption due to leakage current can be reduced.

When the input signal IN2 of FIG. 1 switches at a high speed as shown in a period T1 in FIG. 5, when the input signal IN2 is composed of the resistors R1 and R2 and the load capacitance on the output node OUT side. Since the current does not flow through the overdrive sub-inverter circuit 15B due to the constant circuit and does not affect the inverter circuit output, the operation is substantially the same as that of the logic circuit including only the MOSFETs P1 and N1 of the normal operation inverter circuit 15A. Can be obtained.

Next, a description will be given of the application of an effective logic circuit using the inverter circuit according to the present invention.

In the logic circuit shown in FIG. 1, the registers 11A and 1A on the input side are used to adjust the timing of signals.
1B and a timing pulse φ input to the registers 13A and 13B on the output side.
2, a predetermined delay time t0 (for example, 10 ns) is set, and the timing is designed so that the delay time of each logic circuit provided between the registers is adjusted within the set delay time t0. .

When the logic circuit shown in FIG. 1 is constituted by a conventional deep submicron MOS logic circuit, the delay time of the combinational logic circuit 12 existing in a certain signal path is, for example, almost 9 ns in order to guarantee the logic operation. The delay time of the other signal path-like inverter circuits 15 is, for example, 5 ns.
A situation arises in which there is room. MO of the present invention
In the S logic circuit, the addition of the diodes D1 and D2 and the capacitive load of the input node IN reduce the sub inverter circuit 15B
The delay time is slightly increased due to an increase in the gate capacity of the device. Therefore, the MOS logic circuit of the present invention is preferably applied to a logic circuit of a signal path having a sufficient delay time, whereby the effects of the present invention can be enjoyed without changing the conventional timing design.

Therefore, in the embodiment of FIG. 1, the MOS logic circuit of the present invention is applied to the inverter circuits 15a to 15d of the signal path having a sufficient delay time. As a result, the delay time of this signal path extends to, for example, 8 ns, but can be corrected within a time shorter than the delay time of the combinational logic circuit 12, so that the timing of the inverter circuits 15a to 15d can be reduced without redesigning the timing of the entire logic circuit. The present invention can be applied only by changing each logic cell to the MOS logic circuit of the present invention.

[Second Embodiment] FIG. 6 is a circuit diagram showing a second embodiment of the inverter circuit to which the present invention is applied.

The inverter circuit of this embodiment is different from the inverter circuit 15 of the first embodiment in that a diode D for preventing backflow is provided.
1 and D2 are replaced by a diode-connected P-channel MOSFET P3 and an N-channel MOSFET N3 in which the source and the drain are short-circuited, respectively.

These MOSFET-connected MOSFETs
TP3 and N3 are inverter circuits 15A for normal operation.
MOSFET P1, N1 and output node OUT
Therefore, it is necessary to operate at a high speed because of being provided between the semiconductor device and the semiconductor device, and therefore is designed to have a low threshold value by a deep submicron process.

FIG. 7 shows that the power supply voltage V
FIG. 4 is an equivalent circuit diagram showing a state when a DD high-level signal is input.

When a high-level signal of power supply voltage VDD is input to input node IN, N-channel MOSF
ET N1 and N2 are turned on and the P-channel MOSFE
TP1 and P2 are turned off. However, P-channel MOSFET P1 of the low threshold voltage flows sub-threshold current _{I L0} gate-source voltage Vgs can not be ignored even when a zero. Similarly, the diode-connected N-channel MOSFET N3 also has a low threshold voltage, so that a non-negligible sub-threshold current _ILN3 flows. When the drain of the diode-connected N-channel MOSFET N3 is made lower than the power supply voltage VSS, a parasitic diode DX is generated between the well region and the drain of the N-channel MOSFET N3. Therefore, an equivalent circuit as shown in FIG. 7 is obtained.

In this embodiment, the difference voltage between the overdrive power supply voltage VSSL and the normal power supply voltage VSS is set to be smaller than the forward voltage VD of the diode. The reason is that the voltage of the output node OUT can be reduced only to a voltage lower than the power supply voltage VSS by the forward voltage VD of the diode due to the parasitic diode DX.
The power supply voltage VSSL for overdrive is changed to the voltage (VSS
If the voltage is lower than (−VD), a current flows through the parasitic diode DX to increase power consumption. The influence of the parasitic diode DX can be eliminated by setting the value of the power supply voltage VSSL as described above.

A diode-connected MOSFET N3
_{Causes a} leakage current _ILN3, but this MOSFET
The source-drain voltage of N3 is two power supply voltages VS
Since the difference voltage does not become larger than the difference voltage between S and VSSL and is a small value (for example, 0.5 V), the leak current _ILN3 is reduced by the MOSFET of the inverter circuit due to the dependency of the drain current on the source-drain voltage. compared to the leakage current I _L0 of P3 is negligible small.

In a sub-threshold region of a low threshold voltage MOSFET (a region where a sub-threshold current equal to or lower than the threshold voltage is generated), when the dependency of the drain current on the source-drain voltage is small as described above, Since the leakage current _ILN3 of the diode-connected MOSFET N3 cannot be ignored, the following countermeasures are required.

FIG. 8 is a circuit diagram showing a MOSFE constituting a diode.
FIG. 7A is a circuit diagram when a measure is taken to reduce the leakage current of TP3 and N3, and FIG. 8B is an equivalent circuit diagram when a power supply voltage VDD is input.

The diode-connected MOSFET N3
If the leakage current _ILN3 of
As shown in FIG.
Rather than shorting the gates of TP3 and N3 to their sources, a resistor R connected between MOSFETs P2-N2
1 and R2 are connected to each other, and gate biases displaced toward the overdrive power supply voltages VDDH and VSSL are added. According to such a configuration, for example, when a high-level signal of the power supply voltage VDD is input to the input node IN, as shown in FIG. 8B, the gate-source voltage Vgs of the MOSFET N3 serving as a diode Becomes smaller than 0 due to the voltage drop of the resistor R2, the MOSFET N3 is sufficiently turned off, and the leak current _ILN3 can be set to a negligible level.

It should be noted that the MOSFET P serving as a diode
3, N3 gate bias is too large
If it is displaced too much to H, VSSL side, MOSFET P
3, since the inversion speed of N3 becomes slow and adversely affects the operation speed of the inverter circuit 15A for normal operation, the value of the gate bias may be determined in consideration of the operation speed of the inverter circuit.

Accordingly, the inverter circuit of this embodiment is similar to the inverter circuit 15 of the first embodiment, and when a high-level signal of the power supply voltage VDD is input to the input node IN, the output node OUT Changes from the power supply voltage VSS to the power supply voltage VSSL for overdrive in a time corresponding to a time constant determined by the resistor R2 and the load capacitance of the output node OUT.

FIG. 9 is an equivalent circuit diagram showing a state when a high-level signal of the power supply voltage VDDH is input to the inverter circuit of the embodiment of FIG.

When a high-level signal of the power supply voltage VDDH for overdrive is input to the input node IN, a low threshold voltage P-channel MOSFET
Since the gate-source voltage Vgs of P1 is a negative voltage, the gate-source voltage Vgs is equal to the threshold voltage Vgs.
The sub-threshold current falls to a negligible level by dropping below th.

[Third Embodiment] FIG. 10 is a circuit diagram showing a third embodiment of the inverter circuit to which the present invention is applied.

In the inverter circuit of this embodiment, the substrate potentials of the diode-connected MOSFETs P3 and N3 in FIG. 6 are higher on the P-channel side and lower on the N-channel side. The drive power supply voltage VDDH and the substrate potential on the N-channel side are connected to the power supply voltage VSSL.

The MOSF diode-connected as described above
By changing the substrate potential of ET P3 and N3, the threshold voltage of these MOSFETs is low on the P channel side,
Since the voltage becomes higher on the N-channel side, it is possible to suppress a leak current when a reverse voltage is applied to the diode-connected MOSFETs P3 and N3.

The substrate potentials of the MOSFETs P3 and N3 are changed to the overdrive power supply voltages VDDH and VSSL.
7, the parasitic diode DX shown in FIG. 7 does not occur, so that the overdrive power supply voltages VDDH and VS
It is possible to set SL to a voltage value that is absolutely large, thereby increasing the amount of overdrive of the MOSFET.

[Fourth Embodiment] FIG. 11 is a circuit diagram showing a fourth embodiment of the inverter circuit to which the present invention is applied.

In the inverter circuit of this embodiment, the diodes D1 and D2 of the first embodiment are constituted by Schottky barrier diodes D3 and D4.

The Schottky barrier diode D3
D4 has a characteristic that the forward voltage is low and a characteristic that the capacitance is small and suitable for high-speed operation. By using such diodes D3 and D4, the MOSF
The output of the inverter circuit for normal operation composed of ET P1 and N1 is not affected, and the operation speed can be hardly reduced.

[Fifth Embodiment] FIG. 12 is a circuit diagram showing a fifth embodiment of the inverter circuit to which the present invention is applied.

The inverter circuit of this embodiment has an inverter circuit 15A for normal operation and a sub inverter circuit 15 for overdrive, similarly to the inverter circuit 15 of FIG.
B, and the sub-inverter circuit 15B is a MOSFET connected to the output node OUT side.
Is not overdriven, but the inverter circuit 15A for normal operation in the same cell is overdriven.

In order to perform such overdrive, in the inverter circuit of this embodiment, the input node n2 of the sub-inverter circuit 15B is connected to the common output node O.
The output node n2 of the sub inverter circuit 15B is connected to the common input node IN.

With this connection, the output of the sub-inverter circuit 15B is changed to the overdrive power supply voltages VDDH and VSSL when the signal does not change for a certain long time by the substantially same operation as that of the inverter circuit of FIG. By transition, the normal operation inverter circuit 15A provided in the same cell is sufficiently turned off, so that the leakage current flowing through the inverter circuit 15A and the power consumption due to the leakage current can be reduced.

In the inverter circuit of this embodiment, the diodes D1 and D2 do not prevent a reverse current in the same cell, but allow a current to flow backward between the inverter circuit and an inverter circuit connected to a subsequent stage. It is to prevent that.

In the inverter circuit of this embodiment, factors determining the time constant of the operation speed of sub-inverter circuit 15B are the resistance values of resistors R1 and R2 and input node I
It becomes the capacitance value on the N side. The capacitance of the input node IN is MOS
The sum of the gate capacitance of the FETs P1 and N1 and the capacitance of the circuit connected to the preceding stage is the sum of
Since ET P1 and N1 are deep sub-micron MOSs and have small gate capacitances, the capacitance of the circuit connected to the preceding stage greatly affects the determination of the time constant.

Therefore, when the inverter circuit of this embodiment is provided at the first stage of the inverter circuits 15a to 15d arranged in a plurality of stages in FIG. 1, the resistance values R1 and R2 are determined in consideration of the capacitance of the circuit at the preceding stage. Need to be done.

[Sixth Embodiment] FIG. 13 is a circuit diagram showing a sixth embodiment of the inverter circuit to which the present invention is applied.

In the inverter circuit of this embodiment, diodes D1 and D2 for preventing a reverse current between the inverter circuit of FIG.
It is arranged on the side so as to prevent a reverse current from flowing to the preceding circuit.

In the inverter circuit of this embodiment, since the diodes D1 and D2 are connected in parallel in both directions, the difference voltage between the power supply voltages VDD and VSS for normal operation and the power supply voltages VDDH and VSSL for overdrive is used. Is
It is necessary to set each of them below the forward voltage of the diode.

According to the inverter circuit 15, in the case of a logic circuit in which a plurality of inverter circuits are arranged in parallel at the preceding stage and the output of these inverter circuits is received by one inverter circuit, the diode D1 for backflow prevention is used. , D2
Is provided in only one inverter circuit in the subsequent stage, and is not required in a plurality of inverters in the preceding stage, so that the number of diodes D1 and D2 provided in the entire logic circuit can be reduced.

As described above, according to the inverter circuit 15 of the first to sixth embodiments, while operating at a relatively high speed to some extent, the MOSFET of the low threshold voltage formed by the deep submicron process is used. In the case where the inverter circuit 15A is operated at high speed as usual, but the operation is stopped for a long time without operation, the sub-inverter circuit 15B operates to connect the circuit connected to the subsequent stage. Or low threshold voltage MOS in the same cell
The gate voltage of the FET is greatly overdriven in absolute value, the leakage current between the source and the drain is reduced, and wasteful power consumption can be reduced.

The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say.

For example, although an inverter circuit has been described as an example of a MOS logic circuit, the present invention can be applied to various logic gates and logic circuits such as an AND gate, an OR gate, and a NOT gate. Further, the application part of the logic circuit to which the present invention is applied can be variously changed.

The MOS logic circuit for normal operation (first
And the overdrive MOS logic circuit (second MOS logic circuit) need not be assembled as a circuit having the same logic form. For example, a logic circuit in which a large number of inverter circuits are cascaded. In the circuit, the inverter circuits from the first stage to the third stage may be regarded as one logic circuit, and one overdrive inverter circuit may be provided in parallel with this logic circuit.

In the above description, an example in which the invention made by the present inventor is mainly applied to a logic circuit constituted by a deep submicron MOSFET, which is a field of application as the background, has been described. However, the present invention is not limited to this. However, the present invention can be widely used for a MOS logic circuit in which a MOSFET does not sufficiently turn off in a normal circuit operation and a leak current occurs.

[0080]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, according to the present invention, for example, while utilizing the characteristics of a low threshold voltage deep sub-micron MOS capable of operating at high speed with a low power supply voltage, while the MOS logic circuit does not operate for a long time, Has the effect that the leakage current between the source and the drain of the MOSFET in the off state can be suppressed and the power consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a MOS logic circuit including an inverter circuit suitable for applying the present invention.

FIG. 2 is a circuit diagram showing a first embodiment of the inverter circuit to which the present invention is applied.

FIG. 3 is an equivalent circuit diagram when a power supply voltage VDD is input to the inverter circuit of FIG. 2;

FIG. 4 is an equivalent circuit diagram when an overdrive power supply voltage VDDH is input to the inverter circuit of FIG. 2;

FIG. 5 is a time chart showing an operation when the inverter circuit of FIG. 2 is provided in the second and subsequent stages.

FIG. 6 is a circuit diagram showing a second embodiment of the inverter circuit to which the present invention is applied.

FIG. 7 is an equivalent circuit diagram when a power supply voltage VDD is input to the inverter circuit of FIG. 6;

FIGS. 8A and 8B show a case where measures are taken to reduce leakage current of a MOSFET constituting a diode in the inverter circuit shown in FIGS. 6A and 6B, FIG. 8A is a circuit diagram thereof, and FIG. FIG.

9 is an equivalent circuit diagram when the overdrive power supply voltage VDDH is input to the inverter circuit of FIG. 6;

FIG. 10 is a circuit diagram showing a third embodiment of the inverter circuit to which the present invention is applied.

FIG. 11 is a circuit diagram showing a fourth embodiment of the inverter circuit to which the present invention is applied.

FIG. 12 is a circuit diagram showing a fifth embodiment of the inverter circuit to which the present invention is applied.

FIG. 13 is a circuit diagram showing a sixth embodiment of the inverter circuit to which the present invention is applied.

FIG. 14 is a circuit diagram showing a conventional general CMOS inverter circuit.

FIG. 15 is a graph showing a relationship between a gate-source voltage and a drain current of a MOSFET.

FIG. 16 shows C formed by a deep submicron process.
6 is a time chart illustrating an operation of the MOS inverter circuit.

[Explanation of symbols]

15 Inverter Circuit 15A Inverter Circuit (First Logic Circuit) 15B Sub Inverter Circuit (Second Logic Circuit) R1, R2 Resistance D1, D2 Diode D3, D4 Schottky Barrier Diode I _L0 Subthreshold Current VDD, VSS Power Supply Voltage (first power supply system) VDDH, VSSL Power supply voltage (second power supply system)

Claims (5)

[Claims] 1. A first MOS logic circuit operating on a first power supply system, and operating on a second power supply system larger than the first power supply system and having an output amplitude larger than that of the first MOS logic circuit. A second MOS logic circuit; a time constant circuit for delaying the circuit operation of the second MOS logic circuit; and the first MOS logic circuit and the second MOS logic circuit share a common input node. A first signal having an amplitude corresponding to the first power supply system and having a frequency higher than a predetermined frequency determined by a time constant of the time constant circuit, The first MOS
A current flows through the logic circuit to perform a logic operation, and when a second signal having an amplitude corresponding to the second power supply system and lower than the predetermined frequency is input, a current flowing through the first MOS logic circuit Characterized by being cut off and performing a logical operation by a second MOS logic circuit. 2. The method according to claim 1, wherein the first MOS logic circuit includes the first MOS logic circuit.
A diode for preventing a current from flowing from the positive electrode of the power supply system to the positive electrode of the second power supply system or from the negative electrode of the second power supply system to the negative electrode of the first power supply system. 2. The MOS logic circuit according to 1. 3. The MOS logic circuit according to claim 1, wherein a threshold voltage of a MOSFET constituting the second MOS logic circuit is a MOSFET which constitutes the first MOS logic circuit.
A MOS logic circuit, which is designed to have an absolute value larger than a threshold voltage of T. 4. A P-channel MOSFET and an N-channel MOSFET connected in series and operated by a first power supply system.
A first inverter circuit composed of an SFET and a P-channel MOSFET and an N-channel MOSFET connected in series and operated by a second power supply system larger than the first power supply system, wherein the input node and the output node are the first inverter circuit; A second inverter circuit commonly connected to the second inverter circuit, an output node and a P-channel M of the second MOS logic circuit.
Between the OSFET and the output node and the second MOS
A resistance means connected in series between the N-channel MOSFET of the logic circuit, an output node and the P-channel M of the first inverter circuit;
OSFET and between the output node and the N-channel MOSFET of the first inverter circuit, respectively, from the positive electrode of the first power supply system to the positive electrode of the second power supply system or the negative A MOS logic circuit comprising: a diode for preventing a current from flowing to a negative electrode of a power supply system. 5. A semiconductor integrated circuit comprising a plurality of logic circuits, wherein the MOS logic circuit according to claim 1 is provided on a signal path having a sufficient delay time. Semiconductor integrated circuit.