JP2001237551A - Structure for mounting electronic unit on multilayered substrate - Google Patents
Structure for mounting electronic unit on multilayered substrateInfo
- Publication number
- JP2001237551A JP2001237551A JP2000052089A JP2000052089A JP2001237551A JP 2001237551 A JP2001237551 A JP 2001237551A JP 2000052089 A JP2000052089 A JP 2000052089A JP 2000052089 A JP2000052089 A JP 2000052089A JP 2001237551 A JP2001237551 A JP 2001237551A
- Authority
- JP
- Japan
- Prior art keywords
- electronic unit
- substrate
- conductive pattern
- multilayer
- unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、携帯電話機等に使
用して好適な電子ユニットの多層基板への取付構造に関
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure for mounting an electronic unit on a multilayer board suitable for use in a portable telephone or the like.
【０００２】[0002]
【従来の技術】従来の電子ユニットの多層基板への取付
構造を図９に基づいて説明すると、マザー基板からなる
多層基板２１は、複数枚の絶縁薄板が積層されて形成さ
れ、その表面２１ａには導電パターン２２が設けられる
と共に、その内部２１ｂには複数段積層された導電パタ
ーン２３が設けられている。また、前記導電パターン２
２は、複数のランド部２２ａを有すると共に、このラン
ド部２２ａと異なる位置の多層基板２１の表面２１ａに
は、複数のランド部３２ａを有し、各ランド部３２ａ
は、各段毎の導電パターン２３の一部と対向し、異なる
位置で表面２１ａに設けられている。そして、このラン
ド部３２ａは、必要に応じて表面２１ａの導電パターン
２２の端部に設けられたものも存在する。2. Description of the Related Art A conventional mounting structure of an electronic unit to a multi-layer substrate will be described with reference to FIG. 9. A multi-layer substrate 21 composed of a mother substrate is formed by laminating a plurality of insulating thin plates and has a surface 21a formed on the surface 21a. Is provided with a conductive pattern 22, and a plurality of stacked conductive patterns 23 are provided inside 21b. The conductive pattern 2
2 has a plurality of land portions 22a, and has a plurality of land portions 32a on a surface 21a of the multilayer substrate 21 at a position different from the land portions 22a.
Are provided on the surface 21a at different positions, facing a part of the conductive pattern 23 of each stage. The land portion 32a may be provided at the end of the conductive pattern 22 on the front surface 21a as necessary.
【０００３】また、この多層基板２１は、表面２１ａの
ランド部３２ａから内部２１ｂにわたって設けられた複
数個の孔２１ｃを有し、この孔２１ｃは、それぞれ積層
された導電パターン２３に達するように形成され、これ
等の孔２１ｃには、銀ペースト等の接続導体２４が充填
されて、内部２１ｂの導電パターン２３と表面２１ａの
ランド部３２ａが接続されている。The multilayer substrate 21 has a plurality of holes 21c provided from a land portion 32a of the surface 21a to the inside 21b, and the holes 21c are formed so as to reach the conductive patterns 23 stacked on each other. The holes 21c are filled with connection conductors 24 such as silver paste, so that the conductive patterns 23 in the inside 21b and the lands 32a on the surface 21a are connected.
【０００４】電子ユニット２５は、積層フイルター、電
圧制御発振器等からなり、複数枚の絶縁薄板を積層する
等して形成された絶縁基板２６を有している。そして、
この絶縁基板２６には、ここでは図示しないが、導電パ
ターンが設けられて、この導電パターンに各種の電気部
品を接続する等して、所望の電子ユニット回路が形成さ
れたものとなっている。The electronic unit 25 includes a laminated filter, a voltage controlled oscillator and the like, and has an insulating substrate 26 formed by laminating a plurality of insulating thin plates. And
Although not shown here, a conductive pattern is provided on the insulating substrate 26, and a desired electronic unit circuit is formed by connecting various electric components to the conductive pattern.
【０００５】また、矩形状をなす絶縁基板２６には、図
９に示すように、その端面２６ａに複数の凹部２６ｂが
設けられ、この各凹部２６ｂ面には、サイド電極２７が
形成されている。そして、このサイド電極２７は、絶縁
基板２６に設けられた導電パターンに接続され、このサ
イド電極２７を介して電子ユニット２５が他の回路に面
実装されるようになっている。As shown in FIG. 9, a plurality of recesses 26b are provided on an end surface 26a of a rectangular insulating substrate 26, and a side electrode 27 is formed on each of the recesses 26b. . The side electrode 27 is connected to a conductive pattern provided on the insulating substrate 26, and the electronic unit 25 is surface-mounted to another circuit via the side electrode 27.
【０００６】このように構成された電子ユニット２５
は、マザー基板である多層基板２１の表面２１ａ上に載
置され、各サイド電極２７を各ランド部２２ａ、３２ａ
に対応させる。そして、クリーム半田（図示せず）によ
りサイド電極２７とランド部２２ａ、３２ａとを半田付
けして、接続すると共に、電子ユニット２５を多層基板
２１に取り付ける。これによって、電子ユニット２５が
ランド部２２ａ、３２を介して多層基板２１の所望の回
路に接続されるものである。The electronic unit 25 constructed as described above
Are mounted on the surface 21a of the multilayer substrate 21 as a mother substrate, and each side electrode 27 is connected to each of the land portions 22a and 32a.
To correspond to. Then, the side electrodes 27 and the lands 22a and 32a are soldered and connected by cream solder (not shown), and the electronic unit 25 is attached to the multilayer board 21. Thus, the electronic unit 25 is connected to a desired circuit of the multilayer board 21 via the lands 22a and 32.
【０００７】[0007]
【発明が解決しようとする課題】従来の電子ユニットの
多層基板への取付構造は、複数段積層された導電パター
ン２３の接続部であるランド部３２ａが多層基板２１の
表面２１ａに形成され、電子ユニット２５が表面２１ａ
上に載置されて、サイド電極２７がランド部３２ａに半
田付けされるため、電子ユニット２５が表面２１ａから
大きく出っ張り、高さが大きくなって、大型になるとい
う問題がある。In a conventional structure for mounting an electronic unit on a multilayer substrate, a land portion 32a, which is a connection portion of a plurality of stacked conductive patterns 23, is formed on a front surface 21a of the multilayer substrate 21. Unit 25 is surface 21a
Since the electronic unit 25 is mounted on the upper surface and soldered to the land portion 32a, the electronic unit 25 protrudes greatly from the surface 21a, so that the height of the electronic unit 25 becomes large, which causes a problem that the electronic unit 25 becomes large.
【０００８】そこで、本発明は薄型で、小型に適した電
子ユニットの多層基板への取付構造を提供することを目
的とする。Accordingly, an object of the present invention is to provide a structure for mounting a thin and compact electronic unit on a multilayer substrate.
【０００９】[0009]
【課題を解決するための手段】上記課題を解決するため
の第１の解決手段として、複数のサイド電極を端面に設
けた絶縁基板を有する電子ユニットと、少なくとも内部
に導電パターンを有する多層基板とを備え、前記多層基
板は、前記電子ユニットを収納する凹状の収納部と、こ
の収納部を形成する側壁に設けられ、前記導電パターン
の端部が露出する複数の凹部と、前記導電パターンの前
記端部に導通した状態で、前記複数の凹部面に形成され
た複数のサイド導体とを有し、前記収納部内に前記電子
ユニットを収納すると共に、前記サイド電極と前記サイ
ド導体とを対向させ、前記サイド電極と前記サイド導体
とを半田付けして導通した構成とした。As a first means for solving the above problems, an electronic unit having an insulating substrate provided with a plurality of side electrodes on an end face, and a multilayer substrate having at least a conductive pattern therein are provided. The multilayer board is provided with a concave storage portion for storing the electronic unit, a plurality of concave portions provided on a side wall forming the storage portion, and exposing end portions of the conductive pattern, In a state where it is electrically connected to an end, the plurality of side conductors are formed on the plurality of concave surfaces, and the electronic unit is housed in the housing, and the side electrode and the side conductor are opposed to each other. The side electrode and the side conductor were soldered and electrically connected.
【００１０】また、第２の解決手段として、前記電子ユ
ニットの前記絶縁基板の前記端面には、凹部が設けら
れ、この凹部面に前記サイド電極を設けた構成とした。
また、第３の解決手段として、前記収納部は、有底の凹
状で形成された構成とした。As a second solution, a concave portion is provided on the end surface of the insulating substrate of the electronic unit, and the side electrode is provided on the concave surface.
As a third solution, the storage section is formed in a concave shape with a bottom.
【００１１】また、第４の解決手段として、前記導電パ
ターンは、前記多層基板の表面と、前記多層基板の内部
で複数段積層されて設けられると共に、前記多層基板に
設けられた前記凹部が前記多層基板の表面から前記内部
に位置する最下部の前記導電パターンにわたって設けら
れた構成とした。また、第５の解決手段として、前記多
層基板に設けられた前記複数の凹部の一部は、前記側壁
の中間部に設けられた構成とした。According to a fourth aspect of the present invention, the conductive pattern is provided on the surface of the multi-layer substrate and in a plurality of layers inside the multi-layer substrate. The multi-layer substrate is provided so as to extend from the surface to the lowermost conductive pattern located inside the multilayer substrate. As a fifth solution, a part of the plurality of recesses provided in the multilayer substrate is provided in an intermediate portion of the side wall.
【００１２】[0012]
【発明の実施の形態】本発明の電子ユニットの多層基板
への取付構造の図面を説明すると、図１は電子ユニット
の多層基板への取付構造に係る第１実施例を示す分解斜
視図、図２は本発明の電子ユニットの多層基板への取付
構造に係る第１実施例を示す要部の平面図、図３は図２
の３−３線における断面図である。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an exploded perspective view showing a first embodiment of a mounting structure of an electronic unit to a multilayer board according to the present invention. 2 is a plan view of a main part showing a first embodiment according to the mounting structure of the electronic unit of the present invention on a multilayer board, and FIG.
FIG. 3 is a sectional view taken along line 3-3 of FIG.
【００１３】また、図４は本発明の電子ユニットの多層
基板への取付構造に係る第２実施例を示す要部の平面
図、図５は図４の５−５線における断面図、図６は本発
明の電子ユニットの多層基板への取付構造の第３実施例
に係り、多層基板の要部の斜視図、図７は本発明の電子
ユニットの多層基板への取付構造に係る第３実施例を示
す要部の平面図、図８は図７の８−８線における断面図
である。FIG. 4 is a plan view of an essential part showing a second embodiment of the mounting structure of the electronic unit of the present invention on a multilayer board, FIG. 5 is a sectional view taken along line 5-5 in FIG. FIG. 7 relates to a third embodiment of the mounting structure of the electronic unit to the multilayer board of the present invention, and is a perspective view of a main part of the multilayer board. FIG. 7 is a third embodiment of the mounting structure of the electronic unit to the multilayer board of the present invention. 8 is a cross-sectional view taken along line 8-8 in FIG.
【００１４】次に、本発明の電子ユニットの多層基板へ
の取付構造に係る第１実施例の構成を図１〜図３に基づ
いて説明すると、マザー基板からなる多層基板１は、複
数枚の絶縁薄板が積層されて形成され、その表面１ａに
は導電パターン２が設けられると共に、その内部１ｂに
は複数段（実施例では３段）積層された導電パターン３
が設けられている。また、多層基板１には、座繰り加工
により形成された矩形状の凹状からなる有底の収納部１
ｃと、収納部１ｃに設けられた底部１ｄと、収納部１ｃ
を形成する側壁１ｅに設けられた複数の凹部１ｆとを有
する。Next, the structure of the first embodiment according to the mounting structure of the electronic unit of the present invention on a multilayer substrate will be described with reference to FIGS. 1 to 3. The multilayer substrate 1 composed of a mother substrate is composed of a plurality of substrates. A conductive pattern 2 is provided on the surface 1a of the insulating pattern, and a plurality of (three in this embodiment) conductive patterns 3 are laminated on the inside 1b.
Is provided. Further, the multilayer substrate 1 has a bottomed storage unit 1 having a rectangular concave shape formed by counterboring.
c, a bottom part 1d provided in the storage part 1c, and a storage part 1c
And a plurality of recesses 1f provided on the side wall 1e forming the first groove.
【００１５】そして、表面１ａに形成された前記導電パ
ターン２の端部には、複数のランド部２ａを有すると共
に、このランド部２ａは、凹部１ｆの上端に位置して形
成され、凹部１ｆ面の全面に形成されたサイド導体４ａ
に導通している。また、その他の凹部１ｆには、内部１
ｂに位置する各段のそれぞれ導電パターン３の端部が露
出し、この凹部１ｆ面の全面に形成されたサイド導体４
ｂとそれぞれの導電パターン３の端部が導通した状態と
なっている。なお、このサイド導体４ｂの上端は、必要
に応じて表面１ａに形成された導電パターン２に接続し
ても良い。At the end of the conductive pattern 2 formed on the surface 1a, a plurality of lands 2a are formed, and the lands 2a are formed at the upper ends of the recesses 1f, and are formed on the surfaces of the recesses 1f. Side conductor 4a formed on the entire surface of
It is conducting. In addition, the other concave portion 1f has an internal 1
b, the end portions of the conductive patterns 3 of the respective steps are exposed, and the side conductors 4 formed on the entire surface of the concave portion 1f are exposed.
b and the end of each conductive pattern 3 are in a conductive state. The upper end of the side conductor 4b may be connected to the conductive pattern 2 formed on the front surface 1a as needed.
【００１６】また、この多層基板１に設けられた複数の
凹部１ｆは、何れも表面１ａから内部１ｂに位置する最
下部（表面から最も遠い位置）の導電パターン３にわた
り、且つ、底部１ｄに至って設けられ、これらの凹部１
ｆの全面には、サイド導体４ａ、４ｂが形成されたもの
となっている。Each of the plurality of recesses 1f provided in the multilayer substrate 1 extends from the surface 1a to the lowermost (farthest from the surface) conductive pattern 3 located in the inside 1b and reaches the bottom 1d. Provided these recesses 1
Side conductors 4a and 4b are formed on the entire surface of f.
【００１７】電子ユニット５は、積層フイルター、電圧
制御発振器等からなり、複数枚の絶縁薄板を積層する等
して形成された絶縁基板６を有している。そして、この
絶縁基板６には、ここでは図示しないが、導電パターン
が設けられて、この導電パターンに各種の電気部品を接
続する等して、所望の電子ユニット回路が形成されたも
のとなっている。The electronic unit 5 includes a laminated filter, a voltage controlled oscillator, and the like, and has an insulating substrate 6 formed by laminating a plurality of insulating thin plates. Although not shown here, a conductive pattern is provided on the insulating substrate 6, and a desired electronic unit circuit is formed by connecting various electric components to the conductive pattern. I have.
【００１８】また、矩形状をなす絶縁基板６には、図１
に示すように、その端面６ａに複数の凹部６ｂが設けら
れ、この各凹部６ｂ面には、サイド電極７が形成されて
いる。そして、このサイド電極７は、絶縁基板６に設け
られた導電パターンに接続され、このサイド電極７を介
して電子ユニット５が他の回路に面実装されるようにな
っている。The insulating substrate 6 having a rectangular shape has a structure shown in FIG.
As shown in FIG. 7, a plurality of recesses 6b are provided on the end face 6a, and a side electrode 7 is formed on each of the recesses 6b. The side electrode 7 is connected to a conductive pattern provided on the insulating substrate 6, and the electronic unit 5 is surface-mounted to another circuit via the side electrode 7.
【００１９】このように構成された電子ユニット５の多
層基板１への取付は、先ず、マザー基板である多層基板
１の収納部１ｃ内に電子ユニット５を挿入する。この
時、多層基板１に設けられた凹部１ｆと絶縁基板６に設
けられた凹部６ｂとは互いに対向した状態、即ち、サイ
ド導体４ａ、４ｂとサイド電極７とが互いに対向した状
態となっている。In mounting the electronic unit 5 configured as described above on the multilayer substrate 1, first, the electronic unit 5 is inserted into the storage portion 1c of the multilayer substrate 1 which is a mother substrate. At this time, the concave portion 1f provided on the multilayer substrate 1 and the concave portion 6b provided on the insulating substrate 6 face each other, that is, the side conductors 4a and 4b and the side electrode 7 face each other. .
【００２０】次に、この凹部１ｆ、６ｂとの間にクリー
ム半田を充填して、このクリーム半田を加熱して溶か
し、互いに対向するサイド導体４ａ、４ｂとサイド電極
７とを半田８付けする。すると、電子ユニット５は、サ
イド電極７を介して多層基板１の導電パターン２，３に
接続されると共に、電子ユニット５が多層基板１に取り
付けられる。これによって、電子ユニット５が多層基板
１の所望の回路に接続されるものである。Next, cream solder is filled between the recesses 1f and 6b, the cream solder is heated and melted, and the side conductors 4a and 4b and the side electrode 7 facing each other are soldered to each other. Then, the electronic unit 5 is connected to the conductive patterns 2 and 3 of the multilayer substrate 1 via the side electrodes 7, and the electronic unit 5 is attached to the multilayer substrate 1. Thus, the electronic unit 5 is connected to a desired circuit of the multilayer board 1.
【００２１】また、図４、図５は本発明の第２実施例を
示し、この第２実施例は、前記第１実施例の絶縁基板６
に設けた凹部６ｂを無くし、平面状の端面６ａにサイド
電極７を設けたもので、その他の構成は前記実施例と同
様であるので、同一部品に同一番号を付し、ここではそ
の説明を省略する。そして、この第２実施例では、多層
基板１の凹部１ｆと絶縁基板６の端面６ａとの間にクリ
ーム半田を充填するものである。FIGS. 4 and 5 show a second embodiment of the present invention. This second embodiment is based on the insulating substrate 6 of the first embodiment.
In which the side electrode 7 is provided on the planar end face 6a, and the other configuration is the same as that of the above-described embodiment. Omitted. In the second embodiment, the space between the concave portion 1f of the multilayer substrate 1 and the end surface 6a of the insulating substrate 6 is filled with cream solder.
【００２２】また、図６〜図８は本発明の第３実施例を
示し、この第３実施例は、前記第１実施例の多層基板１
に設けた凹部１ｆの全部が表面１ａから底部１ｄにわた
って設けられたものであるが、その複数の凹部１ｆの一
部が側壁１ｅの中間部に設けられたもので、その他の構
成は前記実施例と同様であるので、同一部品に同一番号
を付し、ここではその説明を省略する。そして、この第
３実施例では、側壁１ｅの中間部に凹部１ｆが位置する
箇所は、側壁１ｅと絶縁基板６の凹部６ｂとの間にクリ
ーム半田を充填して、凹部１ｆ内にクリーム半田を位置
させるものである。FIGS. 6 to 8 show a third embodiment of the present invention, which is a multi-layer substrate 1 of the first embodiment.
Is provided from the surface 1a to the bottom 1d, but a part of the plurality of recesses 1f is provided in an intermediate portion of the side wall 1e. Therefore, the same parts are denoted by the same reference numerals, and description thereof is omitted here. In the third embodiment, the portion where the concave portion 1f is located in the middle of the side wall 1e is filled with cream solder between the side wall 1e and the concave portion 6b of the insulating substrate 6, and the cream solder is filled in the concave portion 1f. It is to be located.
【００２３】なお、上記実施例では、多層基板１の収納
部１ｃが底部１ｄを有する有底のもので説明したが、収
納部１ｃは、多層基板１の上下に貫通されたものでも良
い。In the above embodiment, the storage portion 1c of the multilayer substrate 1 has been described as having a bottom having a bottom portion 1d, but the storage portion 1c may be penetrated up and down of the multilayer substrate 1.
【００２４】[0024]
【発明の効果】本発明の電子ユニットの多層基板への取
付構造において、多層基板１は、電子ユニット５を収納
する凹状の収納部１ｃと、この収納部１ｃを形成する側
壁１ｅに設けられ、内部１ｂに設けられた導電パターン
３の端部が露出する複数の凹部１ｆと、導電パターン３
の端部に導通した状態で、複数の凹部１ｆ面に形成され
た複数のサイド導体４ｂとを有し、収納部１ｃ内に電子
ユニット５を収納すると共に、電子ユニット５のサイド
電極７とサイド導体４ｂとを対向させ、サイド電極７と
サイド導体４ｂとを半田８付けして導通したため、電子
ユニット５が収納部１ｃに収納されて、高さ方向に薄型
となり、小型の電子ユニットの多層基板への取付構造を
提供できる。In the structure for mounting an electronic unit on a multilayer substrate according to the present invention, the multilayer substrate 1 is provided on a concave storage portion 1c for storing the electronic unit 5 and a side wall 1e forming the storage portion 1c. A plurality of recesses if in which the ends of the conductive pattern 3 provided in the interior 1b are exposed;
A plurality of side conductors 4b formed on the surface of the plurality of recesses 1f in a state where the electronic unit 5 is accommodated in the accommodating portion 1c, and the side electrode 7 of the electronic unit 5 and the side electrode 7 Since the conductor 4b is opposed to the side electrode 7 and the side conductor 4b are soldered to each other for conduction, the electronic unit 5 is housed in the housing part 1c, becomes thin in the height direction, and is a multilayer board of a small electronic unit. It can provide a mounting structure to the vehicle.
【００２５】また、電子ユニット５の絶縁基板６の端面
６ａには、凹部６ｂが設けられ、この凹部６ｂ面にサイ
ド電極７を設けたため、この凹部６ｂが多層基板１の凹
部１ｆと対向して、クリーム半田の充填が容易となり、
作業性の良好な電子ユニットの多層基板への取付構造を
提供できる。Further, a concave portion 6b is provided on the end surface 6a of the insulating substrate 6 of the electronic unit 5, and the side electrode 7 is provided on the surface of the concave portion 6b, so that the concave portion 6b faces the concave portion 1f of the multilayer substrate 1. , Cream solder filling becomes easy,
It is possible to provide a structure for mounting the electronic unit to the multilayer board with good workability.
【００２６】また、収納部１ｃは、有底の凹状で形成さ
れたため、収納部１ｃ内に収納された電子ユニット５が
安定し、組立性の良好な電子ユニットの多層基板への取
付構造を提供できる。Further, since the accommodating portion 1c is formed in a concave shape with a bottom, the electronic unit 5 accommodated in the accommodating portion 1c is stabilized, and a mounting structure of the electronic unit with good assemblability to the multilayer board is provided. it can.
【００２７】また、導電パターン２，３は、多層基板１
の表面１ａと、多層基板１の内部１ｂで複数段積層され
て設けられると共に、多層基板１に設けられた凹部１ｆ
が多層基板１の表面１ａから内部１ｂに位置する最下部
の導電パターン３にわたって設けられたため、凹部１ｆ
の形成が共通の深さとなり、作業性の良好な電子ユニッ
トの多層基板への取付構造を提供できる。The conductive patterns 2 and 3 correspond to the multilayer substrate 1.
And a concave portion 1f provided in the multilayer substrate 1 while being provided in a plurality of layers on the surface 1a of the multilayer substrate 1 and inside 1b of the multilayer substrate 1.
Is provided from the surface 1a of the multilayer substrate 1 to the lowermost conductive pattern 3 located in the inside 1b, so that the concave portion 1f
Is formed at a common depth, and it is possible to provide a structure for mounting the electronic unit to the multilayer board with good workability.
【００２８】また、多層基板１に設けられた複数の凹部
１ｆの一部は、側壁１ｅの中間部に設けられたため、特
に、凹部１ｆの上部に導電パターン２が位置するものに
おいて、この導電パターン２と接続しない状態で、導電
パターン３をサイド電極７に接続するもに使用して、好
適である。Since a part of the plurality of recesses 1f provided in the multilayer substrate 1 is provided in an intermediate portion of the side wall 1e, especially in the case where the conductive pattern 2 is located above the recess 1f, this conductive pattern It is suitable for use in connecting the conductive pattern 3 to the side electrode 7 in a state where the conductive pattern 3 is not connected.
【図１】本発明の電子ユニットの多層基板への取付構造
に係る第１実施例を示す分解斜視図。FIG. 1 is an exploded perspective view showing a first embodiment of a mounting structure of an electronic unit to a multilayer board according to the present invention.
【図２】本発明の電子ユニットの多層基板への取付構造
に係る第１実施例を示す要部の平面図。FIG. 2 is a plan view of a main part showing a first embodiment according to the mounting structure of the electronic unit on the multilayer board of the present invention.
【図３】図２の３−３線における断面図。FIG. 3 is a sectional view taken along line 3-3 in FIG. 2;
【図４】本発明の電子ユニットの多層基板への取付構造
に係る第２実施例を示す要部の平面図。FIG. 4 is a plan view of a main part showing a second embodiment according to the mounting structure of the electronic unit on the multilayer board of the present invention.
【図５】図４の５−５線における断面図。FIG. 5 is a sectional view taken along line 5-5 in FIG. 4;
【図６】本発明の電子ユニットの多層基板への取付構造
の第３実施例に係り、多層基板の要部の斜視図。FIG. 6 is a perspective view of a main part of the multilayer board according to a third embodiment of the mounting structure of the electronic unit to the multilayer board according to the present invention.
【図７】本発明の電子ユニットの多層基板への取付構造
に係る第３実施例を示す要部の平面図。FIG. 7 is a plan view of a main part showing a third embodiment according to the mounting structure of the electronic unit on the multilayer board of the present invention.
【図８】図７の８−８線における断面図。FIG. 8 is a sectional view taken along line 8-8 in FIG. 7;
【図９】従来の電子ユニットの多層基板への取付構造を
示す分解斜視図。FIG. 9 is an exploded perspective view showing a conventional structure for mounting an electronic unit on a multilayer board.
１ 多層基板 １ａ 表面 １ｂ 内部 １ｃ 収納部 １ｄ 底部 １ｅ 側壁 １ｆ 凹部 ２ 導電パターン ３ 導電パターン ４ａ サイド導体 ４ｂ サイド導体 ５ 電子ユニット ６ 絶縁基板 ６ａ 端面 ６ｂ 凹部 ７ サイド電極 ８ 半田 DESCRIPTION OF SYMBOLS 1 Multilayer board 1a Surface 1b Inside 1c Storage part 1d Bottom 1e Side wall 1f Concave part 2 Conductive pattern 3 Conductive pattern 4a Side conductor 4b Side conductor 5 Electronic unit 6 Insulating board 6a End face 6b Concave part 7 Side electrode 8 Solder
───────────────────────────────────────────────────── フロントページの続き Ｆターム(参考） 5E336 AA04 AA08 BB03 BC25 BC30 BC36 CC32 CC42 CC60 EE03 GG30 5E344 AA05 BB02 CC11 CC25 DD02 EE12 EE21 5E346 AA02 AA12 AA15 AA42 AA43 BB01 BB13 BB16 CC40 FF19 FF27 FF42 FF45 GG40 HH22 HH24 HH31 ──────────────────────────────────────────────────続 き Continuing on the front page F term (reference) 5E336 AA04 AA08 BB03 BC25 BC30 BC36 CC32 CC42 CC60 EE03 GG30 5E344 AA05 BB02 CC11 CC25 DD02 EE12 EE21 5E346 AA02 AA12 AA15 AA42 AA43 BB01 BB13 BB16 H40 FF24
Claims (5)
板を有する電子ユニットと、少なくとも内部に導電パタ
ーンを有する多層基板とを備え、前記多層基板は、前記
電子ユニットを収納する凹状の収納部と、この収納部を
形成する側壁に設けられ、前記導電パターンの端部が露
出する複数の凹部と、前記導電パターンの前記端部に導
通した状態で、前記複数の凹部面に形成された複数のサ
イド導体とを有し、前記収納部内に前記電子ユニットを
収納すると共に、前記サイド電極と前記サイド導体とを
対向させ、前記サイド電極と前記サイド導体とを半田付
けして導通したことを特徴とする電子ユニットの多層基
板への取付構造。1. An electronic unit having an insulating substrate provided with a plurality of side electrodes on an end face, and a multilayer substrate having at least a conductive pattern therein, wherein the multilayer substrate has a concave storage portion for storing the electronic unit. And a plurality of recesses provided on a side wall forming the storage portion and exposing an end of the conductive pattern, and a plurality of recesses formed on the plurality of recessed surfaces in a state of being electrically connected to the end of the conductive pattern. Wherein the electronic unit is housed in the housing portion, the side electrode and the side conductor are opposed to each other, and the side electrode and the side conductor are soldered to conduct. The mounting structure of the electronic unit to the multilayer board.
端面には、凹部が設けられ、この凹部面に前記サイド電
極を設けたことを特徴とする請求項１記載の電子ユニッ
トの多層基板への取付構造。2. The multi-layer substrate of an electronic unit according to claim 1, wherein a concave portion is provided on the end surface of the insulating substrate of the electronic unit, and the side electrode is provided on the concave surface. Mounting structure.
ことを特徴とする請求項１、又は２記載の電子ユニット
の多層基板への取付構造。3. The mounting structure according to claim 1, wherein the housing is formed in a concave shape with a bottom.
面と、前記多層基板の内部で複数段積層されて設けられ
ると共に、前記多層基板に設けられた前記凹部が前記多
層基板の表面から前記内部に位置する最下部の前記導電
パターンにわたって設けられたことを特徴とする請求項
１から３の何れかに記載の電子ユニットの多層基板への
取付構造。4. The multi-layer substrate according to claim 1, wherein the conductive pattern is provided on the surface of the multi-layer substrate and a plurality of layers are provided inside the multi-layer substrate. 4. The structure for mounting an electronic unit on a multi-layer substrate according to claim 1, wherein the electronic unit is provided over the lowermost conductive pattern located at the lowermost position.
部の一部は、前記側壁の中間部に設けられたことを特徴
とする請求項１から４の何れかに記載の電子ユニットの
多層基板への取付構造。5. The multilayer of the electronic unit according to claim 1, wherein a part of the plurality of recesses provided in the multilayer substrate is provided in an intermediate portion of the side wall. Mounting structure to the board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000052089A JP2001237551A (en) | 2000-02-23 | 2000-02-23 | Structure for mounting electronic unit on multilayered substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000052089A JP2001237551A (en) | 2000-02-23 | 2000-02-23 | Structure for mounting electronic unit on multilayered substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2001237551A true JP2001237551A (en) | 2001-08-31 |
Family
ID=18573657
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000052089A Ceased JP2001237551A (en) | 2000-02-23 | 2000-02-23 | Structure for mounting electronic unit on multilayered substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2001237551A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004095851A (en) * | 2002-08-30 | 2004-03-25 | Ngk Spark Plug Co Ltd | Wiring board |
| KR100650614B1 (en) | 2004-09-01 | 2006-11-27 | 가부시키가이샤 덴소 | Multi-layer board manufacturing method |
| JP2011216790A (en) * | 2010-04-01 | 2011-10-27 | Ngk Spark Plug Co Ltd | Capacitor incorporated in wiring board, and wiring board |
| WO2013096983A1 (en) * | 2011-12-28 | 2013-07-04 | At & S Austria Technologie & Systemtechnik Aktiengesellschaft | Method for producing a printed circuit board consisting of at least two printed circuit board regions, and printed circuit board |
| JP2015023071A (en) * | 2013-07-17 | 2015-02-02 | Ｎｅｃプラットフォームズ株式会社 | Laminated circuit board |
| EP2874476A1 (en) * | 2013-11-14 | 2015-05-20 | Siemens Aktiengesellschaft | Printed circuit base board, module circuit board and circuit board assembly with a base board and a module circuit board |
| JP2016174088A (en) * | 2015-03-17 | 2016-09-29 | Ｎｅｃプラットフォームズ株式会社 | End face electrode substrate and method of manufacturing composite substrate |
| WO2022181684A1 (en) * | 2021-02-26 | 2022-09-01 | 京セラ株式会社 | Electronic element mounting board, electronic component, and electronic apparatus |
-
2000
- 2000-02-23 JP JP2000052089A patent/JP2001237551A/en not_active Ceased
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004095851A (en) * | 2002-08-30 | 2004-03-25 | Ngk Spark Plug Co Ltd | Wiring board |
| KR100650614B1 (en) | 2004-09-01 | 2006-11-27 | 가부시키가이샤 덴소 | Multi-layer board manufacturing method |
| JP2011216790A (en) * | 2010-04-01 | 2011-10-27 | Ngk Spark Plug Co Ltd | Capacitor incorporated in wiring board, and wiring board |
| US9480172B2 (en) | 2011-12-28 | 2016-10-25 | At & S Austria Technologie & Systemtechnik Aktiengesellschaft | Method for producing a printed circuit board consisting of at least two printed circuit board regions, and printed circuit board |
| CN104206037A (en) * | 2011-12-28 | 2014-12-10 | At&S奥地利科技及系统技术股份公司 | Method for producing a printed circuit board consisting of at least two printed circuit board regions, and printed circuit board |
| WO2013096983A1 (en) * | 2011-12-28 | 2013-07-04 | At & S Austria Technologie & Systemtechnik Aktiengesellschaft | Method for producing a printed circuit board consisting of at least two printed circuit board regions, and printed circuit board |
| AT518252B1 (en) * | 2011-12-28 | 2017-09-15 | At & S Austria Tech & Systemtechnik Ag | Method for producing a printed circuit board consisting of at least two printed circuit board areas and printed circuit board |
| AT518252A5 (en) * | 2011-12-28 | 2017-09-15 | At & S Austria Tech & Systemtechnik Ag | Method for producing a printed circuit board consisting of at least two printed circuit board areas and printed circuit board |
| JP2015023071A (en) * | 2013-07-17 | 2015-02-02 | Ｎｅｃプラットフォームズ株式会社 | Laminated circuit board |
| EP2874476A1 (en) * | 2013-11-14 | 2015-05-20 | Siemens Aktiengesellschaft | Printed circuit base board, module circuit board and circuit board assembly with a base board and a module circuit board |
| DE102013223209A1 (en) * | 2013-11-14 | 2015-05-21 | Siemens Aktiengesellschaft | Base board, module board and board assembly with a base board and a module board |
| JP2016174088A (en) * | 2015-03-17 | 2016-09-29 | Ｎｅｃプラットフォームズ株式会社 | End face electrode substrate and method of manufacturing composite substrate |
| WO2022181684A1 (en) * | 2021-02-26 | 2022-09-01 | 京セラ株式会社 | Electronic element mounting board, electronic component, and electronic apparatus |
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