JP2001237278A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP2001237278A
JP2001237278A JP2000048851A JP2000048851A JP2001237278A JP 2001237278 A JP2001237278 A JP 2001237278A JP 2000048851 A JP2000048851 A JP 2000048851A JP 2000048851 A JP2000048851 A JP 2000048851A JP 2001237278 A JP2001237278 A JP 2001237278A
Authority
JP
Japan
Prior art keywords
circuit board
semiconductor chip
electrode
conductive particles
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000048851A
Other languages
Japanese (ja)
Inventor
Takashi Nakamura
崇 中村
泰行 ▲高▼野
Yasuyuki Takano
Masatoshi Takeda
雅俊 竹田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2000048851A priority Critical patent/JP2001237278A/en
Publication of JP2001237278A publication Critical patent/JP2001237278A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device being connected with a circuit board using an anisotropic conductive member in which the number of particles being captured can be increased without sacrifice of insulation performance. SOLUTION: The semiconductor device comprises a semiconductor chip in which circuit elements are fabricated, a plurality of protruding electrodes 6 are arranged while forming gap parts and a plurality of particle guide protrusions 11 are arranged such that gap parts are located between the gap parts of the protruding electrodes 6 on the inside thereof, a circuit board 8 having a wiring layer with a plurality of circuit board electrodes 9 corresponding to the protruding electrodes 6 being formed on the surface, an insulating resin and conductive particles 2 dispersed into the insulating resin. The semiconductor device further comprises an anisotropic conductive film for bonding the semiconductor chip and the circuit board 8 by thermocompressing them thereby capturing the conductive particles 2 between the protruding electrodes 6 and the circuit board electrodes 9.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は半導体装置の実装構
造に関して、導電性粒子と絶縁性樹脂からなる接着剤を
用いて、半導体チップと回路基板とをフェースダウンで
接続するフリップチップ実装構造に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mounting structure of a semiconductor device, and more particularly, to a flip-chip mounting structure for connecting a semiconductor chip and a circuit board face down using an adhesive made of conductive particles and an insulating resin. It is.

【0002】[0002]

【従来の技術】半導体チップと回路基板とをフェースダ
ウンで直接接続するフリップチップ実装は、半導体チッ
プを樹脂で保護成形した従来のパッケージを実装したも
のに比べ、実装面積を大幅に縮小できるという利点を有
しており、今後とも期待されている技術である。
2. Description of the Related Art Flip-chip mounting, in which a semiconductor chip and a circuit board are directly connected face-down, has the advantage that the mounting area can be significantly reduced as compared with a conventional package in which a semiconductor chip is protected and molded with resin. It is a technology that is expected in the future.

【0003】ここで、導電性粒子と絶縁性樹脂とからな
る異方導電性フィルム(Anisotropic Co
nductive Film)(以下、「ACF」とい
う。)を用いた従来のフリップチップ実装技術につい
て、図面を参照しながら説明する。
[0003] Here, an anisotropic conductive film (Anisotropic Co., Ltd.) comprising conductive particles and an insulating resin is used.
A conventional flip-chip mounting technology using a negative film (hereinafter, referred to as “ACF”) will be described with reference to the drawings.

【0004】図18は従来のフリップチップ実装による
半導体装置を示す斜視図、図19は図18のB−B’線
に沿った断面図、図20は図18の半導体装置の製造工
程を連続して示す説明図、図21は図20の製造工程を
経て得られた半導体装置を示す斜視図、図22は図21
のB部を製造時における導電性粒子の流れとともに拡大
して示す説明図、図23は図21のB部を導電性粒子と
ともに拡大して示す説明図である。
FIG. 18 is a perspective view showing a conventional flip-chip mounted semiconductor device, FIG. 19 is a cross-sectional view taken along the line BB 'of FIG. 18, and FIG. FIG. 21 is a perspective view showing a semiconductor device obtained through the manufacturing process of FIG. 20, and FIG.
23 is an explanatory diagram showing the portion B of FIG. 21 enlarged together with the flow of the conductive particles at the time of manufacturing, and FIG. 23 is an explanatory diagram showing the portion B of FIG. 21 together with the conductive particles.

【0005】図示する半導体装置は、ワイヤボンディン
グ技術を応用したボールボンディング法によって形成さ
れた突起状電極(以下、「バンプ」という。)6と回路
基板8とをACF1を用いて接合したものからなる。
The semiconductor device shown in the figure is formed by joining a protruding electrode (hereinafter referred to as a “bump”) 6 formed by a ball bonding method using a wire bonding technique and a circuit board 8 using an ACF 1. .

【0006】図19に示すように、所定の回路素子が作
り込まれた半導体チップ4の主面には、半導体チップ4
の表面保護膜であるパシベーション膜7および金属薄膜
電極5が形成されており、金属薄膜電極5上にバンプ6
が形成されている。
As shown in FIG. 19, a semiconductor chip 4 on which a predetermined circuit element is formed is provided on a main surface of the semiconductor chip 4.
A passivation film 7 as a surface protection film and a metal thin-film electrode 5 are formed.
Are formed.

【0007】また、このような半導体チップ4が実装さ
れる回路基板8は配線層8aが多層にわたって形成され
た多層回路基板であり、その表面には回路基板電極(以
下、「パッド」という。)9がバンプ6に対応して形成
されている。
The circuit board 8 on which such a semiconductor chip 4 is mounted is a multilayer circuit board in which wiring layers 8a are formed in multiple layers, and a circuit board electrode (hereinafter, referred to as a "pad") is provided on the surface thereof. 9 are formed corresponding to the bumps 6.

【0008】半導体チップ4と回路基板8とを接合する
ACF1は、絶縁性樹脂(バインダ)3と、絶縁性樹脂
3中に分散された導電性粒子2とからなる。
The ACF 1 for joining the semiconductor chip 4 and the circuit board 8 includes an insulating resin (binder) 3 and conductive particles 2 dispersed in the insulating resin 3.

【0009】ここで、金属薄膜電極5はたとえばアルミ
ニウム薄膜等から構成され、その厚みは数μmから1μ
m以下と非常に薄い。このため、金属薄膜電極5上に突
起状のバンプ6を形成し、このバンプ6を介して回路基
板8のパッド9と接合して導通が確保されている。
Here, the metal thin-film electrode 5 is made of, for example, an aluminum thin film and has a thickness of several μm to 1 μm.
m and very thin. For this reason, the bumps 6 are formed on the metal thin-film electrodes 5 and are connected to the pads 9 of the circuit board 8 via the bumps 6 to ensure conduction.

【0010】次に、以上の構成を有する半導体装置の製
造工程を図20を参照しながら説明する。
Next, a manufacturing process of the semiconductor device having the above configuration will be described with reference to FIG.

【0011】先ず、図20(a)に示すように、バンプ
6の形成された半導体チップ4と回路基板8との間にA
CF1を配し、半導体チップ4のバンプ6と回路基板8
上のパッド9とを位置合わせする。
First, as shown in FIG. 20A, a gap between a semiconductor chip 4 on which bumps 6 are formed and a circuit board 8 is set.
CF1 is provided, and the bumps 6 of the semiconductor chip 4 and the circuit board 8 are provided.
The upper pad 9 is aligned.

【0012】次に、図20(b)に示すように、ACF
1中の絶縁性樹脂3が溶融して硬化する所定の温度まで
ACF1を加熱すると同時に、バンプ6とパッド9との
接合部位に導電性粒子2を捕獲させるために所定の圧力
をかける。なお、導電性粒子2はACF1中に所定の密
度で存在する。
Next, as shown in FIG.
At the same time, the ACF 1 is heated to a predetermined temperature at which the insulating resin 3 in the resin 1 is melted and hardened, and at the same time, a predetermined pressure is applied to cause the conductive particles 2 to be captured at the joint between the bump 6 and the pad 9. Note that the conductive particles 2 exist in the ACF 1 at a predetermined density.

【0013】これにより、ACF1中の絶縁性樹脂3が
溶融しながら半導体チップ4と回路基板8の間を満たさ
れ、この絶縁性樹脂3の硬化反応が終了することで半導
体チップ4と回路基板8とが接合される。そして、図2
0(c)に示すように、導電性粒子2を介して半導体チ
ップ4と回路基板8との導通が得られる。
As a result, the space between the semiconductor chip 4 and the circuit board 8 is filled while the insulating resin 3 in the ACF 1 is melted, and the curing reaction of the insulating resin 3 is completed. Are joined. And FIG.
As shown in FIG. 1C, conduction between the semiconductor chip 4 and the circuit board 8 is obtained via the conductive particles 2.

【0014】ここで、実装後(図21)にバンプ6とパ
ッド9との間に捕獲された導電性粒子2は、電気的接続
に寄与しているため望大特性を有している。ACF1に
存在する導電性粒子2の密度が高いほど接合部位に捕獲
される粒子個数は増加するが、バンプ6の近辺に存在し
ながら接合部位に捕獲されなかった導電性粒子2は、半
導体チップ4の外縁方向へ押し出されるときにバンプ6
とバンプ6との隙間を流動し(図22)、この部位の粒
子分布密度が局所的に増大する(図23)。
Here, the conductive particles 2 captured between the bumps 6 and the pads 9 after the mounting (FIG. 21) contribute to the electrical connection, and thus have the desired characteristics. As the density of the conductive particles 2 present in the ACF 1 increases, the number of particles captured at the bonding site increases, but the conductive particles 2 existing near the bump 6 but not captured at the bonding site are removed from the semiconductor chip 4. When pushed out toward the outer edge of the bump 6
Then, the particles flow in the gap between the bumps 6 (FIG. 22), and the particle distribution density at this portion locally increases (FIG. 23).

【0015】そして、バンプ6とバンプ6との隙間に流
動した導電性粒子2は絶縁性の低下を引き起こす要因と
なる。
The conductive particles 2 flowing into the gap between the bumps 6 cause a decrease in insulation.

【0016】[0016]

【発明が解決しようとする課題】このように、従来にお
いてACFなどの異方導電性部材を用いたフリップチッ
プ実装技術では、捕獲粒子数の増加(すなわち粒子分布
密度の望大特性)と絶縁性の低下(粒子分布密度の望小
特性)という二律背反の問題を有していた。
As described above, in the conventional flip-chip mounting technology using an anisotropic conductive member such as ACF, the number of trapped particles (that is, the maximum characteristic of the particle distribution density) and the insulating property are reduced. (The desired characteristic of the particle distribution density) is a trade-off.

【0017】そこで、本発明は、捕獲粒子数を増加させ
るとともに絶縁性低下を引き起こすことなく異方導電性
部材を用いて半導体チップと回路基板とが電気的に接続
された半導体装置を提供することを目的とする。
It is an object of the present invention to provide a semiconductor device in which a semiconductor chip and a circuit board are electrically connected to each other by using an anisotropic conductive member without increasing the number of trapped particles and causing a decrease in insulation. With the goal.

【0018】[0018]

【課題を解決するための手段】この課題を解決するため
に、本発明の半導体装置は、回路素子が作り込まれ、間
隙部を形成して複数の突起状電極が配列されるとともに
突起状電極の内側において突起状電極の間隙部間に間隙
部が位置するようにして複数の粒子誘導突起が配列され
た半導体チップと、配線層が形成されて表面に突起状電
極に対応した複数の回路基板電極が形成された回路基板
と、絶縁性樹脂およびこの絶縁性樹脂中に分散された導
電性粒子からなり、半導体チップと回路基板とを熱圧着
することにより突起状電極と回路基板電極との間に導電
性粒子を捕捉させて半導体チップと回路基板とを接合す
る異方導電性部材とを有する構成としたものである。
In order to solve this problem, a semiconductor device according to the present invention has a circuit element formed therein, a gap portion is formed, a plurality of projecting electrodes are arranged, and a projecting electrode is formed. A semiconductor chip in which a plurality of particle guiding protrusions are arranged such that a gap is located between the gaps of the protruding electrodes on the inside of the semiconductor chip, and a plurality of circuit boards on which a wiring layer is formed and corresponding to the protruding electrodes on the surface A circuit board on which electrodes are formed, and an insulating resin and conductive particles dispersed in the insulating resin. The semiconductor chip and the circuit board are thermocompression-bonded between the protruding electrodes and the circuit board electrodes. And an anisotropic conductive member that joins the semiconductor chip and the circuit board by capturing the conductive particles.

【0019】これにより、粒子誘導突起の近傍に存在す
る導電性粒子は粒子誘導突起の間隙部を通って外方に移
動して行き、突起状電極上における粒子密度が高くな
り、その間隙部における粒子密度は低くなって突起状電
極と回路基板電極とに捕捉される粒子数が増加するとと
もに突起状電極相互間に位置する粒子数は少なくなの
で、捕獲粒子数を増加させるとともに絶縁性低下を引き
起こすことなく異方導電性部材を用いて半導体チップと
回路基板とを電気的に接続することが可能になる。
As a result, the conductive particles existing in the vicinity of the particle-guiding projection move outward through the gap between the particle-guiding projections, so that the particle density on the protruding electrode increases, and As the particle density decreases and the number of particles trapped between the protruding electrodes and the circuit board electrode increases, and the number of particles located between the protruding electrodes decreases, the number of trapped particles increases and the insulating property decreases. The semiconductor chip and the circuit board can be electrically connected without using the anisotropic conductive member.

【0020】[0020]

【発明の実施の形態】本発明の請求項1に記載の発明
は、回路素子が作り込まれ、間隙部を形成して複数の突
起状電極が配列されるとともに突起状電極の内側におい
て突起状電極の間隙部間に間隙部が位置するようにして
複数の粒子誘導突起が配列された半導体チップと、配線
層が形成されて表面に突起状電極に対応した複数の回路
基板電極が形成された回路基板と、絶縁性樹脂およびこ
の絶縁性樹脂中に分散された導電性粒子からなり、半導
体チップと回路基板とを熱圧着することにより突起状電
極と回路基板電極との間に導電性粒子を捕捉させて半導
体チップと回路基板とを接合する異方導電性部材とを有
する半導体装置であり、粒子誘導突起の近傍に存在する
導電性粒子は粒子誘導突起の間隙部を通って外方に移動
して行き、突起状電極上における粒子密度が高くなり、
その間隙部における粒子密度は低くなって突起状電極と
回路基板電極とに捕捉される粒子数が増加するとともに
突起状電極相互間に位置する粒子数は少なくなので、捕
獲粒子数を増加させるとともに絶縁性低下を引き起こす
ことなく異方導電性部材を用いて半導体チップと回路基
板とを電気的に接続することが可能になるという作用を
有する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS According to the first aspect of the present invention, a circuit element is formed, a gap is formed, a plurality of projecting electrodes are arranged, and a projecting electrode is formed inside the projecting electrode. A semiconductor chip in which a plurality of particle guiding projections are arranged such that gaps are located between gaps between electrodes, and a wiring layer is formed, and a plurality of circuit board electrodes corresponding to the projecting electrodes are formed on the surface. A circuit board, made of an insulating resin and conductive particles dispersed in the insulating resin, and conductively pressed between the semiconductor chip and the circuit board to form conductive particles between the protruding electrode and the circuit board electrode; A semiconductor device having an anisotropic conductive member that captures and joins a semiconductor chip and a circuit board, and conductive particles existing in the vicinity of the particle guiding protrusion move outward through a gap between the particle guiding protrusion. Go to the projecting electricity Particle density is high on,
As the particle density in the gap decreases, the number of particles trapped by the protruding electrodes and the circuit board electrode increases, and the number of particles located between the protruding electrodes decreases. This has the effect that it becomes possible to electrically connect the semiconductor chip and the circuit board using an anisotropic conductive member without lowering the performance.

【0021】本発明の請求項2に記載の発明は、請求項
1記載の発明において、粒子誘導突起は柱状に形成され
ている半導体装置であり、粒子誘導突起がチップ電極の
面積とほぼ等しい広い頭頂面積を得ることができるの
で、粒子誘導突起によって突起状電極上に誘導される導
電性粒子の粒子数がより多くなって突起状電極と回路基
板電極とに捕捉される粒子数が一層増加し、より安定的
な電気的接続を得ることができるという作用を有する。
According to a second aspect of the present invention, in the first aspect, the particle guiding projection is a semiconductor device having a columnar shape, and the particle guiding projection is substantially equal to the area of the chip electrode. Since the crown area can be obtained, the number of conductive particles guided on the protruding electrodes by the particle guiding protrusions increases, and the number of particles captured by the protruding electrodes and the circuit board electrode further increases. Has the effect that a more stable electrical connection can be obtained.

【0022】本発明の請求項3に記載の発明は、請求項
2記載の発明において、粒子誘導突起は、2つの側面で
構成されるエッジ部の1つが内側に向けて配置された三
角柱型である半導体装置であり、導電性粒子が粒子誘導
突起によりスムーズに外側に誘導されるので、粒子誘導
突起によって突起状電極上に誘導される導電性粒子の粒
子数がより一層多くなり、より安定的な電気的接続を得
ることができるという作用を有する。
According to a third aspect of the present invention, in the second aspect, the particle guiding projection has a triangular prism shape in which one of the edge portions composed of two side faces is arranged inward. In a certain semiconductor device, since the conductive particles are smoothly guided outward by the particle guiding protrusions, the number of conductive particles guided on the protruding electrodes by the particle guiding protrusions is further increased, and more stable. It has an effect that an excellent electrical connection can be obtained.

【0023】本発明の請求項4に記載の発明は、回路素
子が作り込まれ、間隙部を形成して複数の突起状電極が
配列された半導体チップと、配線層が形成され、表面に
突起状電極に対応した複数の回路基板電極が形成される
とともに回路基板電極から内側に延びる粒子誘導溝が形
成された回路基板と、絶縁性樹脂およびこの絶縁性樹脂
中に分散された導電性粒子からなり、半導体チップと回
路基板とを熱圧着することにより突起状電極と回路基板
電極との間に導電性粒子を捕捉させて半導体チップと回
路基板とを接合する異方導電性部材とを有する半導体装
置であり、導電性粒子は粒子誘導溝を通ってより高い密
度になりながら外方向に流動して突起状電極と回路基板
電極との間に到達するので、突起状電極と回路基板電極
とに捕捉される粒子数が増加して、捕獲粒子数を増加さ
せるとともに絶縁性低下を引き起こすことなく異方導電
性部材を用いて半導体チップと回路基板とを電気的に接
続することが可能になるという作用を有する。
According to a fourth aspect of the present invention, there is provided a semiconductor chip in which a circuit element is formed, a gap is formed and a plurality of protruding electrodes are arranged, a wiring layer is formed, and a protrusion is formed on the surface. A circuit board in which a plurality of circuit board electrodes corresponding to the shape electrode are formed and a particle guiding groove extending inward from the circuit board electrode is formed, and the insulating resin and the conductive particles dispersed in the insulating resin are used. A semiconductor having an anisotropic conductive member that joins the semiconductor chip and the circuit board by capturing conductive particles between the protruding electrode and the circuit board electrode by thermocompression bonding the semiconductor chip and the circuit board. The conductive particles flow outward while having a higher density through the particle guiding grooves and reach between the protruding electrodes and the circuit board electrodes. Grain caught The number is increased, an effect that it is possible to electrically connect the semiconductor chip and the circuit board using an anisotropic conductive member without causing insulation decreases with increasing the number of capture particles.

【0024】本発明の請求項5に記載の発明は、回路素
子が作り込まれ、間隙部を形成して複数の突起状電極が
配列された半導体チップと、配線層が形成され、表面に
突起状電極に対応した複数の回路基板電極が形成される
とともに回路基板電極と基板電極との間から内側に延び
る粒子誘導部材が形成された回路基板と、絶縁性樹脂お
よびこの絶縁性樹脂中に分散された導電性粒子からな
り、半導体チップと回路基板とを熱圧着することにより
突起状電極と回路基板電極との間に導電性粒子を捕捉さ
せて半導体チップと回路基板とを接合する異方導電性部
材とを有する半導体装置であり、導電性粒子は粒子誘導
部材と粒子誘導部材との間を通ってより高い密度になり
ながら外方向に流動して突起状電極と回路基板電極との
間に到達するので、突起状電極と回路基板電極とに捕捉
される粒子数が増加して、捕獲粒子数を増加させるとと
もに絶縁性低下を引き起こすことなく異方導電性部材を
用いて半導体チップと回路基板とを電気的に接続するこ
とが可能になるという作用を有する。
According to a fifth aspect of the present invention, there is provided a semiconductor chip in which a circuit element is formed, a gap is formed and a plurality of protruding electrodes are arranged, a wiring layer is formed, and a protrusion is formed on the surface. A circuit board on which a plurality of circuit board electrodes corresponding to the shape electrodes are formed and a particle guiding member extending inward from between the circuit board electrodes and the board electrode, and an insulating resin and dispersed in the insulating resin. Anisotropic conductive material that is made of conductive particles that are bonded by thermocompression bonding between a semiconductor chip and a circuit board, thereby capturing the conductive particles between the protruding electrodes and the circuit board electrodes and joining the semiconductor chip and the circuit board. A semiconductor device having a conductive member, wherein the conductive particles flow outward while increasing in density between the particle guide member and the particle guide member and flow between the protruding electrode and the circuit board electrode. To reach, The number of particles trapped by the raised electrode and the circuit board electrode increases, and the number of trapped particles increases, and the semiconductor chip and the circuit board are electrically connected using an anisotropic conductive member without causing a decrease in insulation. Has the effect that it becomes possible to connect to

【0025】以下、本発明の実施の形態について、図1
から図17を用いて説明する。なお、これらの図面にお
いて同一の部材には同一の符号を付しており、また、重
複した説明は省略されている。
Hereinafter, an embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIG. In these drawings, the same members are denoted by the same reference numerals, and duplicate description is omitted.

【0026】(実施の形態1)図1は本発明の実施の形
態1における半導体装置を示す斜視図、図2は図1のB
部を製造時における導電性粒子の流れとともに拡大して
示す説明図、図3は図1のB部を導電性粒子とともに拡
大して示す説明図である。
(Embodiment 1) FIG. 1 is a perspective view showing a semiconductor device according to Embodiment 1 of the present invention, and FIG.
FIG. 3 is an explanatory diagram showing an enlarged view of the portion B together with the flow of the conductive particles during manufacturing, and FIG. 3 is an explanatory diagram showing the portion B of FIG. 1 together with the conductive particles.

【0027】なお、以下に説明する実施の形態を含め
て、半導体装置の外観構成および断面構造は従来の技術
において説明した図18および図19に示すものと略同
一であるため、ここでは図示および説明を省略する。
Since the external structure and cross-sectional structure of the semiconductor device, including the embodiment described below, are substantially the same as those shown in FIGS. 18 and 19 described in the prior art, FIG. Description is omitted.

【0028】図2に示すように、本実施の形態の半導体
装置では、半導体チップ4の主面外周部において、所定
幅の間隙部を形成してバンプ6が一列に配列されてい
る。そして、このバンプ6の内側には、導通を目的とし
ないバンプ6、つまりダミーバンプ(粒子誘導突起)1
1が、バンプ6の間隙部間にその間隙部が位置するよう
にして一列に配列されている。
As shown in FIG. 2, in the semiconductor device of the present embodiment, a bump having a predetermined width is formed in the outer periphery of the main surface of the semiconductor chip 4 and the bumps 6 are arranged in a line. Inside the bump 6, a bump 6 not intended for conduction, that is, a dummy bump (particle guiding projection) 1
1 are arranged in a row so that the gaps are located between the gaps of the bumps 6.

【0029】次に、このような構成を有する半導体装置
の製造工程について図2および図3を用いて説明する。
Next, a manufacturing process of a semiconductor device having such a configuration will be described with reference to FIGS.

【0030】荷重と熱とを印加する実装時の初期段階に
おいてACF(異方導電性部材)1は軟化し流動して、
半導体チップ4と回路基板8のとの隙間に充填されなが
ら外方向へと押し出される。
ACF (anisotropically conductive member) 1 softens and flows in an initial stage of mounting in which a load and heat are applied,
It is extruded outward while being filled in the gap between the semiconductor chip 4 and the circuit board 8.

【0031】すると、図2に示すように、ACF1中の
ダミーバンプ11近傍に存在する導電性粒子2は、ダミ
ーバンプ11の間隙部を通ってより高い密度になりなが
ら外方向に流動してバンプ6とパッド9との間に到達す
る。
Then, as shown in FIG. 2, the conductive particles 2 existing in the vicinity of the dummy bumps 11 in the ACF 1 flow outward while increasing in density through the gaps of the dummy bumps 11 to form bumps 6. It reaches between the pad 9.

【0032】これにより、図3に示すように、バンプ6
上における粒子密度が高くなり、間隙部における粒子密
度は低くなる分布の濃淡が発生する。したがって、バン
プ6とパッド9とに捕捉される粒子数が増加するととも
にバンプ6相互間に位置する粒子数は少なくなるので、
捕獲粒子数を増加させるとともに絶縁性低下を引き起こ
すことなくACF1を用いて半導体チップ4と回路基板
8とを電気的に接続することが可能になる。
As a result, as shown in FIG.
The density of the distribution increases, with the particle density at the top increasing and the particle density at the gap decreasing. Therefore, the number of particles captured by the bump 6 and the pad 9 increases and the number of particles located between the bumps 6 decreases, so that
The semiconductor chip 4 and the circuit board 8 can be electrically connected by using the ACF 1 without increasing the number of trapped particles and causing a decrease in insulation.

【0033】(実施の形態2)図4は本発明の実施の形
態2における半導体装置を構成する半導体チップを示す
断面図、図5は半導体チップに形成されたダミーバンプ
を示す斜視図、図6は図5(c)に示すダミーバンプを
用いた場合での製造時における導電性粒子の流れを示す
説明図、図7は図6に示す箇所の製造後の状態を示す説
明図である。
(Second Embodiment) FIG. 4 is a sectional view showing a semiconductor chip constituting a semiconductor device according to a second embodiment of the present invention, FIG. 5 is a perspective view showing dummy bumps formed on the semiconductor chip, and FIG. FIG. 5C is an explanatory view showing the flow of the conductive particles at the time of manufacturing when the dummy bump shown in FIG. 5C is used, and FIG. 7 is an explanatory view showing the state shown in FIG. 6 after manufacturing.

【0034】半導体チップ4上に形成されたダミーバン
プ11は、前述した実施の形態1に示すように、導通を
目的としたバンプ6と同形状にすることができるが、図
4および図5に示すようにバンプ6の形成をメッキで行
う場合には異なった形状にすることもできる。
The dummy bumps 11 formed on the semiconductor chip 4 can be formed in the same shape as the bumps 6 for the purpose of conduction as shown in the above-described first embodiment, but are shown in FIGS. As described above, when the bumps 6 are formed by plating, the bumps 6 may have different shapes.

【0035】すなわち、一般的にバンプ6の横断面形状
は円形であり、縦断面形状は図4に示すように2段突起
形状である。一方、ダミーバンプ11の縦断面形状は矩
形にすることができる。但し、ダミーバンプ11を形成
するフォトマスクの開口部の形状を変更することでその
形状は種々変更することができ、たとえば、図5(a)
に示すような四角柱型、図5(b)に示すような円柱
型、図5(c)に示すような三角柱型にすることができ
る。
That is, generally, the cross-sectional shape of the bump 6 is circular, and the vertical cross-sectional shape is a two-step projection shape as shown in FIG. On the other hand, the vertical cross-sectional shape of the dummy bump 11 can be rectangular. However, the shape of the opening of the photomask for forming the dummy bump 11 can be variously changed by changing the shape, for example, as shown in FIG.
5 (b), a columnar shape as shown in FIG. 5 (b), and a triangular prism type as shown in FIG. 5 (c).

【0036】そして、このような柱状にすれば、バンプ
6と比較してダミーバンプ11はチップ電極5の面積と
ほぼ等しい広いバンプ頭頂面積を得ることができる。こ
れにより、ダミーバンプ11によってバンプ6上に誘導
される導電性粒子2の粒子数がより多くなるので、バン
プ6とパッド9とに捕捉される粒子数が一層増加し、よ
り安定的な電気的接続を得ることができる。
With such a column shape, the dummy bump 11 can obtain a wide bump top area substantially equal to the area of the chip electrode 5 as compared with the bump 6. As a result, the number of conductive particles 2 induced on the bumps 6 by the dummy bumps 11 increases, so that the number of particles trapped between the bumps 6 and the pads 9 further increases, resulting in more stable electrical connection. Can be obtained.

【0037】なお、ダミーバンプ11と金属薄膜電極5
との間には、金属被膜(バリアメタル)13が形成され
る。
The dummy bump 11 and the metal thin film electrode 5
Between them, a metal film (barrier metal) 13 is formed.

【0038】ここで、図5(c)に示す三角柱型のダミ
ーバンプ11を用いた半導体装置の要部を図6に示す。
Here, FIG. 6 shows a main part of a semiconductor device using the triangular prism type dummy bumps 11 shown in FIG. 5C.

【0039】図示するように、ダミーバンプ11を三角
柱型にした場合、2つの側面で構成されるエッジ部の1
つを内側に向けて配置することが望ましい。
As shown in the figure, when the dummy bump 11 is formed in a triangular prism shape, one of the edge portions constituted by two side surfaces is formed.
It is desirable to place the two inwards.

【0040】このようにすれば、導電性粒子2がダミー
バンプ11によりスムーズに外側に誘導されるので、図
7に示すように、ダミーバンプ11によってバンプ6上
に誘導される導電性粒子2の粒子数がより一層多くな
り、より安定的な電気的接続を得ることができる。
In this way, the conductive particles 2 are smoothly guided outward by the dummy bumps 11, and as shown in FIG. 7, the number of the conductive particles 2 guided on the bumps 6 by the dummy bumps 11 is increased. , And a more stable electrical connection can be obtained.

【0041】(実施の形態3)図8は本発明者が検討対
象とした半導体装置を示す斜視図、図9(a)は図8の
A−A’線に沿った断面図、図9(b)は図8のB−
B’線に沿った断面図、図10は図8の半導体装置にお
けるレジスト塗布状態の一例を示す説明図、図11は図
8の半導体装置におけるレジスト塗布状態の他の一例を
示す説明図、図12は本発明の実施の形態3における半
導体装置の要部を示す説明図、図13は図12のA−
A’線に沿った断面図、図14は本発明の実施の形態3
の変形例である半導体装置の要部を示す説明図、図15
は図14のA−A’線に沿った断面図である。
(Embodiment 3) FIG. 8 is a perspective view showing a semiconductor device studied by the present inventor, FIG. 9A is a sectional view taken along the line AA 'of FIG. 8, and FIG. b) is B- of FIG.
FIG. 10 is a cross-sectional view taken along line B ′, FIG. 10 is an explanatory view showing an example of a resist application state in the semiconductor device of FIG. 8, and FIG. 11 is an explanatory view showing another example of a resist application state in the semiconductor device of FIG. 12 is an explanatory view showing a main part of the semiconductor device according to the third embodiment of the present invention, and FIG.
FIG. 14 is a sectional view taken along the line A ′, and FIG.
FIG. 15 is an explanatory view showing a main part of a semiconductor device as a modification of FIG.
FIG. 15 is a sectional view taken along line AA ′ of FIG.

【0042】図8に示すように、回路基板8の表面に
は、半導体チップ4に形成されたバンプと接続するパッ
ド9の部分を除き、レジスト(表面保護層)10が塗布
される場合がある。
As shown in FIG. 8, a resist (surface protective layer) 10 may be applied to the surface of the circuit board 8 except for a portion of a pad 9 connected to a bump formed on the semiconductor chip 4. .

【0043】この場合、図9に示すように、レジスト1
0のない部位ではパッド9が露出しており、レジスト1
0のある部位ではパッド9がレジスト10で覆われてい
る。また、レジスト10の塗布形態は、図10に示すよ
うに、パッド9の周囲にはレジスト10を塗布しないも
の、図11に示すように、パッド9以外の箇所は全てレ
ジスト10で覆い尽くすものなどがある。
In this case, as shown in FIG.
The pad 9 is exposed in the area where there is no 0, and the resist 1
The pad 9 is covered with the resist 10 at a portion where there is zero. Further, as shown in FIG. 10, the resist 10 is not coated around the pad 9 as shown in FIG. 10, and the resist 10 covers all parts except the pad 9 as shown in FIG. There is.

【0044】そして、これらの構造は導電性粒子の流動
を制御するものではないため、バンプとパッド9との接
合部位で導電性粒子の分布密度が低く、バンプとバンプ
との間で分布密度が高くなるという現象が発生する。
Since these structures do not control the flow of the conductive particles, the distribution density of the conductive particles is low at the joint between the bump and the pad 9, and the distribution density between the bumps and the bump is low. The phenomenon of becoming high occurs.

【0045】そこで、図12および図13に示すよう
に、パッド9から内側に延びる粒子誘導溝12をレジス
ト10により形成する。
Therefore, as shown in FIG. 12 and FIG. 13, a particle guiding groove 12 extending inward from the pad 9 is formed by the resist 10.

【0046】これにより、図13に示すように、導電性
粒子2は粒子誘導溝12を通ってより高い密度になりな
がら外方向に流動してバンプとパッド9との間に到達す
るので、バンプとパッド9とに捕捉される粒子数が増加
して、捕獲粒子数を増加させるとともに絶縁性低下を引
き起こすことなくACF1を用いて半導体チップ4と回
路基板8とを電気的に接続することが可能になる。
As a result, as shown in FIG. 13, the conductive particles 2 flow outward while increasing in density through the particle guiding grooves 12 and reach between the bumps and the pads 9. The number of particles trapped on the semiconductor chip 4 and the circuit board 8 can be increased by using the ACF 1 without increasing the number of trapped particles and lowering the insulating property. become.

【0047】また、図14および図15に示すように、
レジスト10はパッド9とパッド9との間にまで存在し
ていてもよい。
As shown in FIGS. 14 and 15,
The resist 10 may be present between the pads 9.

【0048】なお、粒子誘導溝12はレジスト10以外
の絶縁性部材で形成してもよい。
The particle guiding groove 12 may be formed of an insulating member other than the resist 10.

【0049】(実施の形態4)図16は本発明の実施の
形態4における半導体装置の要部を示す説明図、図17
は図16のA−A’線に沿った断面図である。
(Embodiment 4) FIG. 16 is an explanatory view showing a main part of a semiconductor device according to Embodiment 4 of the present invention.
FIG. 17 is a sectional view taken along line AA ′ of FIG.

【0050】図示するように、本実施の形態では、パッ
ド9とパッド9との間から内側に延び、電気的接続を目
的としないダミーパッド(粒子誘導部材)16が形成さ
れている。
As shown, in this embodiment, a dummy pad (particle guiding member) 16 extending inward from between the pads 9 and not intended for electrical connection is formed.

【0051】これにより、図17に示すように、導電性
粒子2はダミーパッド16とダミーパッド16との間を
通ってより高い密度になりながら外方向に流動してバン
プとパッド9との間に到達するので、バンプとパッド9
とに捕捉される粒子数が増加して、捕獲粒子数を増加さ
せるとともに絶縁性低下を引き起こすことなくACF1
を用いて半導体チップ4と回路基板8とを電気的に接続
することが可能になる。
As a result, as shown in FIG. 17, the conductive particles 2 flow between the dummy pad 16 and the dummy pad 16 and move outward while increasing the density, and the space between the bump and the pad 9 is increased. To reach the bumps and pads 9
The number of particles captured by the ACF1 increases without increasing the number of captured particles and causing a decrease in insulation.
To electrically connect the semiconductor chip 4 and the circuit board 8.

【0052】なお、本実施の形態においてはACF1を
用いたフリップチップ実装について説明したが、本発明
はACF1を用いた場合に限定されるものではなく、異
方導電性ペースト−ACP(Anisotropic
Conductive Paste)−など導電性粒子
が分散された種々の異方導電性部材を介して電気的接続
を得るフリップチップ実装に適用される。
In this embodiment, the flip-chip mounting using the ACF1 has been described. However, the present invention is not limited to the case where the ACF1 is used, but the anisotropic conductive paste-ACP (Anisotropic).
(Conductive Paste)-is applied to flip chip mounting for obtaining electrical connection through various anisotropic conductive members in which conductive particles are dispersed.

【0053】[0053]

【発明の効果】以上のように、本発明によれば、突起状
電極上における粒子密度が高くなり、その間隙部におけ
る粒子密度は低くなって突起状電極と回路基板電極とに
捕捉される粒子数が増加するとともに突起状電極相互間
に位置する粒子数は少なくなので、捕獲粒子数を増加さ
せるとともに絶縁性低下を引き起こすことなく異方導電
性部材を用いて半導体チップと回路基板とを電気的に接
続することが可能になるという有効な効果が得られる。
As described above, according to the present invention, the particle density on the protruding electrode is increased, and the particle density in the gap is reduced, so that the particles captured by the protruding electrode and the circuit board electrode are reduced. As the number increases and the number of particles located between the protruding electrodes decreases, the number of trapped particles is increased and the semiconductor chip and the circuit board are electrically connected using an anisotropic conductive member without causing a decrease in insulation. An effective effect that it becomes possible to connect to the terminal is obtained.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施の形態1における半導体装置を示
す斜視図
FIG. 1 is a perspective view showing a semiconductor device according to a first embodiment of the present invention;

【図2】図1のB部を製造時における導電性粒子の流れ
とともに拡大して示す説明図
FIG. 2 is an explanatory diagram showing part B of FIG. 1 in an enlarged manner together with a flow of conductive particles during manufacturing.

【図3】図1のB部を導電性粒子とともに拡大して示す
説明図
FIG. 3 is an explanatory view showing part B of FIG. 1 in an enlarged manner together with conductive particles.

【図4】本発明の実施の形態2における半導体装置を構
成する半導体チップを示す断面図
FIG. 4 is a sectional view showing a semiconductor chip included in a semiconductor device according to a second embodiment of the present invention;

【図5】半導体チップに形成されたダミーバンプを示す
斜視図
FIG. 5 is a perspective view showing a dummy bump formed on a semiconductor chip;

【図6】図5(c)に示すダミーバンプを用いた場合で
の製造時における導電性粒子の流れを示す説明図
FIG. 6 is an explanatory diagram showing a flow of conductive particles during manufacturing when the dummy bump shown in FIG. 5C is used.

【図7】図6に示す箇所の製造後の状態を示す説明図FIG. 7 is an explanatory view showing a state of the portion shown in FIG. 6 after manufacturing;

【図8】本発明者が検討対象とした半導体装置を示す斜
視図
FIG. 8 is a perspective view showing a semiconductor device studied by the present inventors.

【図9】(a)図8のA−A’線に沿った断面図 (b)図8のB−B’線に沿った断面図9A is a sectional view taken along line A-A 'in FIG. 8; FIG. 9B is a sectional view taken along line B-B' in FIG.

【図10】図8の半導体装置におけるレジスト塗布状態
の一例を示す説明図
FIG. 10 is an explanatory diagram showing an example of a resist application state in the semiconductor device of FIG. 8;

【図11】図8の半導体装置におけるレジスト塗布状態
の他の一例を示す説明図
FIG. 11 is an explanatory diagram showing another example of the resist application state in the semiconductor device of FIG. 8;

【図12】本発明の実施の形態3における半導体装置の
要部を示す説明図
FIG. 12 is an explanatory diagram showing a main part of a semiconductor device according to a third embodiment of the present invention;

【図13】図12のA−A’線に沿った断面図13 is a sectional view taken along the line A-A 'in FIG.

【図14】本発明の実施の形態3の変形例である半導体
装置の要部を示す説明図
FIG. 14 is an explanatory diagram showing a main part of a semiconductor device according to a modification of the third embodiment of the present invention;

【図15】図14のA−A’線に沿った断面図15 is a sectional view taken along the line A-A 'in FIG.

【図16】本発明の実施の形態4における半導体装置の
要部を示す説明図
FIG. 16 is an explanatory diagram showing a main part of a semiconductor device according to a fourth embodiment of the present invention;

【図17】図16のA−A’線に沿った断面図FIG. 17 is a sectional view taken along the line A-A ′ in FIG. 16;

【図18】従来のフリップチップ実装による半導体装置
を示す斜視図
FIG. 18 is a perspective view showing a conventional flip-chip mounted semiconductor device.

【図19】図18のB−B’線に沿った断面図19 is a sectional view taken along the line B-B 'of FIG.

【図20】図18の半導体装置の製造工程を連続して示
す説明図
FIG. 20 is an explanatory view showing the manufacturing process of the semiconductor device of FIG. 18 continuously;

【図21】図20の製造工程を経て得られた半導体装置
を示す斜視図
FIG. 21 is a perspective view showing a semiconductor device obtained through the manufacturing process of FIG. 20;

【図22】図21のB部を製造時における導電性粒子の
流れとともに拡大して示す説明図
FIG. 22 is an explanatory diagram showing part B of FIG. 21 in an enlarged manner together with the flow of conductive particles during manufacturing.

【図23】図21のB部を導電性粒子とともに拡大して
示す説明図
FIG. 23 is an explanatory view showing part B of FIG. 21 in an enlarged manner together with conductive particles.

【符号の説明】[Explanation of symbols]

1 異方導電性フィルム(異方導電性部材,ACF) 2 導電性粒子 3 絶縁性樹脂 4 半導体チップ 6 バンプ(突起状電極) 8 回路基板 8a 配線層 9 パッド(回路基板電極) 11 ダミーバンプ(粒子誘導突起) 12 粒子誘導溝 16 ダミーパッド(粒子誘導部材) DESCRIPTION OF SYMBOLS 1 Anisotropic conductive film (anisotropic conductive member, ACF) 2 Conductive particles 3 Insulating resin 4 Semiconductor chip 6 Bump (protruding electrode) 8 Circuit board 8a Wiring layer 9 Pad (circuit board electrode) 11 Dummy bump (particle) Guide protrusion) 12 Particle guide groove 16 Dummy pad (Particle guide member)

───────────────────────────────────────────────────── フロントページの続き (72)発明者 竹田 雅俊 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 Fターム(参考) 5E319 AA03 AB05 AC11 BB16 CC61 5F044 KK01 KK12 LL09 QQ02  ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Masatoshi Takeda 1006 Kazuma Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. F-term (reference) 5E319 AA03 AB05 AC11 BB16 CC61 5F044 KK01 KK12 LL09 QQ02

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】回路素子が作り込まれ、間隙部を形成して
複数の突起状電極が配列されるとともに前記突起状電極
の内側において前記突起状電極の前記間隙部間に間隙部
が位置するようにして複数の粒子誘導突起が配列された
半導体チップと、 配線層が形成されて表面に前記突起状電極に対応した複
数の回路基板電極が形成された回路基板と、 絶縁性樹脂およびこの絶縁性樹脂中に分散された導電性
粒子からなり、前記半導体チップと前記回路基板とを熱
圧着することにより前記突起状電極と前記回路基板電極
との間に前記導電性粒子を捕捉させて前記半導体チップ
と前記回路基板とを接合する異方導電性部材とを有する
ことを特徴とする半導体装置。
1. A circuit element is formed, a gap is formed, a plurality of projecting electrodes are arranged, and a gap is located between the gaps of the projecting electrodes inside the projecting electrodes. A semiconductor chip on which a plurality of particle guiding protrusions are arranged as described above; a circuit board on which a wiring layer is formed and a plurality of circuit board electrodes corresponding to the protruding electrodes are formed on the surface; The semiconductor chip is made of conductive particles dispersed in a conductive resin, and the semiconductor chip and the circuit board are thermocompression-bonded to trap the conductive particles between the protruding electrodes and the circuit board electrode, thereby forming the semiconductor. A semiconductor device having an anisotropic conductive member for joining a chip and the circuit board.
【請求項2】前記粒子誘導突起は柱状に形成されている
ことを特徴とする請求項1記載の半導体装置。
2. The semiconductor device according to claim 1, wherein said particle guiding projection is formed in a column shape.
【請求項3】前記粒子誘導突起は、2つの側面で構成さ
れるエッジ部の1つが内側に向けて配置された三角柱型
であることを特徴とする請求項2記載の半導体装置。
3. The semiconductor device according to claim 2, wherein the particle guiding projection has a triangular prism shape in which one of edge portions formed by two side faces is arranged inward.
【請求項4】回路素子が作り込まれ、間隙部を形成して
複数の突起状電極が配列された半導体チップと、 配線層が形成され、表面に前記突起状電極に対応した複
数の回路基板電極が形成されるとともに前記回路基板電
極から内側に延びる粒子誘導溝が形成された回路基板
と、 絶縁性樹脂およびこの絶縁性樹脂中に分散された導電性
粒子からなり、前記半導体チップと前記回路基板とを熱
圧着することにより前記突起状電極と前記回路基板電極
との間に前記導電性粒子を捕捉させて前記半導体チップ
と前記回路基板とを接合する異方導電性部材とを有する
ことを特徴とする半導体装置。
4. A semiconductor chip in which circuit elements are formed, a gap portion is formed and a plurality of protruding electrodes are arranged, and a wiring layer is formed, and a plurality of circuit boards corresponding to the protruding electrodes are formed on the surface. A circuit board on which an electrode is formed and a particle guiding groove extending inward from the circuit board electrode is formed; an insulating resin and conductive particles dispersed in the insulating resin; Having an anisotropic conductive member for joining the semiconductor chip and the circuit board by capturing the conductive particles between the protruding electrode and the circuit board electrode by thermocompression bonding a substrate. Characteristic semiconductor device.
【請求項5】回路素子が作り込まれ、間隙部を形成して
複数の突起状電極が配列された半導体チップと、 配線層が形成され、表面に前記突起状電極に対応した複
数の回路基板電極が形成されるとともに前記回路基板電
極と前記基板電極との間から内側に延びる粒子誘導部材
が形成された回路基板と、 絶縁性樹脂およびこの絶縁性樹脂中に分散された導電性
粒子からなり、前記半導体チップと前記回路基板とを熱
圧着することにより前記突起状電極と前記回路基板電極
との間に前記導電性粒子を捕捉させて前記半導体チップ
と前記回路基板とを接合する異方導電性部材とを有する
ことを特徴とする半導体装置。
5. A semiconductor chip in which circuit elements are formed, a gap is formed and a plurality of protruding electrodes are arranged, and a wiring layer is formed, and a plurality of circuit boards corresponding to the protruding electrodes are formed on the surface. A circuit board on which an electrode is formed and a particle guiding member extending inward from between the circuit board electrode and the board electrode; and an insulating resin and conductive particles dispersed in the insulating resin. Anisotropically conducting the semiconductor chip and the circuit board by thermocompression bonding to capture the conductive particles between the protruding electrode and the circuit board electrode and joining the semiconductor chip and the circuit board. A semiconductor device comprising: a conductive member.
JP2000048851A 2000-02-25 2000-02-25 Semiconductor device Pending JP2001237278A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000048851A JP2001237278A (en) 2000-02-25 2000-02-25 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000048851A JP2001237278A (en) 2000-02-25 2000-02-25 Semiconductor device

Publications (1)

Publication Number Publication Date
JP2001237278A true JP2001237278A (en) 2001-08-31

Family

ID=18570880

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000048851A Pending JP2001237278A (en) 2000-02-25 2000-02-25 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2001237278A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007035743A (en) * 2005-07-25 2007-02-08 Asahi Kasei Electronics Co Ltd Circuit connection method and connection structure
JP2007103439A (en) * 2005-09-30 2007-04-19 Optrex Corp Semiconductor integrated circuit
JP2009295857A (en) * 2008-06-06 2009-12-17 Optrex Corp Connecting structure of ic chip and external wiring, and ic chip
JP2011049362A (en) * 2009-08-27 2011-03-10 Seiko Epson Corp Method for manufacturing semiconductor circuit device, semiconductor circuit device, and electro-optical device
US20110139501A1 (en) * 2009-12-16 2011-06-16 Lin Ching-San Electronic chip and substrate with shaped conductor
CN103065990A (en) * 2012-12-12 2013-04-24 山西国惠光电科技有限公司 Wafer level inversion interconnection method
JP2014140035A (en) * 2014-01-23 2014-07-31 Seiko Epson Corp Semiconductor circuit device manufacturing method and semiconductor circuit device

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007035743A (en) * 2005-07-25 2007-02-08 Asahi Kasei Electronics Co Ltd Circuit connection method and connection structure
JP2007103439A (en) * 2005-09-30 2007-04-19 Optrex Corp Semiconductor integrated circuit
JP4739895B2 (en) * 2005-09-30 2011-08-03 オプトレックス株式会社 Semiconductor integrated circuit
JP2009295857A (en) * 2008-06-06 2009-12-17 Optrex Corp Connecting structure of ic chip and external wiring, and ic chip
JP2011049362A (en) * 2009-08-27 2011-03-10 Seiko Epson Corp Method for manufacturing semiconductor circuit device, semiconductor circuit device, and electro-optical device
US20110139501A1 (en) * 2009-12-16 2011-06-16 Lin Ching-San Electronic chip and substrate with shaped conductor
CN103065990A (en) * 2012-12-12 2013-04-24 山西国惠光电科技有限公司 Wafer level inversion interconnection method
JP2014140035A (en) * 2014-01-23 2014-07-31 Seiko Epson Corp Semiconductor circuit device manufacturing method and semiconductor circuit device

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