JP2001236788A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To miniaturize the constitution and to achieve low power consumption of a semiconductor memory in which word lines are made a hierarchical state and a block state, and a load circuit of bit lines is arranged at a reverse side to a write-in/read-out of bit lines. SOLUTION: This device is constituted so that a pre-charge control signal of a bit line load circuit 3 is generated by a bit line load control circuit 4 from a word line selecting signal arranged parallel to the bit lines and a pre-charge clock signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device in which a word line selection signal is a pulse signal, and more particularly to a bit line load circuit in an SRAM (static random access memory). The present invention relates to a semiconductor memory device having improved technology.

[0002]

2. Description of the Related Art A semiconductor memory device which is frequently used as a cache memory because data can be read / written at a high speed and in which word lines are hierarchized, such as an SRAM.
For example, there is a conventional configuration shown in FIG. In FIG. 9, the SRAM has four word lines WL for each main word line of a large number of main word lines MWL (0, 1,...), For example, main word line MWL0.
0 to WL3 are hierarchized, and the word lines WL0 to WL3 are selected and controlled in accordance with the selection signal of the main word line MWL0 and the logical product signal of the corresponding word line selection signals (SD0 to SD3). To enable high-speed read / write operations, bit lines (BL, /
Bit line load circuit 101 for precharging BL)
Is on the side opposite to the bit line write / read circuit 103 with respect to the array of memory cells 102 (hereinafter referred to as the upper side of the bit line and the write / read circuit side as the lower side of the bit line). The memory cell 102 is laid out at a position and provided corresponding to each bit line pair.
After the end of reading / writing of data, a precharge control signal (/) which is an output of the bit line load control circuit 104 that inputs a precharge clock signal (/ PCLK) for precharge control synchronized with the main clock signal (CK) of the device. PC) to charge and equalize the bit lines. FIG. 10 shows an operation timing chart of FIG.

It is desirable to control the load of such bit lines by dividing the array of the memory cells 102 into appropriate blocks in order to reduce power consumption.
Therefore, for such bit line load control, a block selection signal (SEL) indicating selection / non-selection of the block is used.
Is required. This block selection signal is usually generated and supplied by a control circuit such as a bit line write / read circuit. For this reason, in a conventional semiconductor memory device,
In order to control the bit line load circuit 101 on the upper side of the bit line, it is necessary to supply the block selection signal to the bit line load control circuit 104 provided on the upper side of the bit line. Therefore, the block selection signal on the lower side of the bit line must be wired to the bit line load circuit 104 on the upper side of the bit line, and the block selection signal is transmitted to the memory cell 102.
Array had to be traversed. For this reason, in a storage device having a storage capacity of a megabit level, the number of divisions of the memory cell array is 100 or more, so that the wiring space for the block selection signal is extremely large, and the chip area is increased. Further, the wiring of the block selection signal becomes longer in the longitudinal direction of the memory cell array, so that the driving power of the block selection signal must be increased, and the power consumption has increased.

[0004]

As described above,
In a conventional semiconductor memory device in which a bit line load circuit is provided on the upper side of a bit line, when the above-mentioned bit line load circuit corresponding to each block of the divided memory cell array is divided and controlled, the division control is performed. It was necessary to cause a block selection signal as a control signal to traverse the memory cell array. As a result, a wiring space for the block selection signal is required in the area of the memory cell array,
This causes a problem that the chip area increases. Further, a large driving force is required to drive the block selection signal at a high speed, which causes a problem that power consumption increases.

The present invention has been made in view of the above, and it is an object of the present invention to provide a structure in which word lines are hierarchized and blocked, and a load circuit for bit lines is provided for a memory cell array. An object of the present invention is to provide a semiconductor memory device which can achieve a reduction in size and a reduction in power consumption of a semiconductor memory device arranged on the side opposite to a write / read circuit.

[0006]

In order to achieve the above object, a first means for solving the problems is that word lines are hierarchized, and a word line selection signal of a word line for selecting a memory cell is pulsed. The word line selection signal is wired in parallel with a bit line of a memory cell array, the memory cell is accessed by a write / read circuit via the bit line, and the bit line is controlled based on a pulsed precharge control signal. In a semiconductor memory device, a precharge operation is divided and controlled in block units by a bit line load circuit, and the bit line load circuit is controlled based on a precharge control signal supplied from the bit line load control circuit. The load circuit and the bit line load control circuit are configured to perform the write / read with the memory cell array interposed therebetween. The bit line load control circuit generates a precharge control signal based on a delay signal obtained by delaying the word line selection signal and a precharge clock signal. It is characterized by becoming.

The second means is that a word line is hierarchized, a word line selection signal of a word line for selecting a memory cell is pulsed, and the word line selection signal is wired in parallel with a bit line of a memory cell array. The memory cell is accessed by a write / read circuit via the bit line, and the bit line is divided and controlled in a block unit by a bit line load circuit based on a pulsed precharge control signal. In a semiconductor memory device in which a bit line load circuit is controlled based on a precharge control signal given from a bit line load control circuit, the bit line load circuit and the bit line load control circuit are arranged so that the bit line load circuit sandwiches the memory cell array. It is arranged on the side opposite to the position where the write / read circuit is arranged,
The bit line load control circuit may include a flip-flop circuit that has one input as the word line selection signal, the other input as a precharge clock signal, and outputs a signal for generating the precharge control signal. Features.

[0008] The third means is the second means,
The flip-flop circuit is set by the word line selection signal and reset by a rise of the precharge clock signal, and the precharge control signal is obtained by a logical operation of the output signal of the flip-flop circuit and the precharge clock signal. It is characterized by being generated.

The fourth means is the first means,
The bit line load control circuit receives a delay output of the delay circuit for delaying the word line selection signal and generates a first pulse signal obtained by pulsing the delayed word line selection signal. A first pulse generation circuit, a second pulse generation circuit that receives a precharge clock signal and generates a second pulse signal obtained by pulsing the precharge clock signal, and the first pulse is applied to one input. And a flip-flop circuit to which a signal is supplied and the second pulse signal is supplied to the other input, and which outputs a signal for generating the precharge control signal.

The fifth means is the fourth means,
The first pulse signal and the second pulse signal are set at timings at intervals of about half the cycle time by the delay circuit.

[0011]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a configuration of a semiconductor memory device according to an embodiment of the present invention. FIGS. 2 and 3 are operation timing charts of the device shown in FIG. In FIG. 1, a semiconductor memory device of this embodiment has a memory cell array in which a large number of memory cells 1 are arranged in rows and columns, the memory cell array is divided into blocks of an appropriate size, and word lines are hierarchized. In addition, the main word lines are divided into blocks of an appropriate size corresponding to the memory cell array, and four word lines WL are hierarchized for each of the main word lines MWL (0, 1,...), Each of the word lines WL is alternatively selected based on the logical product of the selection of the main word line MWL and the corresponding word line selection signal. For example, each of the word lines WL (0 to 0) corresponding to the main word line MWL0 is selected. 3) The selection of the main word line MWL0 selected in synchronization with the main clock signal (CK) and the corresponding word line WL
Selection control is alternatively performed according to the output of the AND gate 5 which receives the selection signals (SD0 to SD3) of (0 to 3). Hereinafter, the main word line MWL will be described as representative of the main word line MWL0 shown in FIG. 1, and the word lines WL hierarchized corresponding to the main word line MWL will be described as representative of the word lines WL0 to WL3 shown in FIG. . Main word line M
The selection signal (SD0 to SD3) for selecting WL0 and for each word line WL0 is converted into a pulse signal for performing high-speed reading / writing as shown in FIG. 2, and the main word line MWL0 and the word line WL0 are connected to the bit line. (BL, / BL), which are wired across the array of memory cells 1 so as to be orthogonal to (BL, / BL).
D0 to SD3) are laid in the memory cell 1 array in parallel with the bit lines (BL, / BL).

Each bit line (BL, / BL) pair is provided with a bit line load circuit 3 on the upper side of the memory cell array opposite to the lower side on which the write / read circuit 2 is arranged for the memory cell array. Connected and arranged. After the access to the memory cell 1 is completed and the word line is in the non-selected state, the bit line load circuit 3, as shown in FIG.
During a predetermined period (a period in which the precharge control signal (/ PC) is at a low level, not all periods until the next access starts after the word line is deselected, but the word line is deselected) Thereafter, the bit line is activated (at least for a limited period during which the precharging of the bit line is possible) to precharge the bit line. Activation of the bit line load circuit 3 is controlled by a bit line load control circuit 4. The bit line load control circuit 4 is arranged on the upper side of the memory cell array similarly to the bit line load circuit 3, and is provided for each word line division unit. The bit line load control circuit 4 includes selection signals (SD0 to SD3) for the word lines WL0 to WL3 and a precharge clock signal (/ PC) for precharge control.
LK) to generate and output a precharge control signal (/ PC) for controlling the activation of the bit line load circuit 3. The bit line load control circuit 4 receives the word line selection signals (SD0 to SD1) of the word lines WL0 to WL3 as NORs.
A gate 41, a delay circuit 42 for delaying a predetermined time (d 2) by receiving an output of the NOR gate 41, and a select signal (SEL) and a precharge clock signal (/ PCLK) which are outputs of the delay circuit 42 are inputted. A NAND gate 43 for outputting a precharge control signal (/ PC) is provided. Precharge clock signal (/ PCLK)
Is generated inside the device in synchronization with the main clock signal (CK).

In such a configuration, the main word line MWL0 and, for example, the word line WL0 are selected (selection signal SD0).
0 is set to the high level) and when the access of the selected memory cell 1 is completed, as shown in FIG.
Is selected, the delay circuit 42 of the bit line load control circuit 4
After a predetermined time d2 delayed by the selection signal (S
EL) is output, whereby the precharge control signal (/ PC) goes low, the bit line load circuit 3 precharges the bit line, and charges and equalizes the bit line.

As described above, according to the above embodiment, the bit line load circuit 3 arranged on the upper side of the memory cell array utilizes the word line selection signal wired in parallel with the bit line. The block selection signal for selecting the bit line block generated and supplied and divided and controlled at the lower side of the memory cell array is passed through the memory cell array from the lower side of the memory cell array. In addition, it is not necessary to provide wiring on the upper side of the memory cell array, a wiring area is not required, and the chip area can be reduced. Furthermore, it is not necessary to drive the block selection signal of a long wiring at high speed,
Power consumption can be reduced. In order to speed up the access, when the selection signal SD of the word line WL is pulsed as shown in FIG. 2, the selection signal SD of the word line WL is delayed as shown in FIG. The bit line load circuit 3 arranged on the upper side of the memory cell array can be controlled by the signal (SEL).

On the other hand, in such a configuration, the period during which the bit line load is activated, that is, the recovery time is limited by the select signal, so that when the frequency of the main clock signal (CK) is lowered, the recovery time is reduced. Time is not relaxed at all. FIG. 3 is a diagram showing an operation timing chart when the clock frequency is lower than that shown in FIG. 2 in the device having the configuration shown in FIG. FIG.
As shown in FIG. 2, the select signal (SEL) obtained by delaying the selection signal SD of the word line WL is generated only for a period equivalent to that shown in FIG. Therefore, an embodiment in which an optimum recovery time can be obtained according to the clock frequency even when the frequency of the main clock signal is reduced will be described as another embodiment of the present invention.

FIG. 4 is a diagram showing a configuration of a semiconductor memory device according to another embodiment of the present invention, and FIGS. 5 and 6 are diagrams showing operation timing charts of the device shown in FIG. In FIG. 4, the feature of this embodiment is that the configuration of the bit line load control circuit 4 is different from the configuration of the embodiment shown in FIG. 1, and the rest is the same as that shown in FIG. The bit line load control circuit 4 according to the present embodiment receives an input of a selection signal (SD0 to SD3) for the word line WL.
The output of the R gate 44 and the output of the OR gate 44 are received at a set terminal (S), the precharge clock signal (PCLK) synchronized with the main clock signal is received at a reset terminal (R), and the select signal (/ Q) is output (/ Q). / SEL), and an OR gate 4 for inputting a select signal and a precharge clock signal.
6 is provided.

In such a configuration, the F / F 45 is set when any of the selection signals (SD0 to SD3) of the word line WL is selected, and is repeatedly reset at the rising edge of the precharge clock signal. Line W
The word line selection / non-selection information of the block corresponding to the L selection signal is held. A precharge control signal (/ PC) is generated by the select signal (/ SEL) of the output of the F / F 45 and the precharge clock signal, and the bit line load circuit 3 of the selected block is turned on while the precharge control signal is at a low level. Activated, the corresponding bit line is precharged. In such an operation, when the device is operated at a relatively high frequency of the main clock signal as in FIG. 2, the optimum operation is performed according to the frequency of the main clock signal as in FIG. Recovery time can be secured. On the other hand, when the main clock signal is operated at a relatively low frequency as shown in FIG. 3, the selection / non-selection of the word line is held by the F / F 45 to extend the low level period of the select signal. The recovery time is extended compared to the high-speed operation shown in FIG.
As shown in FIG. 6, an optimum recovery time can be obtained according to the operating frequency of the main clock signal.

In such an embodiment, the same effects as those of the above embodiment can be obtained, and an optimum recovery time can be secured according to the operating frequency of the main clock signal.

FIG. 7 is a diagram showing another configuration of the bit line load control circuit 4, and FIG. 8 is an operation timing chart of the storage device employing the configuration of FIG. In FIG. 7, the bit line load control circuit 4 holds the selection / non-selection of the word line WL similarly to the bit line load control circuit 4 shown in FIG. SD
0 to SD3), a delay circuit 52 that receives the output of the NOR gate 51 and delays it by a predetermined time (d1), and a pulse generation circuit 53 that receives the output of the delay circuit 52 and outputs a pulse signal. And a pulse generation circuit 54 that receives the precharge clock signal (PCLK) to generate a pulse signal, and sets the output of the pulse generation circuit 53 to a set signal (/ S) and sets the output of the pulse generation circuit 54 to a reset signal (/ R). And a NAND gate 56 that inputs a select signal (SEL) of the output of the F / F 55 and an inverted signal of the precharge clock signal and outputs a precharge control signal (/ PC). .

In such a configuration, the F / F 55 2
The two inputs are pulse generating circuits 53, 5 as shown in FIG.
4, the set signal and the reset signal are set at intervals of approximately half a cycle of the main clock signal (cycle time) by the delay circuit 52. As a result, it is possible to secure a sufficiently large operation margin of the F / F 55, so that the F / F 55 does not malfunction at any place in a wide memory cell array. Therefore, a stable recovery time can be obtained at any bit line of the memory cell array.

[0022]

As described above, according to the present invention, the bit line load circuit is controlled by the hierarchical word line selection signal and the precharge clock signal. It is no longer necessary to traverse the chip, and a reduction in chip area and power consumption can be achieved. Further, even if the operating frequency changes, it is possible to secure an optimal recovery time according to the operating frequency.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a diagram showing an operation timing chart of the device shown in FIG. 1;

FIG. 3 is a diagram showing an operation timing chart of the device shown in FIG. 1;

FIG. 4 is a diagram showing a configuration of a semiconductor memory device according to another embodiment of the present invention.

FIG. 5 is a diagram showing an operation timing chart of the device shown in FIG. 4;

6 is a diagram showing an operation timing chart of the device shown in FIG.

FIG. 7 is a diagram showing a configuration of a bit line load control circuit shown in FIG. 4;

8 is a diagram showing an operation timing chart of the device shown in FIG. 4 employing the configuration shown in FIG. 7;

FIG. 9 is a diagram showing a configuration of a conventional semiconductor memory device.

FIG. 10 is a diagram showing an operation timing chart of the device shown in FIG. 9;

[Explanation of symbols]

 Reference Signs List 1 memory cell 2 write / read circuit 3 bit line load circuit 4 bit line load control circuit 41, 51 NOR gate 42, 52 delay circuit 43, 56 NAND gate 44, 46 OR gate 45, 55 flip-flop circuit 53, 54 pulse generation Circuit MWL Main word line WL Word line BL, / BL Bit line

Claims (5)

[Claims] 1. A word line is hierarchized, a word line selection signal of a word line for selecting a memory cell is pulsed, and the word line selection signal is wired in parallel with a bit line of a memory cell array. The bit line is accessed by a write / read circuit via the bit line, and the bit line is divided and controlled by a bit line load circuit in block units based on a pulsed precharge control signal. Is a semiconductor memory device controlled based on a precharge control signal given from a bit line load control circuit, wherein the bit line load circuit and the bit line load control circuit are connected to the write / read circuit with the memory cell array interposed therebetween. The bit line load control circuit is disposed on the side opposite to the position where The semiconductor memory device characterized by comprising generates a precharge control signal based on the selection signal of the serial word lines and the delayed signal and the precharge clock signal delayed. 2. A word line is hierarchized, a word line selection signal of a word line for selecting a memory cell is pulsed, and the word line selection signal is wired in parallel with a bit line of a memory cell array. The bit line is accessed by a write / read circuit via the bit line, and the bit line is divided and controlled by a bit line load circuit in block units based on a pulsed precharge control signal. Is a semiconductor memory device controlled based on a precharge control signal given from a bit line load control circuit, wherein the bit line load circuit and the bit line load control circuit are connected to the write / read circuit with the memory cell array interposed therebetween. The bit line load control circuit is disposed on the side opposite to the position where Square Input the as the word line selection signal, the semiconductor memory device characterized by comprising comprises a flip-flop circuit and the other input and the precharge clock signal, and outputs a signal for generating the precharge control signal. 3. The flip-flop circuit is set by the word line selection signal and reset by a rise of the precharge clock signal, and the precharge control signal includes an output signal of the flip-flop circuit and the precharge clock. 3. The semiconductor memory device according to claim 2, wherein the semiconductor memory device is generated by a logical operation of a signal. 4. A bit line load control circuit, comprising: a delay circuit for delaying the word line selection signal; and a first pulse receiving the delayed output of the delay circuit and pulsating the delayed word line selection signal. A first pulse generation circuit for generating a pulse signal; a second pulse generation circuit for receiving a precharge clock signal and generating a second pulse signal obtained by pulsing the precharge clock signal; And a flip-flop circuit to which the first pulse signal is supplied and the other input is supplied with the second pulse signal, and which outputs a signal for generating the precharge control signal. 2. The semiconductor memory device according to 1. 5. The semiconductor according to claim 4, wherein the first pulse signal and the second pulse signal are set at timings of about half the cycle time by the delay circuit. Storage device.