JP2001236784A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory to which high-speed access is enabled without complexing constitution. SOLUTION: A SDRAM 10 has a timing controller 1, a row address decoder 2, a column address decoder 3, a memory cell array 4, a read/write controller 5, I/O buffers 60, 690, 6180, 6270, and I/O terminals 70, 790, 7180, 7270. This SDRAM 10 is operated based on a basic clock signal CLK0, a first shift clock signal CLK90 of which the phase is shifted by 90 degrees for this basic clock signal CLK0, a second shift clock signal CLK180 of which the phase is shifted by 180 degrees for this basic clock signal CLK0, a third shift clock signal CLK270 of which the phase is shifted by 270 degrees for this basic clock signal CLK0.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device which performs data read / write operation in synchronization with a clock signal.

[0002]

2. Description of the Related Art Synchronous (Synchronous)
s) A DRAM (SDRAM) is a semiconductor memory device that latches each control signal at a rising (or falling) edge of a basic input clock and performs a data read / write operation in synchronization with the input clock. FIG. 8 shows a schematic configuration of a conventional SDRAM 101.

The SDRAM 101 comprises a timing controller 111, a row address decoder 112, a column address decoder 113, a memory cell array 114, a read / write controller 115, an input / output (I / O) buffer 116, and an I / O terminal 117.
Having.

A timing controller 111 receives an address input signal A, a row address strobe signal RAS, a column address strobe signal CAS, a write enable signal WE, and a clock signal CLK. Based on these signals, a row address decoder 112, The column address decoder 113 and the read / write controller 115 are controlled.

When a row address decoder 112 activates a word line and a column decoder 113 activates a bit line, a predetermined memory cell is selected from a plurality of memory cells constituting a memory cell array 114. In the case of a data read operation, data stored in the selected memory cell is transferred to the I / O buffer 115 via the read / write controller 115 and the I / O buffer 116.
The signal is output from the terminal 117 to the outside. In the case of a data write operation, data input from the I / O terminal 117 is
The data is written to the selected memory cell via the I / O buffer 116 and the read / write controller 115.

FIG. 9 is a timing chart showing a data read operation of the conventional SDRAM 101. Here, the CAS latency is “2” and the burst length is “4”.
The operation in the case where is set to is described.

The SDRAM 101 takes in the row address in synchronization with the rising edge of the clock signal CLK when the row address strobe signal RAS is in the active state (L level), and receives the column address strobe signal C
The column address is fetched in synchronization with the rising edge of the clock signal CLK when the AS is in the active state (L level), and the data read (read) operation is started.

Since the CAS latency is set to "2" and the burst length is set to "4", the SDRAM 1
01 is an I / O terminal 1 which outputs read data DO having a burst length of “4” two clocks later in synchronization with a clock signal CLK.
17 to output.

Next, by setting the write enable signal WE to the active state (L level) and setting the row address strobe signal RAS to the active state (L level), the SDRAM 101 turns the row synchronously with the rising edge of the clock signal CLK. An address is fetched, and a precharge operation and a row address reset operation are performed.

As described above, since the SDRAM 101 operates in synchronization with the clock signal CLK, if the clock signal CLK is shared with a system clock (for example, a clock signal on a motherboard), the system can be synchronized. Control becomes easy. Further, by employing the parallel operation and the burst mode by the internal pipeline, it becomes possible to transfer the second and subsequent bits of the data of the continuous address at a high speed.

[0011]

However, when performing a data read operation or a data write operation continuously, it is necessary to secure a time required for a data level change (for example, a change from H level to L level). For this reason, the conventional SDRAM has a limit in increasing the access speed.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor memory device capable of high-speed access without complicating the configuration.

[0013]

In order to solve the above-mentioned problems, there is provided a semiconductor memory device which accesses a memory cell array and performs a data write / read operation in synchronization with a basic clock signal. In the semiconductor memory device, the memory cell array is synchronized with a shift clock signal having a predetermined phase delay from the basic clock signal in parallel with access to the memory cell array synchronized with the basic clock signal. It is characterized by accessing. According to this configuration, after starting access to the memory cell array synchronized with the basic clock signal,
With a delay of the phase difference between the basic clock signal and the shift clock signal, access to the memory cell array synchronized with the shift clock signal starts.

According to the present invention, in parallel with the access to the memory cell array synchronized with the basic clock signal, the memory cell array is accessed in synchronization with each of a plurality of shift clock signals having different phase delays from the basic clock signal. A semiconductor memory device is provided. According to this configuration, for example, when the plurality of shift clock signals are the first shift clock signal, the second shift clock signal, and the third shift clock signal, after the start of access to the memory cell array synchronized with the basic clock signal, The access to the memory cell array synchronized with the first shift clock signal is started with a delay by the phase difference between the basic clock signal and the first shift clock signal, and after the access to the memory cell array synchronized with the first shift clock signal is started. , The first shift clock signal and the second
The access to the memory cell array synchronized with the second shift clock signal starts with a delay by the phase difference of the shift clock signal, and after the access to the memory cell array synchronized with the second shift clock signal starts, the second shift clock signal and the third Access to the memory cell array synchronized with the third shift clock signal is started with a delay by the phase difference of the shift clock signal.

Thus, for the memory cell array,
Since the access synchronized with the basic clock signal and the access synchronized with one or more shift clock signals are continuously performed in parallel, at least twice (shift clock) as compared with the access synchronized only with the basic clock signal. When there are a plurality of signals, data writing or data reading at a speed higher than that is possible.

[0016] As described in claim 2 or 5,
By providing the shift clock signal generator for generating the shift clock signal based on the basic clock signal, it is not necessary to prepare an input port for taking in the shift clock signal from outside. However, it is also possible to generate the shift clock signal externally. In this case, it is not necessary to provide a shift clock signal generator inside, so that the semiconductor memory device can be made compact.

According to the third aspect, the data read from the memory cell array in synchronization with the basic clock signal and the data read from the memory cell array in synchronization with the shift clock signal are shifted with the basic clock signal. There is provided a semiconductor memory device provided with a data selection circuit which sequentially selects with a phase difference from a clock signal and supplies the data to a data bus.

According to the present invention, the data read from the memory cell array in synchronization with the basic clock signal and the plurality of data read from the memory cell array in synchronization with each of the plurality of shift clock signals are provided. Are sequentially selected based on the mutual phase difference between the basic clock signal and the plurality of shift clock signals, and provided to a data bus.

Here, the phase difference between the basic clock signal and the shift clock signal and the phase difference between the plurality of shift clock signals are determined according to the clock signal serving as a reference for the operation of the external circuit to which the semiconductor memory device is connected. It is preferable to set. For example, if the frequency of the clock signal of the external circuit is 5
In the case of 00 MHz (cycle 2 ns), the phase difference between the basic clock signal and the shift clock signal is 2 ns, and the phase difference between each shift clock signal is also 2 ns. As a result, the time difference between the data read start timing from the memory cell array synchronized with the basic clock signal and the data read start timing from the memory cell array synchronized with the shift clock signal is 2 ns. Then, the data selection circuit first supplies the data read from the memory cell array to the data bus in synchronization with the basic clock signal, and supplies the data bus for 2 ns (that is, according to the phase difference between the basic clock signal and the shift clock signal). After (time), the data read from the memory cell array is supplied to the data bus in synchronization with the shift clock signal. As described above, according to the present invention, even when the frequency of the basic clock signal is lower than the frequency of the clock signal of the external circuit, data can be read out in synchronization with the clock signal of the external circuit.

[0020]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.
Preferred embodiments of the semiconductor memory device according to the present invention will be described in detail. In the following description and the accompanying drawings, components having substantially the same functions and configurations are denoted by the same reference numerals, and redundant description is omitted.

FIG. 1 shows a schematic configuration of an SDRAM 10 as a semiconductor memory device according to an embodiment of the present invention.

[0022] SDRAM10 the timing controller 1, a row address decoder 2, a column address decoder 3, the memory cell array 4, the read / write controller 5, I / O buffer _{6 0,} 6 _{90, 6 180,} 6
_270, and I / O terminals _{7 0,} 7 _{90, 7 180,} 7
₂₇₀ .

The SDRAM 10 includes a basic clock signal CLK ₀ , a first shift clock signal CLK _{90 having} a phase shifted by 90 ° with respect to the basic clock signal CLK ₀ , and a second shift clock having a phase shifted by 180 ° It operates based on the signal CLK ₁₈₀ and the third shift clock signal CLK ₂₇₀ shifted by 270 °.

The first to third shift clock signals CLK
_90,180,270Is the basic clock signal CLK₀Based on
SDRAM configured to generate internally
FIG. 2 shows 10 as SDRAM 10 int. This S
The DRAM 10 int is the timing controller described above.
1, row address decoder 2, column address decoder
3, memory cell array 4, read / write controller
5, I / O buffer 6 ₀, 6₉₀, 6₁₈₀,
6₂₇₀, And I / O terminal 7₀, 7₉₀, 7₁₈₀,
7₂₇₀In addition to the input basic clock signal CLK
₀From the first shift clock signal CLK₉₀int, second
Shift clock signal CLK₁₈₀int and third
Clock signal CLK₂₇₀generate and output int
It has a shift clock signal generator 8.

[0025] The timing controller 1, the address input signal A, the row address strobe signal RAS, a column address strobe signal CAS, a write enable signal WE, and a basic clock signal CLK ₀ is input, based on these signals, the row address decoder 2, the operation of the column address decoder 3, the read / write controller 5, and the shift clock signal generator 8.

Row address decoder 2 activates word line
And the column decoder 3 activates the bit line.
Therefore, a plurality of memory cells constituting the memory cell array 4 are
A predetermined memory cell is selected from the files. Data reading
In the case of a read operation, the data stored in the selected memory cell
Data read / write controller 5 and I / O
O buffer 6₀, 6₉₀, 6₁₈₀, 6₂₇₀Via
I / O terminal 7₀, 7 ₉₀, 7₁₈₀, 7₂₇₀Out of
Output to the unit. In the case of data write operation, I / O
Terminal 7₀, 7₉₀, 7₁₈₀, 7₂₇₀Input from
If the data is in the I / O buffer 6₀, 6₉₀, 6₁₈₀,
6₂₇₀And via the read / write controller 5
Then, the data is written to the selected memory cell.

FIG. 3 is a timing chart showing a data read operation of the SDRAM 10 int. Here, the CAS latency is “2” and the burst length is “4”.
The operation in the case where is set to is described. The frequency of the basic clock signal CLK ₀ is set to 125 MHz.

The shift clock signal generator 8, on the basis of the basic clock signal CLK _0, the first shift clock signal _CLK 90 int, the second shift clock signal CLK
_{18 0} int, and the third shift clock signal CLK
Generate ₂₇₀ int. First shift clock signal CLK ₉₀ i generated by shift clock signal generator 8
It is preferable that the phase difference between nt, the second shift clock signal CLK ₁₈₀ int, and the third shift clock signal CLK ₂₇₀ int be determined according to the system clock frequency of a device (for example, a memory controller) to which the SDRAM 10 int is connected. That is, when the memory controller is operating at a system clock frequency of 500 MHz (cycle t = 2 ns), the basic clock signal CLK0, the first shift clock signal CLK ₉₀ int,
The phase of each of the second shift clock signal CLK ₁₈₀ int and the third shift clock signal CLK ₂₇₀ int is shifted by 2 ns. As a result, the first shift clock signal CLK ₉₀ int becomes the basic clock signal C
The second shift clock signal CLK ₁₈₀ int is delayed by 90 ° with respect to the first shift clock signal CLK ₉₀ int, and the third shift clock signal CLK ₂₇₀ int is delayed by 90 ° with respect to LK ₀ . The phase is delayed by 90 ° with respect to the second shift clock signal CLK ₁₈₀ int. Incidentally, the retardation is preferably determined according to the relationship between the system clock frequency of the external device such as a frequency and a memory controller of the basic clock signal CLK _0, the present invention is, as described above every 90 ° Is not limited to the above phase shift. Further, the number of shift clock signals generated by the shift clock signal generator 8 is not limited to three.

[0029] SDRAM10int, as shown in FIG. 3, the row address strobe signal RAS takes in a row address in synchronization with the rising edge of the basic clock signal CLK ₀ when the active state (L level), the column address strobe signal CAS There takes in a column address in synchronization with the rising edge of the basic clock signal CLK ₀ when the active state (L level), initiates a data read (read) operation.

Since the CAS latency is set to "2" and the burst length is set to "4", the SDRAM 1
0int is to synchronize the read data DO ₀ of the burst length "4" with the basic clock signal CLK ₀ outputted from the I / O pin _{7 0} after two clocks. Then, the SDRAM 10
int sequentially outputs the read data DO ₉₀ having the burst length “4” every 2 ns to the first shift clock signal CLK _90.
in synchronism with the int output from the I / O terminals _{7 90,} the read data _{DO 180} of the burst length "4" in synchronization with the second shift clock signal _CLK 180 int I / O pin 7
₁₈₀ and read data DO ₂₇₀ having a burst length of “4” and a third shift clock signal CLK ₂₇₀ in
Output from the I / O terminal 7 ₂₇₀ in synchronization with t.

Next, by setting the write enable signal WE to the active state (L level) and setting the row address strobe signal RAS to the active state (L level), the SDRAM 10int
It captures the row address in synchronization with the rising edge of K _0, performing a precharge operation and a row address reset operation.

As described above, the shift clock signal generator 8
Has been described for the configuration of the SDRAM 10 int having the inside and its data read operation. This SDRAM 10
int, based on the basic clock signal CLK _0, is constructed first shift clock signal _CLK 90 int, the second shift clock signal _CLK 180 int, and the third shift clock signal _CLK 270 int to generate therein However, on the other hand, each shift clock signal may be externally input.

The SDRAM 10ext shown in FIG.
Has a configuration in which the shift clock signal generator 8 is omitted from the SDRAM 10 int shown in FIG. Then, this SDRAM10ext, first shift clock signal _CLK 90 int above, the second shift clock signal _CLK 180 int, and the third shift clock signal _CLK 270 first shift clock signal correspond to the int _CLK 90 ext, the 2 shift clock signal CLK ₁₈₀ ext and third shift clock signal C
LK ₂₇₀ ext is externally input.

The first shift clock signal CLK ₉₀ ex
t, the second shift clock signal _{CLK 1} 80 ext, and third shift clock signal _CLK 270 ext via the timing controller 1 (or directly)
It is input to the read / write controller 5.

FIG. 5 is a timing chart showing a data read operation of the SDRAM 10ext. Here, the CAS latency is “2” and the burst length is “4”.
The operation in the case where is set to is described. The frequency of the basic clock signal CLK ₀ is set to 125 MHz.

[0036] SDRAM10ext the basic clock signal CLK ₀ incorporation row address in synchronization with the rising edges, the column address strobe signal CAS is active (L level) when the row address strobe signal RAS is active (L level) basic clock signal CLK captures the column address in synchronization with the rising edge of the _0, starts reading data (read) operation when. Hereinafter, SDRAM10ext
A data read operation substantially the same as that of the above-described SDRAM 10int is performed.

Since the CAS latency is set to "2" and the burst length is set to "4", the SDRAM 1
0ext is to synchronize the read data DO ₀ of the burst length "4" with the basic clock signal CLK ₀ outputted from the I / O pin _{7 0} after two clocks. Then, the SDRAM 10
ext sequentially outputs the read data DO ₉₀ having the burst length “4” every 2 ns to the first shift clock signal CLK _90.
in synchronization with ext output from the I / O terminals _{7 90,} the read data _{DO 180} of the burst length "4" in synchronization with the second shift clock signal _CLK 180 ext I / O pin 7
_180, and outputs the read data DO ₂₇₀ having a burst length of “4” to the third shift clock signal CLK ₂₇₀ ex
Output from the I / O terminal 7 ₂₇₀ in synchronization with t.

Next, by setting the write enable signal WE to the active state (L level) and setting the row address strobe signal RAS to the active state (L level), the SDRAM 10ext enables the basic clock signal CL
It captures the row address in synchronization with the rising edge of K _0, performing a precharge operation and a row address reset operation.

As described above, the SDRAM 10 (SDRAM 10
10 int, SDRAM 10 ext) reads data
As a result of the operation, the I / O terminal 7₀, 7₉₀,
7₁₈₀, 7 ₂₇₀From the read data DO
₀, DO₉₀, DO₁₈₀, And DO₂₇₀Is output
These are input to the data selection circuit 20 shown in FIG.
You. The data selection circuit 20 is provided inside the SDRAM 10
As a circuit, or SDRAM 10 and data bus DB
And an external circuit located between the two.

The data selection circuit 20, four three-state buffer _{21 0,} 21 _90, 21 1 _{80, 21 270,}
Four AND gates 22 ₀ , 22 ₉₀ , 22 ₁₈₀ , 2
And a 2 _{2 70,} two inverters 23 and 24, and one NOR gate 25. The data selection circuit 20 has a system clock signal CLK of an external device such as a memory controller to which the SDRAM 10 is connected.
₀₀₀ and _divide- by-2 clock signal CLK ₀₀ , and system clock signal CLK ₀₀₀ by 4-divided clock signal (basic clock signal CLK _{0 of} SDRAM ₁₀ ).

The three stages provided in the data selection circuit 20
Buffer 21₀, 21₉₀, 21 ₁₈₀, 21₂₇₀
Input terminals are I / O terminals 7₀, 7₉₀, 7₁₈₀, 7
_{27 0}And each output terminal is connected to a data bus DB.
, And each control terminal is connected to an AND gate 22.
₀, 22₉₀, 22₁₈₀, 22₂₇₀To each output terminal
It is connected.

The first input terminal of the AND gate 22 ₀ is connected to the transmission line of data read enable signal REN, a second input terminal 2 divided clock signal CLK
₀₀ is connected to the transmission line, the third input terminal is connected to the output terminal of the inverter 23.

The first input terminal of the AND gate 22 ₉₀ is connected to the transmission line of data read enable signal REN, a second input terminal connected to an output terminal of the inverter 24, the third input terminal basic clock Signal C
LK ₀ is connected to the transmission line.

The first input terminal of the AND gate _{22 180} is connected to the transmission line of data read enable signal REN, a second input terminal 2 divided clock signal CL
K _{0 0} is connected to the transmission line, the third input terminal is connected to the transmission line of the basic clock signal CLK _0.

The first input terminal of the AND gate 22 ₂₇₀ is connected to the transmission line for the data read enable signal REN, and the second input terminal is connected to the output terminal of the NOR gate.

Input terminal of the [0046] Inverter 23 is connected to the transmission line of the basic clock signal CLK _0. The input terminal of the inverter 24 receives the divided clock signal CLK ₀₀
Connected to the transmission line. The first input terminal of the NOR gate 25 is connected to the transmission line 2 divided clock signal CLK _00, the second input terminal is connected to the transmission line of the basic clock signal CLK _0.

The data selection circuit 2 configured as described above
The operation of 0 will be described with reference to FIG. Here, the frequency of the system clock signal CLK ₀₀₀ is 500 MHz.
A description will be given in accordance with the case of z.

Since the frequency of the system clock signal CLK ₀₀₀ is 500 MHz, the frequency of the frequency-divided clock signal CLK ₀₀ and the frequency-divided clock signal CLK ₀ (base clock signal CLK ₀ ) generated by dividing the frequency by 2 and 4 are calculated. The frequencies are 250 MHz and 125 MHz, respectively.

[0049] with respect to the fundamental clock signal CLK _0, the first
Shift clock signal CLK ₉₀ is delayed by 90 ° in phase, and second shift clock signal CLK ₁₈₀ is delayed by 1 in phase.
80 ° delayed, the third shift clock signal CLK
₂₇₀ is 270 ° delayed in phase. Therefore, the basic clock signal CLK ₀ , the first shift clock signal CLK ₉₀ , and the second shift clock signal CL
K ₁₈₀ and the third shift clock signal CLK ₂₇₀
, The read data DO ₀ , the read data DO ₉₀ , the read data DO ₁₈₀ , and the read data DO ₂₇₀ read from the memory cells in synchronization with
Each I / O pin _{7 0,} 7 _90, 7 _{180, 7 2 70}
Are sequentially output with a time difference of 2 ns.

First, in cycle S1, the data read enable signal REN is asserted (H level). At this time, 2-divided clock signal _{CLK 00} is at H level, since the basic clock signal CLK ₀ is L level, four AND provided to the data selection circuit 20
Gate _{22 0,} 22 _90, 22 _{180, 22 270} of, an active state only the output of the AND gate 22 _0, other AND gates _{22 90, 22} 180, 22
The output of ₂₇₀ remains inactive. Then, the four 3-state buffers 21 ₀ , 21 ₉₀ , 21
_{180, 21 270} of the three-state buffer 21 ₀
Only the active state is set, and the other three-state buffers 21 ₉₀ , 21 ₁₈₀ , and 21 ₂₇₀ have their output terminals at high impedance. Accordingly, in cycle S1, via the three-state buffer 21 _0,
First data DO ₀ 1 read data DO ₀ is outputted to the data bus DB as read data DO.

[0051] In the following cycle S2, 2-divided clock signal _{CLK 00} is switched from H level to L level, the basic clock signal CLK ₀ is switched from L level to H level. Therefore, the four AND gates 22 ₀ , 22 ₉₀ , 2 provided in the data selection circuit 20
Of 2 _{180, 22 270,} an active state only the output of the AND gate _{22 90,} the output of the other AND gates _{22 0,} 22 _{180, 22 270} becomes inactive. And four three-state buffers 21
₀ , 21 ₉₀ , 21 ₁₈₀ , 21 ₂₇₀ , only the three-state buffer 21 ₉₀ is in the active state, and the other three-state buffers 21 ₀ , 21 ₁₈₀ , 21 _270
270 sets each output terminal to high impedance. Thus, the cycle S2, through the 3-state buffers _{21 90,} the first read data _{DO 9 0}
Data _{DO 90} 1 is output to the data bus DB as read data DO.

[0052] In the subsequent cycle S3, 2-divided clock signal _{CLK 00} is switched from L level to H level, the basic clock signal CLK ₀ is maintained at the H level.
Therefore, the four ANs provided in the data selection circuit 20
Of the D gates 22 ₀ , 22 ₉₀ , 22 ₁₈₀ , 22 ₂₇₀ , only the output of the AND gate 22 ₁₈₀ becomes active, and the other AND gates 22 ₀ , 22 ₉₀ , 2
The output of ₂₂₇₀ goes inactive. And
Four three-state buffers 21 ₀ , 21 ₉₀ , 21
₁₈₀ , 21 ₂₇₀ , the three-state buffer 21
Only ₁₈₀ is in the active state, and the other three-state buffers 21 ₀ , 21 ₉₀ , 21 ₂₇₀ have their output terminals at high impedance. Therefore,
In the cycle S3, the first data DO of the read data DO ₁₈₀ is output via the three-state buffer 21 _180.
180 1 are outputted to the data bus DB as read data DO.

In the subsequent cycle S4, the frequency-divided clock is divided by two.
Signal CLK₀₀Switches from H level to L level
And the basic clock signal CLK₀Is H level to L level
Switch to Therefore, the data selection circuit 20 is provided with
Four AND gates 22₀, 22₉₀, 2
2₁₈₀, 22₂₇₀Of which, AND gate 22₂₇₀
Only the output of the other
G22₀, 22₉₀, 22₁₈₀Output is inactive
State. And four three-state buffers 21
₀, 21₉₀, 21₁₈₀, 21₂₇₀Of which, 3
Port buffer 21₂₇₀Only becomes active,
Other three-state buffers 21₀, 21₉₀, 21
₁₈₀Indicates that each output terminal is high impedance.
I do. Therefore, in cycle S4, the three-state battery
Fa 21₂₇₀Through the read data DO ₂₇₀of
First data DO₂₇₀1 is data as read data DO.
Output to the data bus DB.

Thereafter, in cycles S5 to S8, the read
Outgoing data DO₀Second data DO of ₀2, read data
TA DO₉₀Second data DO of₉₀2. Read data D
O_{1 80}Second data DO of₁₈₀2, and read data
Data DO₂₇₀Second data DO of₂₇₀2 is read data
Are sequentially output to the data bus DB as data DO.
In steps S9 to S12, the read data DO₀The third
Data DO₀3, read data DO₉₀Third data
DO₉₀3, read data DO₁₈₀Of the third data D
O₁₈₀3, and read data DO₂₇₀3rd de
Data DO₂₇₀3 is the data buffer as the read data DO.
Are sequentially output to the data base DB, and in cycles S13 to S16
Read data DO₀Of the fourth data DO₀4, reading
Outgoing data DO₉₀Of the fourth data DO₉₀4, reading
Data DO₁₈₀Of the fourth data DO₁₈₀4, and reading
Extruded data DO₂₇₀Of the fourth data DO₂₇₀4 reads
Are sequentially output to the data bus DB as overflow data DO.
You. Then, in cycle S16, data read is performed.
The enable signal REN is negated (L level).
The data read operation is completed.

As described above, according to the SDRAM 10 according to the embodiment of the present invention, although the frequency of the internal basic clock signal is 125 MHz and the burst length is set to "4", Read data DO
Is output to the data bus DB at an extremely high frequency of 500 MHz, and its burst length is "16".
Stretched to Further, each bit data DO ₀ 1 to DO ₂₇₀ 1, DO ₀ 2 to DO 2 of the read data DO
₂₇₀ 2, DO ₀ 3-DO ₂₇₀ 3, DO ₀ 4-DO
₂₇₀ 4, the system clock signal CLK of the external device of the memory controller or the like SDRAM10 is connected
Since the synchronization with each cycle of _000, without providing a special configuration to an external device, it is possible to process the read data on the data bus DB efficiently.

Although the preferred embodiments of the present invention have been described with reference to the accompanying drawings, the present invention is not limited to such embodiments. It is clear that a person skilled in the art can conceive various changes or modifications within the scope of the technical idea described in the claims, and those modifications naturally fall within the technical scope of the present invention. It is understood to belong.

For example, the embodiment of the present invention
Although only the case where M10 performs the data read operation has been described, the present invention is not limited to this.
Similarly, high-speed access is possible in the data write operation.

[0058]

As described above, according to the semiconductor memory device of the present invention, high-speed access is possible while minimizing an increase in circuit scale.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an SDRAM according to an embodiment of the present invention.

FIG. 2 is a block diagram showing one embodiment of the SDRAM of FIG. 1;

FIG. 3 is a timing chart showing a data read operation of the SDRAM of FIG. 2;

FIG. 4 is a block diagram showing another embodiment of the SDRAM of FIG. 1;

FIG. 5 is a timing chart showing a data read operation of the SDRAM of FIG. 4;

FIG. 6 is a circuit diagram showing a configuration of a data selection circuit provided in the SDRAM of FIG. 1;

FIG. 7 is a timing chart showing an operation of the data selection circuit of FIG. 6;

FIG. 8 is a block diagram showing a configuration of a conventional SDRAM.

FIG. 9 is a timing chart showing a data read operation of the SDRAM of FIG. 8;

[Description of References] 1: Timing controller 2: Row address decoder 3: Column address decoder 4: Memory cell array 5: Read / write controller 6: I / O buffer 7: I / O terminal 8: Shift clock signal generator 10: SDRAM 20: Data selection circuit A: Address input signal CAS: Column address strobe signal CLK ₀ : Basic clock signal CLK ₉₀ : First shift clock signal CLK ₁₈₀ : Second shift clock signal CLK ₂₇₀ : Third shift clock signal CLK ₀₀ : 2 Divided clock signal CLK ₀₀₀ : System clock signal DB: Data bus DO: Read data RAS: Row address strobe signal REN: Data read enable signal WE: Write enable signal

Claims (6)

[Claims] 1. A semiconductor memory device which accesses a memory cell array and performs a data write / read operation in synchronization with a basic clock signal, wherein the semiconductor memory device performs the data writing / reading operation in parallel with the access to the memory cell array in synchronization with the basic clock signal. A semiconductor memory device, wherein the memory cell array is accessed in synchronization with a shift clock signal having a predetermined phase delay from a basic clock signal. 2. The semiconductor memory device according to claim 1, further comprising a shift clock signal generator for generating said shift clock signal based on said basic clock signal. 3. The data read from the memory cell array in synchronism with the basic clock signal and the data read from the memory cell array in synchronism with the shift clock signal are combined with the basic clock signal and the basic clock signal. 3. The semiconductor memory device according to claim 1, further comprising a data selection circuit for sequentially selecting the data with a phase difference from the shift clock signal and supplying the data to a data bus. 4. A semiconductor memory device for accessing a memory cell array and performing data write / read operation in synchronization with a basic clock signal, wherein the semiconductor memory device performs the data write / read operation in parallel with the access to the memory cell array in synchronization with the basic clock signal. A semiconductor memory device, wherein the memory cell array is accessed in synchronization with each of a plurality of shift clock signals having different phase delays from a basic clock signal. 5. The semiconductor memory device according to claim 4, further comprising a shift clock signal generator for generating said plurality of shift clock signals based on said basic clock signal. 6. The data read from the memory cell array in synchronization with the basic clock signal, and the plurality of data read from the memory cell array in synchronization with each of the plurality of shift clock signals, 5. A data selection circuit, comprising: a data selection circuit for sequentially selecting a basic clock signal and a plurality of shift clock signals with a mutual phase difference and supplying the selected data to a data bus.
Or the semiconductor memory device according to 5.