JP2001236782A - Synchronizing type dram - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a synchronizing type DRAM in which a usable balance time is long and read-operation following write-operation is sure. SOLUTION: A DDR-SDRAM has an input buffer 1, a command decoder 2, a write-timing generating section 3, a write-buffer 4, a read-amplifier 5, a memory cell plate 6, and a data latch 7. A system clock CLK is supplied to the command decoder 2, a data strobe signal DQS is supplied to the write-timing generating section 3 and the data latch 7. In the DDR-SDRAM, read-out from the memory cell by read-operation is performed synchronizing with the system clock CLK, writing in the memory cell by write-operation is performed based on the data strobe signal DQS.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a synchronous DRAM, and more particularly, to a double data rate synchronous DR.
The present invention relates to a circuit configuration for performing synchronous control of write and read operations of AM (hereinafter, referred to as DDR-SDRAM).

[0002]

2. Description of the Related Art A DDR-SDRAM utilizes a system clock input from the outside and a data strobe signal input / output in synchronization with transfer data, and both have the same period. Control of write and read operations is performed based on a system clock and a data strobe signal. The standards for the system clock and the data strobe signal are defined by JEDEC specifications. For example, according to the JEDEC specification, the clock input delay time Td indicating the time difference between the two signals is 75% to 12% of the clock signal period Tck.
It is determined to be 5% of the time.

FIG. 5 is a block diagram showing a signal flow during a write operation of a conventional DDR-SDRAM. The system clock CLK is supplied to the command decoder 2, the write timing generator 3, and the system synchronization latch 8 as an SA synchronization signal, and the data strobe signal DQ
The signal S is supplied as an SC latch signal to the data latch 7 disposed before the system synchronization latch 8. Data latch 7 latches input data DQ in synchronization with data strobe signal DQS. Thereafter, the system synchronization latch 8 latches the contents of the data latch 7 in synchronization with the system clock CLK. DDR-SDRA
M indicates that the write and read operations are performed by the system clock CLK.
Sync to.

FIG. 6 is a timing chart at the time of a write and read operation of a conventional DDR-SDRAM. D
The DR-SDRAM starts a write operation when a first clock pulse P1 of the system clock CLK rises. The transfer data and the data strobe signal DQS are
Input from outside. The data latch 7 latches data 0 at time t0 as transfer data and latches data 1 at time t1. The system synchronizing latch 8 operates at time t2.
Then, the contents of the data latch 7 are latched, and data 0 and 1 are latched.
Is input to the write buffer 4 as internal data DI. The write timing generator 3 outputs the system clock C
The write signal SE is input to the write buffer 4 in synchronization with LK. The write buffer 4 outputs a differential voltage to a pair of common data input / output lines (hereinafter, referred to as I / O lines) 9 in synchronization with the write signal SE.

In the DDR-SDRAM, a read operation is started at the rise of the fourth clock pulse P4 of the system clock CLK, and the read amplifier 5 inputs a differential voltage from the I / O line 9. The transfer data and the data strobe signal DQS are output to the outside.

Writing to a memory cell by a write operation,
Reading from a memory cell by a read operation is started in synchronization with the system clock CLK.

According to the JDEC specification of the DDR-SDRAM, the minimum time when the operation shifts from the write operation to the read operation is two clock signal periods Tck, and the data strobe signal D with respect to the system clock CLK.
Clock signal phase difference time T which is a predetermined phase delay of QS
d is at most 125% of the clock signal period Tck.

[0008]

From the time t3b when the write operation ends to the time t4 when the read operation starts, the balance time during which the I / O line 9 is disconnected from the bit line in the memory cell plate 6 is set. is necessary. As an example, if the clock signal period Tck is 6.5 ns and the time required to connect the I / O line and the bit line is 4 ns, the time that can be used as the balance time is 6.5-4.
= 2.5 ns.

For example, since the maximum value of the differential voltage of the complementary signal of the I / O line 9 is about 2.2 V in the write operation and about 0.2 V in the read operation, the write operation of the I / O line 9 is 2.5 ns. There is a possibility that the balance time for making the differential voltage zero for the next read operation may be insufficient. When the two differential voltages have opposite polarities, it becomes remarkable unless there is a balance time.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and a synchronous DRA in which a read operation following a write operation is reliably performed.
M is intended to be provided.

[0011]

In order to achieve the above object, a synchronous DRAM according to the present invention comprises a system clock,
What is claimed is: 1. A synchronous DRAM which operates based on a data strobe signal having a predetermined phase delay from said system clock, wherein a read operation is performed in synchronization with said system clock, and input data input based on a data strobe signal. Is performed on the basis of the data strobe signal.

In the synchronous DRAM of the present invention, since the write operation for writing to the memory cell starts in synchronization with the data strobe signal, the balance time becomes longer than when the write operation starts in synchronization with the system clock. The read operation following the operation is assured.

[0013] In the synchronous DRAM of the present invention, the predetermined phase delay may be 75% to 1% of the cycle of the system clock.
Up to 25%.

Also, in the synchronous DRAM of the present invention, a plurality of the data strobe signals and input data corresponding to the data strobe signals are input, and each of the input data is connected to a corresponding I / O line. It is preferable to write the data into the memory cell through the memory cell. In this case, a plurality of data are processed at the same time, so that the data processing ability is improved.

In the synchronous DRAM according to the present invention, the plurality of data strobe signals are synchronized with each other, or the plurality of data strobe signals have a phase difference with each other and are synchronized with a data strobe signal having the most delayed phase. It is also a preferred embodiment of the present invention that the write operation is started after that. In this case, the data processing capability is improved, and the read operation following the write operation is ensured.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A synchronous DRAM according to the present invention will be described below with reference to the drawings based on an embodiment of the present invention. FIG. 1 shows a DDR- according to the first embodiment of the present invention.
FIG. 3 is a block diagram showing a signal flow during a write operation of the SDRAM. The DDR-SDRAM includes an input buffer 1, a command decoder 2, a write timing generator 3, a write buffer 4, a read amplifier 5, a memory cell plate 6,
Further, the burst length indicating the number of multi-bit data having the data latch 7 and performing the write and read operations is 2.

The buffer 1 receives a signal input from the outside and transmits it to each circuit in the DDR-SDRAM. The command decoder 2 has a row address strobe (RA
S), column address strobe (CAS), write enable (WE), and chip select signal (CS)
, And decodes the requested instruction. The write timing generator 3 generates a signal required for a write operation. The write buffer 4 writes data to the selected memory cell via the I / O line 9. The read amplifier 5 reads data from the selected memory cell via the I / O line 9. The memory cell plate 6 has a number of word lines extending in the row direction, a number of bit lines extending in the column direction, and a plurality of memory cells connected thereto. When one memory cell is selected, the corresponding bit line and I / O line 9 conduct. Data latch 7
Latches data as DDR that operates at the rise and fall of the data strobe signal DQS.

The DDR-SDRAM employs an I / O
It has input buffers 1, data latches 7, write buffers 4, read amplifiers 5, and I / O lines 9 as many as the number of components. Input / output data is composed of multiple bits.
The DDR-SDRAM employs a number of I / O configurations corresponding to the number of input / output data bits.

When a DDR-SDRAM performs a write operation with two burst lengths, two multi-bit data are input. One data (R side) is latched at the rising edge of the data strobe signal DQS, and the other data (F side) is latched at the falling edge of the data strobe signal DQS. The data latch 7, the write buffer 4, the read amplifier 5, and the I / O line 9 operate independently in two internal functions, and correspond to R-side and F-side data transfer.

The system clock CLK is a synchronous signal SA
The data strobe signal DQS is supplied to the write timing generator 3 as the timing signal SD, and is supplied to the data latch 7 as the latch signal SC.

The command decoder 2 synchronizes with RAS, CAS, WE, and CS in synchronization with the system clock CLK.
To monitor. When CS, CAS, and WE are at L level and RAS is at H level, the command decoder 2 recognizes that the command is a write instruction and inputs an H level decode signal SB to the write timing generation unit 3. I do.

When the decode signal SB goes to the H level, the write timing generator 3 outputs the data strobe signal DQ
The write signal SE synchronized with S is input to the write buffer 4.

The write buffer 4 starts writing to a memory cell by a write operation in synchronization with the data strobe signal DQS.

FIG. 2 shows a DDR according to the first embodiment of the present invention.
4 is a timing chart of write and read operations of the SDRAM. The DDR-SDRAM operates with two burst lengths, and transfers data 0 as transfer data at the rising edge of the first clock pulse P1 of the system clock CLK.
Then, a write operation for writing two multi-bit data of data 1 into the memory cell is started. Data 0 is written to address 0, and data 0 is written to an internally generated address based on address 0.

Transfer data and data strobe signal DQ
S is input from outside. Data strobe signal DQ
S has a clock signal phase difference time Td of 75% to 125% of the clock signal period Tck with respect to the system clock CLK.

Data latch 7 latches multi-bit data 0 at time t0 and multi-bit data 1 at time t1. When a predetermined time has elapsed from time t1, the data latch 7 simultaneously inputs data 0 and data 1 to the write buffer 4 as internal data DI.
The write buffer 4 outputs a differential voltage to the I / O line 9,
At time t3a, the I / O line 9 and the bit line are disconnected, and the write operation ends.

The DDR-SDRAM reads the multi-bit data 0 indicated by the address 1 at the rise of the fourth clock pulse P4 of the system clock CLK, and reads the multi-bit indicated by the address generated internally based on the address 1. A read operation for reading the configuration data 1 is started.

Transfer data and data strobe signal DQ
S is output to the outside. At time t4, the I / O line 9 and the bit line conduct, and the read amplifier 5 inputs a differential voltage of the I / O line 9. In the transfer data, data 0 is read at time t5, and data 1 is read at time t6.

Here, the clock signal period Tck is 6.5.
ns, the time required to connect the I / O line and the bit line is 4 ns, and the clock signal phase difference time Td is 8.125.
An example of ns will be described. At time t3a, which is the end time of the write operation, the start of writing to the memory cell by the write operation is synchronized with the data strobe signal DQS, so that it is 1.625 ns earlier than time t3b, so that the usable balance time is longer. Become.

FIG. 3 is a detailed timing chart of the write operation of the DDR-SDRAM. DDR-SD
The RAM employs an 8-I / O configuration and operates as a 4-burst length. The DDR-SDRAM operates at time t1
1, a command and an external address indicating address 1 are input, a 4-burst-length write operation is started for the memory cells of addresses 1 to 4, and at time t12, data strobe signals DQS for 2 cycles and 8 Data 1 to 4 having a bit configuration are input. Data 1 to 4 are information written in four address 1 to address 4 areas.

The synchronization signal SA is the system clock CLK.
, And is supplied to the command decoder 2. The latch signal SC is the data strobe signal CL
It occurs in synchronization with the rise and fall of K and is supplied to the data latch 7. The timing signal SD is generated in synchronization with the fall of the data strobe signal CLK, and is supplied to the write timing generator 3.

The command decoder 2 decodes the command signal in synchronization with the synchronization signal SA, and outputs a decode signal SB indicating a write operation to the write timing generator 3. The data latch 7 latches the data 1 as the internal data R at the rise of the first signal pulse P1 of the latch signal SC, and outputs the first signal pulse P of the latch signal SC.
At the falling edge of 1, data 2 is latched as internal data F,
Data 3 is latched as internal data R at the rising edge of the second signal pulse P2 of the latch signal SC, and data 4 is latched as internal data F at the falling edge of the second signal pulse P2 of the latch signal SC. And F to the write buffer 4. The write timing generator 3 supplies a write signal SE, which is a timing signal of a write operation, to the write buffer 4 in synchronization with the timing signal SD.

The DDR-SDRAM has an address latch circuit (not shown). The address latch circuit synchronizes with the system clock CLK, latches the address 1 which is the content of the external address as the first internal address, latches the address 1 as the second internal address in the next cycle, and stores the address 1 in an internal circuit (not shown). Output to counter. The internal counter calculates the data 2 based on the address 1.
To generate addresses 2 to 4 corresponding to data 4 and output addresses 1 to 4 to the address latch circuit. The address latch circuit latches addresses 1 and 3 as the third internal address R and latches addresses 2 and 4 as the third internal address F in synchronization with the timing signal SD.

At the rising edge of the first signal pulse P1 of the write signal SE, the write buffer 4 applies data 1 and data to the memory cell at address 1 via the I / O line R of the I / O line 9.
Data 2 is output to the memory cell at address 2 via I / O line F of I / O line 9. Also, the second of the write signal SE
At the rise of the signal pulse P2, the data 3 is supplied to the memory cell at address 3 via the I / O line R of the I / O line 9, and the I / O line F of the I / O line 9 is supplied to the memory cell at address 4. To write data 4 in the memory cell plate 6.

In the DDR-SDRAM, reading from a memory cell by a read operation is executed in synchronization with a system clock CLK, and writing to a memory cell by a write operation is performed by a data strobe signal DQS and a signal generated from the data strobe signal DQS. It is executed based on.

According to the above embodiment, the write operation to the memory cell by the write operation is performed by the data strobe signal DQS.
, The usable balance time is longer than in the case of starting in synchronization with the system clock CLK, so that the read operation following the write operation is reliably performed.

FIG. 4 shows a DDR according to the second embodiment of the present invention.
4 is a detailed timing chart of a write operation of the SDRAM. In the DDR-SDRAM of the second embodiment, the processing corresponding to the input system composed of the data strobe signal DQS and the corresponding input data DQ is performed on the U side (for upper bits of the multi-bit configuration data) and the L side (multi-bit configuration data). This is different from the previous embodiment in that it is composed of two systems (for lower bits). The DDR-SDRAM employs a 16-I / O configuration and operates at a 4-burst length.

FIG. 4 shows the U-side data strobe signal UDQ.
An example is shown in which the phase difference between S and the L-side data strobe signal LDQS is a half cycle of the clock signal. DDR-
In the SDRAM, an external address indicating address 1 is input, and data A1 to A4 on the U side and data B1 on the L side are input.
To B4 are input.

Data A1 and B1, data A2 and B2, data A3 and B3, and data A4 and B4 are 16 bits respectively.
Bit-structured data, address 1, address 2,
It is written to address 3 and address 4 respectively.

At time t11, a 4-burst-length write operation is started for the memory cells at addresses 1 to 4, and at time t12a, the contents of the U-side data strobe signal UDQS and the U-side input data UDQ for two cycles are obtained. 4
Bit data A1 to A4 are input. Time t
L-side data strobe signal LD for two cycles in 12b
4 bi as the contents of the QS and the L side input data LDQ
Data t1 to B4 for t are input. By operating two of the write buffer 4, the read amplifier 5, the memory cell plate 6, and the data latch 7 simultaneously, two input systems (U side and L side) are processed in parallel.

A latch signal USC synchronized with the rise and fall of the U-side data strobe signal UDQS is supplied to the U-side data latch 7, and the L-side data strobe signal LD
L side latch signal LS synchronized with the rise and fall of QS
C is supplied to the L-side data latch 7.

A data strobe signal selection circuit (not shown) detects a clock signal phase difference time Td between all data strobe signals and the system clock, and selects a data strobe signal having the longest clock signal phase difference time Td. Then, a timing signal SD synchronized with the falling edge of the data strobe signal is supplied to the write timing generator 3.

The U-side and L-side data latches 7 further convert the contents of the U-side and L-side internal data R into U-side and L-side internal data 2R so that the U-side internal data and the L-side internal data can be processed in parallel. Latch late. This allows U
From the rising time of the side latch signal USC to the L side latch signal L
Since the time up to the rise time of the SC has a time corresponding to at most a half cycle of the clock signal, the data latched at the former time is delayed in time, and the data latched at the latter time is temporally delayed. Approaching. All data latches 7 re-latch all internal data in synchronization with the falling edge of the data strobe signal selected by the data strobe signal selection circuit, thereby further ensuring the write operation of the DDR-SDRAM. You can also.

The U-side data latch 7 outputs a U-side latch signal U
The data A1 is latched as the U-side internal data R at the rise of the first signal pulse P1 of the SC, and the U-side latch signal USC
At the falling edge of the first signal pulse P1 of the U-side internal data 2R
And the data A1 is latched as
To latch the data A2. At the rising edge of the second signal pulse P2 of the U-side latch signal USC, the data A3 is latched as U-side internal data R, and the U-side latch signal USC is latched.
At the falling edge of the second signal pulse P2 of C, the U-side internal data 2
The data A3 is latched as R, and the data A4 is latched as U-side internal data F.
And F to the write buffer 4.

The L-side data latch 7 outputs the L-side latch signal L
At the rising edge of the first signal pulse P1 of SC, data B1 is latched as L-side internal data R, and L-side latch signal LSC
L-side internal data 2R at the falling edge of the first signal pulse P1.
, The data B1 is latched, and the L-side internal data F
To latch the data B2. Further, at the rising edge of the second signal pulse P2 of the L-side latch signal LSC, data B3 is latched as L-side internal data R, and the L-side latch signal LS
At the falling edge of the second signal pulse P2 of C, the L-side internal data 2
The data B3 is latched as R, and the data B4 is latched as L internal data F, so that the L internal data 2R
And F to the write buffer 4.

The write buffer 4 applies the first signal pulse P1 of the write signal SE to the memory cell at the address 1 on the U side and L side, and the I / O line R on the U side and L side of the I / O line 9 , And outputs data A2 and B2 to the memory cell at address 2 on the U side and L side via the I / O line F on the U side and L side of the I / O line 9. And U
Writing is performed on the memory cell plate 6 on the L side and the L side.

The second signal pulse P2 of the write signal SE causes the memory cells at address 3 on the U and L sides to receive the I
Data A via the I / O line R on the U side and L side of the / O line 9
3 and B3 are output, and I /
The data A4 via the I / O line F on the U side and the L side of the O line 9
And B4 are output to write data to the U-side and L-side memory cell plates 6, respectively.

According to the above embodiment, a plurality of input systems including the data strobe signal DQS and the corresponding input data DQ are processed in parallel, so that the data processing capability is improved. In addition, since the write operation is started in synchronization with the data strobe signal having the slowest phase difference, the usable balance time is extended, so that the read operation following the write operation is reliably performed.

As a modification of the above embodiment, all data strobe signals and input data can be simultaneously input to a plurality of input systems. In this case, the data strobe signal selection circuit is omitted.

In the DDR-SDRAM of the above embodiment, when a precharge operation command is requested during a write operation, the potential of the word line drops after a certain period of time,
The writing to the memory cell is completed, the bit lines are balanced, and a command request for the next active operation (write or read) is prepared. Here, since the write operation is completed quickly and the usable balance time is long, the time TRP from the command request of the precharge operation to the command request of the next active operation can be reduced.

As described above, the present invention has been described based on the preferred embodiment. However, the synchronous DRAM of the present invention is not limited to the configuration of the above-described embodiment, and is not limited to the configuration of the above-described embodiment. Synchronous D with various modifications and changes from
A RAM is also included in the scope of the present invention.

[0052]

As described above, the synchronous type D of the present invention is used.
In the RAM, writing to a memory cell by a write operation starts in synchronization with the data strobe signal DQS.
Since the usable balance time is longer than when the operation is started in synchronization with the system clock CLK, the read operation following the write operation is ensured.

If the clock signal phase difference time Td of the data strobe signal having the slowest phase difference is reduced, the usable balance time becomes longer.

[Brief description of the drawings]

FIG. 1 is a DDR-SDRAM according to a first embodiment of the present invention;
FIG. 3 is a block diagram showing a signal flow at the time of a write operation.

FIG. 2 is a timing chart of write and read operations of the DDR-SDRAM of FIG. 1;

FIG. 3 is a detailed timing chart of a write operation of the DDR-SDRAM of FIG. 1;

FIG. 4 is a DDR-SDRAM according to a second embodiment of the present invention;
5 is a detailed timing chart of the write operation of FIG.

FIG. 5 is a block diagram showing a signal flow during a write operation of a conventional DDR-SDRAM.

FIG. 6 is a timing chart at the time of write and read operations of the DDR-SDRAM of FIG. 5;

[Explanation of symbols]

 Reference Signs List 1 input buffer 2 command decoder 3 write timing generator 4 write buffer 5 read amplifier 6 memory cell plate 7 data latch 8 system synchronization latch 9 I / O line SA synchronization signal SB decode signal SC latch signal SD timing signal SE write signal CLK System clock DQS, UDQS, LDQS Data strobe signal DQ, UDQ, LDQ Input data DI Internal data Tck Clock signal period Td Clock signal phase difference time

Claims (5)

[Claims] 1. A synchronous DRAM that operates based on a system clock and a data strobe signal having a predetermined phase delay from the system clock, wherein the synchronous DRAM performs a read operation in synchronization with the system clock.
2. A synchronous DRAM according to claim 1, wherein a write operation for writing input data input to a memory cell based on a data strobe signal is executed based on said data strobe signal. 2. The synchronous DRAM according to claim 1, wherein said predetermined phase delay is between 75% and 125% of a cycle of said system clock. 3. A plurality of data strobe signals and input data corresponding to the data strobe signal in synchronization with the data strobe signal are input, and each of the input data is written to a memory cell via a corresponding I / O line. Item 3. The synchronous DRAM according to item 1 or 2. 4. The synchronous DRAM according to claim 3, wherein said plurality of data strobe signals are synchronized with each other. 5. The synchronous DRAM according to claim 3, wherein said plurality of data strobe signals have a phase difference with each other, and said write operation is started in synchronization with a data strobe signal having the most delayed phase.