JP2001236220A5 - - Google Patents
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- JP2001236220A5 JP2001236220A5 JP2001041237A JP2001041237A JP2001236220A5 JP 2001236220 A5 JP2001236220 A5 JP 2001236220A5 JP 2001041237 A JP2001041237 A JP 2001041237A JP 2001041237 A JP2001041237 A JP 2001041237A JP 2001236220 A5 JP2001236220 A5 JP 2001236220A5
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- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/506972 | 2000-02-18 | ||
| US09/506,972 US6647487B1 (en) | 2000-02-18 | 2000-02-18 | Apparatus and method for shift register rate control of microprocessor instruction prefetches |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2001236220A JP2001236220A (ja) | 2001-08-31 |
| JP2001236220A5 true JP2001236220A5 (enExample) | 2006-11-24 |
| JP4195778B2 JP4195778B2 (ja) | 2008-12-10 |
Family
ID=24016755
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001041237A Expired - Fee Related JP4195778B2 (ja) | 2000-02-18 | 2001-02-19 | マイクロプロセッサの命令プリフェッチ量制御のための装置および方法 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US6647487B1 (enExample) |
| JP (1) | JP4195778B2 (enExample) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6973542B1 (en) * | 2000-07-18 | 2005-12-06 | International Business Machines Corporation | Detecting when to prefetch inodes and then prefetching inodes in parallel |
| CN100353346C (zh) * | 2002-09-20 | 2007-12-05 | 联发科技股份有限公司 | 嵌入式系统及其指令预取装置和方法 |
| JP2004192021A (ja) * | 2002-12-06 | 2004-07-08 | Renesas Technology Corp | マイクロプロセッサ |
| US7337483B2 (en) * | 2004-01-23 | 2008-03-04 | Allen Medical Systems, Inc. | Surgical positioning apparatus |
| US7707359B2 (en) * | 2005-12-09 | 2010-04-27 | Oracle America, Inc. | Method and apparatus for selectively prefetching based on resource availability |
| KR101360221B1 (ko) * | 2007-09-13 | 2014-02-10 | 삼성전자주식회사 | 인스트럭션 캐시 관리 방법 및 그 방법을 이용하는프로세서 |
| US10528352B2 (en) | 2016-03-08 | 2020-01-07 | International Business Machines Corporation | Blocking instruction fetching in a computer processor |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5473756A (en) * | 1992-12-30 | 1995-12-05 | Intel Corporation | FIFO buffer with full/empty detection by comparing respective registers in read and write circular shift registers |
| JP2621772B2 (ja) * | 1993-10-29 | 1997-06-18 | 日本電気株式会社 | シリアル伝送装置 |
| US5819079A (en) * | 1995-09-11 | 1998-10-06 | Intel Corporation | Instruction fetch on demand for uncacheable memory which avoids memory mapped I/O side effects in a processor with speculative instruction fetch |
| US5987539A (en) * | 1996-06-05 | 1999-11-16 | Compaq Computer Corporation | Method and apparatus for flushing a bridge device read buffer |
| US5809566A (en) * | 1996-08-14 | 1998-09-15 | International Business Machines Corporation | Automatic cache prefetch timing with dynamic trigger migration |
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2000
- 2000-02-18 US US09/506,972 patent/US6647487B1/en not_active Expired - Lifetime
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2001
- 2001-02-19 JP JP2001041237A patent/JP4195778B2/ja not_active Expired - Fee Related