JP2001236045A - Display device and electronic equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the display quality of a display device in which a multi-line driving method is adopted from being lowered by preventing the generation of a crosstalk phenomenon in a period which does not contribute to a picture display. SOLUTION: A display-off(DSP-OFF) signal is made to be inputted to a decoder 258 and a voltage-off circuit 266 is provided in the decoder 258 in order to make voltages to be applied to data lines constant in a flyback period. Then, voltages to be suppied to respective data lines are made to be fixed by the voltage-off circuit 266 in the period which does not contribute to the picture display. Thus, the crosstalk can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device and an electronic apparatus, and more particularly, to a so-called multi-line which simultaneously selects and displays h (h is an integer of 2 or more) scanning lines out of scanning lines. The present invention relates to a display device and an electronic device using a driving method.

[0002]

2. Description of the Related Art A simple matrix type liquid crystal display device is widely used for a monitor of a portable personal computer because it does not require an expensive switching element on a substrate and is inexpensive as compared with an active matrix type liquid crystal display device. ing.

A so-called multi-line driving method has been proposed for the purpose of lowering the driving voltage of such a simple matrix type liquid crystal display device and further improving its display quality.

[0004]

Documents relating to the multi-line driving method include the following, for example.

[0005] "A GENERALIZED ADD"
RESSING TECHNIQUE FOR RMS
RESPONDING MATRIX LCDS, 1
988 INTERNAL DISPLAY
RESEARCH CONFERENCE P80 ~
P85 "" Japanese Patent Publication, 1993-46127 "" Japanese Patent Publication, 1993-10642 "" Japan Patent Publication, 6-4049 " Conducted various studies on the data line drive circuit, scan line drive circuit, and related circuits of a liquid crystal display device employing a multi-line drive method, and as a result,
The problem of the conventional circuit became clear.

[0006] The present invention has been made based on the results of the above-mentioned study by the present inventors.

An object of the present invention is to prevent the occurrence of a crosstalk phenomenon during a period that does not contribute to image display, and to prevent the display quality of a display device employing a multi-line driving method from deteriorating.

[0008]

In the display device of the present invention employing the multi-line driving method, preferably, the frame memory, which is one of the components of the data line driving circuit, includes at least the first RAM and the second RAM. In a certain frame period, the first RAM is used for reading data and the second RAM is used for writing data. In the next frame, reading and writing are reversed, and reading is performed every frame. The memory and the write memory are alternately used.

Thus, when determining the voltage to be supplied to the data line, image data belonging to different frame periods are not mixed, and accurate display is realized.

In an embodiment using only one frame memory, preferably, a number of image data corresponding to the number of simultaneously driven scanning lines are simultaneously written into the frame memory.

[0011] This prevents image data belonging to different frame periods from being mixed into a part of a plurality of image data necessary for determining a voltage to be supplied to the data line. An unnecessary streak-like pattern is prevented from being formed in the portion, and a decrease in image quality can be prevented.

With the above configuration, a display device employing a multi-line driving method capable of performing natural display with less distortion is realized.

In the display device of the present invention employing the multi-line driving method, preferably, a decoder for performing a process for determining a voltage to be supplied to the data line is constituted by a ROM.

As a result, the configuration of the decoder can be simplified, and when an IC is used, the chip area can be significantly reduced.

In the display device of the present invention employing the multi-line driving method, preferably, a circuit for fixing the voltage supplied to the data line during a period not contributing to image display is provided. The “period not contributing to image display” is a retrace period, a touch position detection period on the touch panel, or the like.

As a result, it is possible to prevent the occurrence of a crosstalk phenomenon in a period not contributing to image display, and to prevent a decrease in display quality of a display device employing a multi-line driving method.

In the display device of the present invention employing the multi-line driving method, preferably, in the scanning line driving circuit, data necessary for selecting a scanning line and a voltage supplied to the scanning line are determined. And separates the data required for processing.

As a result, the number of stages of the shift register can be greatly reduced. That is, when the number of scanning lines driven at the same time is “h” and the total number of scanning lines is “n”, the required number of shift register stages is “n / h”. Thereby, the simplification of the configuration of the scanning line driving circuit of the display device employing the multi-line driving method is achieved.

Further, in the display device of the present invention employing the multi-line driving method, when a scanning voltage pattern (also referred to as a selection voltage pattern) is periodically changed within one frame period, a scanning line driving circuit and a data line driving circuit are used. The circuit mutually exchanges information regarding the scanning voltage pattern.

Thus, it is only necessary to input information on the scanning voltage pattern to either the scanning line driving circuit or the data line driving circuit, and the display device can be easily controlled.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the present invention, a circuit configuration is devised by focusing on the features of a multi-line driving method (hereinafter, referred to as an MLS driving method). For an understanding of the invention, M
Since it is important to know the contents of the LS driving method,
An outline of the MLS driving method will be described.

A. Advantages of MLS drive method The MLS drive method is based on STN (Super Twisted).
This is a technique for simultaneously selecting a plurality of scanning lines in a simple matrix type liquid crystal panel such as a liquid crystal panel.

Thus, the driving voltage of the scanning line can be reduced.

Further, as shown in the upper part of FIG. 54, in the conventional line-sequential driving method, the interval between the selection pulses is wide, and the transmittance of the liquid crystal decreases with the passage of time. The brightness at the time decreases.
On the other hand, as shown in the lower part of FIG. 54, according to the MLS driving method, the interval between the selection pulses can be narrowed, so that the contrast and the luminance can be improved.

B. Principle of MLS drive method As shown in FIG. 55, a case is considered where two scanning lines X1 and X2 are simultaneously driven to turn on / off a pixel at a position where the scanning line and the data line Y1 intersect.

The ON pixel is set to "-1", and the OFF pixel is set to "+".
1 ". The data indicating this ON / OFF is stored in the frame memory. The selection pulse is represented by two values of "+1" and "-1". The data line Y
The drive voltage of 1 has three values of “−V2”, “+ V2”, and “V1”.

"-V2", "+ V
2 or V1 is determined by the product of the display data vector d and the selection matrix β.

In the case of FIG. 55A, d · β = −2, and in the case of FIG. 55B, d · β = + 2,
In the case of FIG. 55 (c), d · β = + 2, and FIG.
In the case of (d), d · β = 0.

When the product of the display data vector d and the selection matrix β is "-2", "-V2" is selected as the data line driving voltage, and when "+2", "+ V2" is selected. , “0”, “V1” is selected.

When the calculation of the product of the display data vector d and the selection matrix β is performed by an electronic circuit, a circuit for determining the number of mismatches between the corresponding data of the display data vector d and the selection matrix β may be provided. .

That is, when the number of mismatches is "2", "-V2" is selected as the data line drive voltage. When the number of mismatches is “0”, the data line driving voltage is “+ V
Select "2". When the number of mismatches is “1”,
“V1” is selected as the data line drive voltage. In the MLS drive for simultaneously selecting two lines, the data line drive voltage is determined as described above, and the selection of the pixel is performed twice within one frame period, thereby displaying the on / off state of the pixel.
For this reason, the driving voltage can be lowered, and the contrast and brightness are improved by providing a certain interval from the end of the first selection period to the start of the second selection period.

As described above, in order to realize the MLS driving, the data of the display image (that is, the display pattern) and the pattern of the selection pulse, that is, the scanning voltage pattern (the selection voltage pattern) may be provided for each selection period. ) Must be determined.

Since display image data is stored in the frame memory, it is important to access the frame memory effectively. Further, in order to make the liquid crystal panel larger, it is important to simplify the mismatch determination circuit. In addition, it is important to pay attention to the characteristics of the MLS drive to prevent the display quality from deteriorating. Further, it is important to simplify the configuration of the scanning line driving circuit while always maintaining the consistency between the data of the display image and the pattern of the selection pulse.

C. Specific Example of MLS Driving Hereinafter, the operation in the case where the four scanning lines are simultaneously selected to drive the simple matrix type liquid crystal display device will be specifically described with reference to FIGS. 53, 56, 57, and 58. .

In FIG. 53, scanning lines (X1 to Xn) and data lines (Y1 to Ym) are formed by transparent electrodes on two transparent glass substrates, and a liquid crystal is sandwiched between the two substrates. Have been.

The data lines are connected to a data line driving circuit (Y driver) 2100, and the scanning lines are connected to a scanning line driving circuit (X driver) 2200. In the drawings, for simplification of description, the data line driving circuit is described as “Y driver” and the scanning line driving circuit is described as “X driver”.

Pixels are formed at the intersections of the respective scanning lines and the respective data lines, and the display elements are driven by the scanning signals and the data signals supplied to the respective scanning lines and the respective data lines.

The scanning line driving circuit includes a controller (FIG. 53).
Not shown). Then, three (+ V1, 0, -V1) voltage levels are appropriately selected according to the scanning voltage pattern defined by the orthogonal function system selected in advance, and applied to the four scanning lines. I have. For example, four scanning lines X1 to X4 shown in FIG. 56A are simultaneously selected.

Further, the scanning pattern at this time is compared with a display pattern determined from data displayed on the pixels on the selected line, and the voltage levels (-V3, -V2, 0, + V2) determined by the number of mismatches are compared. , + V3) is applied to each data line from the data line driving circuit. Hereinafter, a procedure for determining the voltage level applied to the data line will be described.

The scanning voltage pattern is when the selection voltage is + V1 (+), when the selection voltage is -V1 (-), and when the display pattern is ON display data (+) and OFF display data (+). −). In the non-selection period, the number of mismatches is not considered.

In FIG. 56, the period required to display one screen is one frame period (F), and all the scanning lines are set to one frame period (F).
The period required for selecting one scan line is defined as one field period (f), and the period required for selecting one scan line is defined as one selection period (H).

Here, “H _1st ” in FIG. 56 is the first selection period, and “H _2nd ” is the second selection period.

Also, f _1st is the first field period, and f _2nd is the second field period. Also, F
_1st is the first frame period, and F _2nd is the second frame period.

In the case of FIG. 56, the first field period f
The first selection period in _1st (H _1st) 4 chosen in
The scanning pattern of the lines (X1 to X4) is set in advance in FIG.
6 (a), it is always (++-+) regardless of the state of the display screen.

Here, considering the case of performing full-screen display, (pixel (X1, Y1), pixel (X2, Y1), pixel (X
The display pattern in the first column corresponding to (3, Y1) and the pixel (X4, Y1)) is (++++). When the two patterns are compared in order, the first, second, and fourth polarities match, and the third pattern differs. That is, the number of mismatches is “1”. If the number of mismatches is “1”, 5 levels (+
(V3, + V2, 0, -V2, -V3) -V2 is selected from a certain voltage level. Thus, in the case of the scanning lines X1, X2 and X4 for which + V1 is selected, the voltage applied to the liquid crystal element is increased by the selection of -V2, while the case of the scanning line X3 for which -V1 is selected. In this case, the voltage applied to the liquid crystal element is reduced by selecting -V2.

The voltage applied to the data lines in this manner corresponds to the "vector weight" at the time of the orthogonal transformation, and a true display pattern is reproduced when all the weights are added to the four scanning patterns. Voltage levels are set so that

Similarly, when the number of mismatches is "0", -V
3, 0 level when the number of mismatches is "2", + V2 when the number of mismatches is "3", and + V3 when the number of mismatches is "4"
Select V2 and V3 have a voltage ratio (V2: V3 = 1: 1).
2).

In the same manner, for the four scanning lines X1 to X4, the number of data line mismatches from Y2 to Ym is determined, and the obtained data of the selected voltage is transferred to the data line driving circuit. During the first selection period, the voltage determined by the above procedure is applied.

Similarly, when the above procedure is repeated for all the scanning lines (X1 to Xn), the operation in the first field period (f _1st ) is completed.

Similarly, for the second and subsequent field periods, when the above procedure is repeated for all the scanning lines, 1
One frame (F _1st ) is completed, and one screen is displayed.

When the voltage waveform applied to the data line (Y1) when the entire surface is turned on is obtained in accordance with the above procedure, it becomes as shown in FIG. 56 (b), and the voltage waveform applied to the pixel (X1, Y1) is obtained. Is as shown in FIG. 56 (c).

Here, when the above procedure is performed, all data to be displayed on the screen (all data for one frame period) is required to determine all the numbers of mismatches in one field period.

In the case of driving for simultaneous selection of four lines as shown in FIG. 56, all data for one frame period is required for each field period. That is, it is necessary to read all the image data from the frame memory a total of four times during one frame period.

In the case of simultaneous selection of eight lines, all data for one frame period is required for every one field period.
During one frame period, it is necessary to read all image data from the frame memory eight times in total. In the case of simultaneous selection of 16 lines, it is necessary to read all image data from the frame memory a total of 16 times during one frame period. In the case of simultaneous selection of 32 lines, it is necessary to read all image data from the frame memory a total of 32 times during one frame period.

In order to maintain orthogonality, in the case of simultaneous selection of three lines, all data for one frame period (a total of four times) is required for each field period. In the case of simultaneous selection of 5 to 7 lines, All data for one frame period (a total of eight times) is required for each field period, and in the case of simultaneous selection of 9 to 15 lines, all data for one frame period (a total of 16 times) for each field period ) Is required, and in the case of simultaneous selection of 17 to 31 lines, all data for one frame period (32 times in total) is required for each field period.

The above is a description of a specific example of the MLS driving method.

D. Features of Preferred Embodiments of the Present Invention Next, features of preferred embodiments of the present invention will be outlined with reference to FIG.

One preferred embodiment of the present invention (Embodiments 1 and 2) relates to control of data input to a frame memory as shown in FIG. A plurality of frame memories 252 are provided to switch input / output for each frame, or when one frame memory is used, a plurality of data are written simultaneously.

In one preferred embodiment of the present invention (Embodiment 3), as shown in FIG. 1 (2), the mismatch determination circuit in the decoder 258 is constituted by a ROM 262.

In one preferred embodiment (Embodiment 4) of the present invention, as shown in FIG. 1C, when the retrace period is detected by the retrace period detecting circuit 272, The voltage applied to the data lines of panel 2250 is fixed.

In one preferred embodiment (Embodiment 5) of the present invention, as shown in FIG. 1 (4), a scanning line driving circuit (X driver) 2200 selects a scanning line. And the data required to determine the voltage to be supplied to the scanning lines are processed separately, thereby simplifying the configuration of the scanning line driving circuit.

In one preferred embodiment (Embodiment 6) of the present invention, the scanning voltage pattern is devised to prevent flicker and the like, and as shown in FIG. The scan voltage pattern is changed while transmitting the scan pattern information between the circuit (X driver) 2200 and the data line drive circuit (Y driver) to prevent crosstalk and the like.

Hereinafter, embodiments of the present invention will be described.

(Embodiment 1) This embodiment relates to the frame memory 252 shown in FIG.

(A) Description of Data Transfer FIG. 57 is a diagram showing a timing chart for one frame period. In the figure, “YD” is a frame signal indicating the start of one frame period, and “LP” is a selection signal indicating the start of one selection period.

The upper part of FIG. 57 shows the write timing of the write data (DATA (LINE)) in line units, and the lower part of FIG. 57 shows the read data of the read data (DATA_O (LINE)) in line units. It is shown.

FIG. 58 is a diagram showing the transfer timing of data in dot units during one selection period, and shows the operation within one selection period in FIG. 57 in detail. "L" in FIG.
The "P" signal is the same as the "LP" signal in FIG.
As is clear from FIG. 58, display data (m pieces) for one scanning line is transferred in one selection period. Therefore,
One screen of display data (n × m) is transferred in one frame period.

As is apparent from FIG. 57, when four scanning lines are driven simultaneously, the ratio between the data input speed and the data output speed is 1: 4.

(B) Problems identified by the present inventor First problem In the conventional multiplex driving method, one scanning line is selected only once during one frame period. It was sufficient to perform normal read / write to the frame memory.

However, in the case of the MLS drive, the number of scanning lines selected at the same time is 2, 3, 4, 5, 6, 7,
In the case of eight lines, the number of times of reading all data in one frame period is 2, 4, 4, 8, 8, 8,
8 times. Further, the number of scanning lines is 2, 3, 4, 5,
When the number of lines is 6, 7, 7, and 8, the speed ratio between input and output is 1: 1, 1: 1.3, 1: 1, 1: 1.16, respectively.
1: 1.13, 1: 1.11, 1: 1.

Therefore, if input and output are simultaneously performed on one frame memory, two
.. While reading all data four times, four times, four times, eight times..., The next data is written one after another, and new and old data are mixed. And as a result, twice, 4
.., 4 times, 8 times,..., The contents of the read data are different for each read.

Second Problem As described with reference to FIG. 55, when h scanning lines are selected simultaneously, two, four, four, eight, eight, eight, eight
, 16... Image data must be read from the frame memory at the same time to detect a mismatch with the selected pattern. In this case, if new and old data are mixed in simultaneously read data, an erroneous mismatch determination is made. As a result, for example, a local linear meaningless pattern appears on the display image, and The quality is significantly reduced.

This situation is shown in FIGS. 4B and 7.

FIG. 4B shows that four scanning lines are selected at the same time,
The read / write state for one frame memory when the total number of scanning lines n = 240 is shown.

As shown in FIG. 4A, the inside of one frame memory is made to correspond to 80 scanning lines, and
Think separately from part c. As shown in FIG. 4B, the first field period (f) in the first frame period (F _1st )
_{In 1st} ), only data belonging to the immediately preceding frame period (old data, which is indicated as “0” in the lowermost column of FIG. 4B) is read. In the second field period (f _2nd ), the read data corresponding to the portion a of the frame memory is data newly written in the current frame period (new data, and “1” is shown in the lowermost column of FIG. 4B). Is displayed). As a result, new and old data are mixed.

The relationship between the read address and the write address in the second field period (f _2nd ) is shown on the left side of FIG.

As shown on the left side of FIG. 7, the write address matches the read address for an address corresponding to 80 lines. This address corresponds to the point α in FIG. 4B.

77 lines, 78 lines, 79 lines, 8 lines
Four data corresponding to the 0 line are data necessary for the non-coincidence determination. In this case, as specified in FIG.
Data corresponding to lines 7, 78, and 79 is new data, and only data corresponding to line 80 is old data. In other words, new and old data are mixed in the data of 77 lines to 80 lines. As a result, the number of mismatches is not accurately determined, and the display is distorted.

That is, when the write address of the memory exceeds the read address, the set of the new data and the old data is read together, resulting in a meaningless display mode.

The overtaking of such an address is 160
This also occurs at line (β point in FIG. 4B) and 240 lines (γ point in FIG. 4B).

Generally, when data of the nth line is written and data of the n-3th line to the nth line are read, the data of the nth line is data belonging to the previous frame, and -1 line data is
This is the newly written data.

Such a problem has been clarified by the study of the present inventors.

(C) Contents of the present embodiment As shown in FIG. 5B, two frame memories 252a and 252b having a capacity of one frame are prepared, and the input switch 2600 and the output switch 2610 are set in opposite phases. ,
It is configured to switch every frame in the same cycle. That is, reading / writing of data in the double buffering format is performed.

With this configuration, when the number of mismatches is determined, display data of different frames is not mixed during the same frame period. Therefore, the number of mismatches can be determined, and the display can be accurately performed. As a result, a more natural display can be performed even in the case where the display is frequently switched. That is, the above-mentioned problem (1) is solved.

(Embodiment 2) (A) Features of this Embodiment Since the frame memory is expensive, it may be strongly desired to reduce the required capacity of the frame memory.

In this case, as shown in FIG. 5A, one frame memory 252 is used as in the prior art, and the data writing method is changed to solve the above-mentioned problem, that is, a plurality of data necessary for the discrimination of mismatch. Only the problem caused by mixing data belonging to different frame periods is solved.

In this case, although the above-described problem occurs, in the case of displaying a still image or a quasi-still image, data of consecutive frames is almost the same, so that an image can be temporarily formed. In the case of displaying a moving image, the response speed of the liquid crystal is 5
0 ms, and one frame period (16.6 ms)
ec), the minimum display is possible even if data belonging to new and old frames are mixed.

Using one frame memory as before,
In order to solve the above problem, a writing method as shown in FIG. 6B or the right side of FIG. 7 is adopted.

That is, as shown on the right side of FIG. 7, a plurality of data used for discrepancy determination are collectively written simultaneously. That is, as shown in FIG. 7, in the present embodiment, at time t8, 77 lines, 78 lines,
Four data corresponding to 9 lines and 80 lines are simultaneously written. Since the data is written at the same time, all of those data belong to the same frame period, and the mixing of old and new data is prevented. This can prevent a distorted display mode from occurring.

FIG. 6A shows a data writing method according to the prior art.

(B) Overall Configuration of the Liquid Crystal Display FIG. 2 shows the overall configuration of the liquid crystal display.

The DM in the module controller 2340
The A control circuit 2344 includes a microprocessor (MPU)
Upon receiving an instruction from the 2300, the video RAM (VRA)
M) 2320, read out one frame of image data via the system bus 2420, and send the image data (DATA) to the data line driving circuit together with the clock signal (XCLK).

The data line driving circuit (in FIG. 2, enclosed by a dashed line) includes a control circuit 2000, an input buffer 2011, a frame memory 252, an output shift register 2021, a decoder 258, and a voltage selector 2100. .

Reference numeral 2400 denotes an input touch sensor, and reference numeral 2410 denotes a touch sensor control circuit. The input touch sensor 2400 and the touch sensor control circuit 2410 may be deleted when unnecessary.

In addition to the system configuration shown in FIG.
A, the configuration of FIG. 3B can also be adopted. In the case of FIG. 3A,
Control circuit 2000, input buffer 2011, frame memory 252, output shift register 2021, decoder 2
58 is built in the MLS decoder 2500. In the case of FIG. 3B, only the decoder 258 is built in the MLS decoder 2500, and the control circuit 2000, the input buffer 2011, the frame memory 252, and the output shift register 2021 are built in the memory circuit 2510.

(C) Specific Circuit Configuration FIG. 8 shows a specific configuration of the input buffer circuit 2011 and the frame memory 252 shown in FIG. 9 and 10 are timing charts showing the operation of the input buffer circuit 2011.

The control circuit 2000 shown in FIG.
The control signals CLK1 to CLKm and LP1 to LP4 are generated based on the clock signal sent from the A control circuit 2344, and the image data for four lines is input to the input buffer circuit 20.
11 is stored.

As shown in FIG. 8, the input buffer circuit 2011 includes D flip-flops (DFF) DF1 to DFm for storing input data for one line and B1 to B4m of DFF for storing display data for four lines. It is configured.

As shown in FIGS. 9 and 10, during the first selection period (H _1st ), when CLK1 is input to DF1, the data (D1) displayed at the pixel at the intersection of X1 and Y1 of the display data is displayed.
OT1) is stored in DF1. Similarly, when CLK2 is input to DF2, data (DOT2) displayed at the pixel at the intersection of X1 and Y2 is stored in DF2, and when CLKm is input to DFm, the pixel at the intersection of X1 and Ym is displayed. (DOTm) is stored in DFm.

The data (LIN) stored in DF1 to DFm
E1) is B1, B5, B9,..., B4m according to the LP1 signal.
Moved to -3.

In H _{2nd in} the next (second) selection period, the data (LINE2) displayed at the pixel at the intersection of X2 and Y1 to Ym is changed by CLK1 to CLKm by the same operation.
Stored in DF1 to DFm. The data stored in DF1 to DFm are converted into B2, B6, B10,.
Moved to m-2.

H _3rd of the next (third) selection period is
In a similar operation, data (LINE3) displayed at the pixel at the intersection of X3 and Y1 to Ym is stored in DF1 to DFm according to CLK1 to CLKm. The data stored in DF1 to DFm are converted into B3, B7, B11,
…, Moved to B4m-1.

In the last (fourth) selection period, H _4th , by the same operation, data (LINE 4) displayed at the pixel at the intersection of X 4 and Y 1 to Ym is stored in DF 1 to DFm by CLK 1 to CLKm. Can be The image data stored in DF1 to DFm is converted to B4, B8, B1 by the LP4 signal.
2, ..., moved to B4m.

After the image data of the first four lines (X1 to X4) are stored in the input buffer circuit 2011 and before the next field period, the control circuit 2000 controls the word line WL1 of the data storage means 19 by the control circuit 2000. Is selected, and the data is stored in the RAM connected to WL1 and BL1 to BL4m in FIG. Next 4 lines (X5 ~
The same applies to data after X8).

The frame memory 252 is a normal CMOS
It is composed of SRAM made by the process.

That is, the frame memory 252 has 4 m bit lines (BL) and word lines (WL).
Has n / 4 lines (integer). The capacity of the RAM is 4m × (n / 4) = m × n (the number of data lines × the number of scanning lines), and has a capacity for one frame.
8, the symbol “C” in the frame memory 252 represents a memory cell. In addition, instead of SRAM, DRA
M, a high-resistance RAM, or a storage element having a function of temporarily storing data may be used.

Data is read by the control circuit 2000 in word line (WL) units and output to the output shift register 2021. Therefore, data for four consecutive lines in the same frame period is output at a time.

The output shift register 2021 outputs to the decoder 258 the data of four pixels necessary for the discrimination of a mismatch.

As described with reference to FIG. 55, the decoder 258 compares the scanning pattern with the image data, detects the number of mismatches, and sends a signal for determining the data line driving voltage to the voltage selector 2100. The voltage selector 2100 selects a voltage corresponding to the transmitted signal and applies the voltage to the data line. FIG. 56 shows an example of the data line drive voltage waveform.
(B).

The scanning line driving circuit 2200 forms the scanning voltage waveform shown in FIG.

As described above, in the case of simultaneous selection of 4 lines, if an input buffer circuit having a capacity of 1 line + 4 lines, that is, a total of 5 lines is provided, reading is performed at the conventional timing. Also, the data of the n line is
The data is written to the data storage means at the same timing as the data from the (n-3) th line to the (n-1) th line. Therefore, different frames of data are not mixed in the four lines selected at the same time. Further, the capacity of the frame memory is sufficient for one frame.

Although the above description has been made with reference to four lines, the present invention is not limited to this. Even in the case of simultaneous selection of 3, 5, 6, 7, and 8 lines, the display data capacity for one line is If a buffer having a capacity that is equal to the display data capacity of the selected line is added, data of different frames will not be mixed in the lines to be selected at the same time. Also, this buffer is useful for data unit processing for simultaneously selected lines even when converting to data of a mismatch number for selecting a voltage.

Although the description has been given of the example of the simple matrix type liquid crystal panel, the present invention is not limited to this, and can be applied to a display device using an MIM panel, an EL panel, or the like.

Hereinafter, a modification of the second embodiment will be described.

In the modification shown in FIG. 11, the input buffer circuit 2011 is constituted by a shift register having a capacity for storing data for the lines selected simultaneously.

FIG. 11 is a diagram showing a configuration example of the input buffer circuit 2011. The input buffer circuit 2011
It is composed of 4m DFFs from 1 to B4m (the number of simultaneously selected lines × the number of output data lines). This DF
F is a shift register that shifts from B1 to B4m, and the shift order is B1, B5, B9,..., B4m-3, B
2, B6, B10, ..., B4m-2, B3, B7, B11, ..., B4m
-1, B4, B8, B12, ..., B4m. B1 to B4
The output of m is the bit line BL1 of the data storage means of FIG.
It is connected to ~ BL4m.

The signal CLKs connected to the CLK terminal of the DFF is supplied to the control circuit 2000 by the control circuit 2000 in FIG.
K is obtained by masking only a certain portion of data and extracting and inverting K (see FIG. 12). At the timing shown in FIG. 12, when the DATA signal is input from B1, shifted by CLKs, and data for four lines is accumulated, it is transferred to the frame memory by the above-described operation.

In this modification, all DFFs are set to CLKs
Since the operation is performed synchronously, m DFFs (for one line) can be reduced, and cost reduction and space saving can be achieved.

Next, a modification shown in FIG. 13 will be described.

The modification shown in FIG. 13 is a D-type transparent latch (DT) for storing data for simultaneously selected lines.
L) and an AND gate to form an input buffer circuit 2011
Is characterized in that

When the latch enable (LE) terminal is High (active), the data connected to the D terminal is passed as it is, and when the latch enable (LE) terminal is Low (inactive), the D terminal (data) at the time of the falling edge of LE is used. Is an element also called a through latch, which holds the state immediately before.

The input buffer circuit shown in FIG.
Up to 4m (the number of simultaneously selected lines × the number of signal electrode outputs) DTL. Each one has an AND gate. Generally, the transparent latch DTL has a smaller circuit configuration than the DFF because the number of internal gates is smaller. Therefore, D
Even if an AND gate is added to the TL, the size is only equivalent to that of the DFF. Therefore, the size of the circuit is substantially the same as the configuration of FIG. 11, and the operation can be the same as that of the first embodiment.

FIGS. 14 and 15 are timing charts illustrating the accumulation operation of the input buffer circuit of FIG.

In FIG. 14, first selection period (H _1st )
In the example, only the LP1G signal is High (active). Only the CLK1 to CLKm input to the AND gates connected to LP1G in FIG. 13 are input to the latches B1, L5,..., Latch B4m-3.

That is, the first selection period (H _1st ) is X 1
(LINE) displayed on the pixel at the intersection of Y1 and Y1 to Ym.
1) are stored in the latches B1, L5,..., Latch B4m-3 according to CLK1 to CLKm.

In the next (second) selection period (H _2nd ),
Only the LP2G signal is High (active). Only CLK1 to CLKm input to the AND gate connected to the LP2G are latches B2, B6,.
Input to 4m-2. That is, in 2H, X2 and Y1 to Ym
Data (LINE2) displayed at the pixel at the intersection of
.., B4m-2 according to CLKm from LK1.

Similarly, the third selection period (H _3rd )
Then, the data (LINE3) displayed at the pixel at the intersection of X3 and Y1 to Ym is changed to B1 by CLK1 to CLKm.
3, B7, ..., B4m-1.

Similarly, the fourth selection period (H _4th )
In this case, the data (LINE4) displayed at the pixel at the intersection of X4 and Y1 to Ym is changed to B by CLK1 to CLKm.
4, B8, ..., B4m.

When data for four lines from X1 to X4 is stored, the data is transferred to the data storage means by the same operation as in the configuration of FIG. Similarly, the buffer operation for four scanning electrodes is repeated over one frame period.

Next, a modification shown in FIG. 16 will be described.

The modification shown in FIG. 16 is for inputting data in parallel. FIG. 17 is a timing chart showing the data accumulation operation.

Referring to FIG. 16, flip-flop DF1
And DF2 have a common clock CLK1
It is connected to the. The data terminal of DF1 is connected to DATA1, and the data terminal of DF2 is connected to DATA2. Thus, in the case of two parallel input signals, one clock is input to two DFFs, DATA1 is connected to DF (odd number) of DFF, and DF (even number) is connected to DFF. Is connected to DATA2. As shown in FIG. 12, when CLK1 is input, one dot and two dots of DATA, that is, the data displayed at the pixel at the intersection of X1 and Y1 and the data displayed at the pixel at the intersection of X1 and Y2 are DF1 And DF2. Similarly, scan line 1 is generated by CLK1 to CLK (m / 2).
Line data is accumulated.

As described above, by using the parallel input, the number of clocks can be reduced to half (m / 2) as compared with the case where the configuration shown in FIG. 11 for performing the serial input is employed. For this reason, buffer means with low power consumption can be configured.

Further, a modification as shown in FIG. 18 can be considered. In the examples described so far, there is no limit on the number of lines to be selected simultaneously. However, the present inventor has found that when data is transferred between the input buffer circuit and the frame memory, the controllability is significantly different depending on the number of simultaneously selected scanning lines. Then, in order to optimize the controllability, 2 ^k
It has been found that it is desirable to select (k is a natural number) lines simultaneously. FIG. 18 is an example of control timing when the number of simultaneously selected lines is 2 ^k lines.

For concrete consideration, consider the case where the total number of scanning lines is n = 240 when four lines are simultaneously selected. In this case, the required number of fields is four to ensure the orthogonality of the scanning pattern. Therefore, one field period is (240 /
4) = 60 selection periods, and one frame period is (60 ×
4) = 240 selection periods. This means that the total number of scanning lines n =
240, as shown in FIGS. 2, 3A, and 3B.
YD of input signal from MPU and general controller,
LP means that the CLK of the input signal can be used as it is for controlling the output signal.

Next, by simultaneously selecting three lines, the total number of scanning lines n =
Consider the case of 240. Also in this case, four fields are required to ensure orthogonality. Therefore, one field period is (240/3) = 80 selection periods, and one frame period is (80 × 4) = 320 selection periods. Therefore, one frame period is longer than in the case of simultaneous selection of four lines. This case is shown in FIG.

Even when the input is for 240 selection periods,
If the output is required for 320 selection periods, it is necessary to match these frame periods and make the frame frequency the same in order to prevent frame response and flicker. For this reason, it is necessary to make the selection period at the time of output shorter than the selection period at the time of input.

Therefore, the control circuit 20 has a VCO
It is necessary to provide a circuit such as a (voltage-controlled oscillator) or a PLL (phase-locked loop circuit) to generate an internal clock higher than the input signal CLK to eliminate the difference in the selection period.

In reading from the memory,
Since writing and reading operate without synchronization, control of data input to the data storage means becomes complicated. In order to realize asynchronous writing and reading, a simple one-port RAM cannot be used, and a two-port RAM that can perform writing and reading independently must be used. However, a two-port RAM is more expensive and has a larger area than a one-port RAM. As described above, when a number of lines other than the four lines (for example, 3, 5,...) Are simultaneously selected, the input signal cannot be used for output control as it is.
The control circuit 2000 becomes expensive.

However, 2, 8, 16, 32, 64
For example, when the number of 2 ^k (k is a natural number) lines is selected at the same time, the timing of the input selection period can be used as it is for the output selection period, as in the case of simultaneously selecting four lines.

Here, if the response speed of the liquid crystal is slow, the change in luminance due to the frame response is not sharp. However, as the response speed increases, the change in luminance due to the frame response increases.
Therefore, when a liquid crystal having a high response speed is used, it is necessary to set the number of lines selected at the same time to a certain number.

However, if the simultaneous selection of about 4 to 8 lines or more is performed, the effect of this luminance change can be substantially suppressed. On the other hand, if too many lines are selected at the same time, the capacity of buffering increases, and the controllability of the output signal by the input signal also deteriorates.

Therefore, considering the degree of luminance change due to the frame response, the buffer capacity, the controllability of the output signal by the input signal, and the like, the best cost performance is obtained when four or eight lines are selected simultaneously.

Next, a third embodiment will be described.

Embodiment 3 (A) Description of Discrepancy Determination Circuit As described with reference to FIG. 55, in a matrix type display device using a driving method of simultaneously selecting a plurality of scanning lines, data lines are connected to data lines. In order to determine the voltage to be supplied, it is necessary to determine the number of mismatches between the image data and the scan pattern.

The mismatch determination circuit is provided in the decoder 258 shown in FIGS. FIG. 19 shows the internal configuration of the decoder 258.

The decoder 258 comprises latch circuits 261, 262
63, a mismatch determination circuit 262, and a state counter 265 for determining a scanning pattern from the FS signal and the YD signal.

According to the study of the present inventor, it has been found that the mismatch judgment circuit 262 can be constituted by the circuit shown in FIG. The circuit of FIG. 26, as shown on the right side of FIG.
This circuit performs an operation for selecting an appropriate potential from among five levels of data line drive voltages VY1, VY2, VY3, VY4, and VY5. That is, the number of mismatches between the scanning pattern and the display pattern is detected, and the number of mismatches is 0, 1, 2, 3, 4,
In this case, signals for selecting VY1, VY2, VY3, VY4, and VY5 are generated.

As shown in FIG. 27, the scanning line potentials are VX1 (11.30 V) and -VX1 (-11.30 V).
V) and 0V. FIGS. 28A and 28B show an example of a scanning pattern for four lines. As shown, the scanning pattern is represented by a matrix of 4 rows and 4 columns, where the rows indicate the line order of the scanning lines and the columns indicate the order of selection. The mismatch determination circuit 262 selects four lines four times,
The number of mismatches between the display pattern and the scanning pattern is determined four times,
Determine the voltage level of the data line.

(B) Problems identified by the inventor The circuit shown in FIG. 26 employs an exclusive OR (EX_OR) and an addition circuit (A
DDER) to determine the number of mismatches. In other words, the circuit of FIG. 26 uses four signals for detecting the number of mismatches.
It is composed of an EX_OR gate, six EX_OR gates used for the ADDER circuit, five AND gates, five three-input NAND gates, and three inverters.

However, this configuration has a problem that the circuit scale becomes large. For example, as is clear from FIG. 26, the wiring connecting the gates is considerably complicated, and the circuit becomes large because an adder (ADDER) circuit is required.

Further, as the number of simultaneously selected lines increases, the complexity increases. In particular, the circuit of the ADDER circuit increases in proportion to almost the square of the number of simultaneously selected scanning lines.

Such an increase in the circuit scale is caused by the configuration in which the mismatch determination circuit is built in the data line drive circuit (the configuration in FIG. 2).
This is a particularly serious problem when adopting the method.

(C) Features of this Embodiment In this embodiment, the mismatch detection circuit is constituted by a read-only memory (ROM).

(D) Specific contents of the present embodiment The following describes an example in which four lines are simultaneously selected.

FIG. 20 shows a system configuration. As shown in FIG. 29, the decoder 258 including the mismatch determination circuit 262 includes a frame memory 252 and a level shifter 259.
And is located between.

FIG. 21 is a block diagram showing a circuit configuration of a circuit for judging the number of inconsistencies per output which is incorporated in the data line driving circuit. The number-of-mismatch determination circuit includes a first ROM circuit 1, a second ROM circuit 2, a third ROM circuit 3,
ROM circuit 4, fifth ROM circuit 5, and precharge (PC) circuits 6 to 10. PC circuits 6, 7,
9 and 10 have the same configuration, but the PC circuit 8 has a slightly different configuration, and the number of input / output terminals is one.

The input signal to the number-of-mismatch determination circuit is a pattern identification signal F1 for distinguishing four scanning patterns,
F2 and the data signal da read from the frame memory
ta1 to data4, a precharge signal PC, and a signal FR for inverting display ON / OFF.

Each of these input signals, via an inverter, receives both the non-inverted signal and the inverted signal from the ROM1-5 circuits 1-5.
5 are commonly input. However, only the normal rotation signal is input to the FR terminal.

Output signals sw1 of PCs 1 to 5 and circuits 6 to 10
To sw5 are connected to the control terminal of the voltage selector 260 via the level shifter 259 in FIG. When any one of the output signals sw1 to sw5 is High, one of the corresponding voltage levels VY1 to VY5 is selected in the voltage selector and applied to the data line.

FIG. 22 is a diagram schematically showing the ROM 5 circuit 5 of FIG. 21, and N-channel transistors (hereinafter, Nch-Tr) are indicated by white circles (○).

On the left side of FIG. 22, as shown in correspondence with a normal CMOS transistor symbol, the gate is described as (a, c), the drain is described as (b),
The source is described as (d), and the substrate (Vss =
GND).

The ROM circuits are all Nch-Tr
The logic is composed of This means that although a logical configuration of only a P-channel transistor (hereinafter Pch-Tr) is possible, when realizing the same transistor driving capability, N
This is because the mobility of the channel transistor is about three times the mobility of the P-channel transistor, and therefore, when transistors having the same capacity are to be formed, the mobility of the N-channel transistor can be reduced to 1/3 or less.

In FIG. 22, Nch • Tr driven by the XPC signal (which is an inverted signal of PC) has Vdd (5 V) and Vss (GND) during precharge.
This prevents a short circuit with the potential.

Next, the process of generating an output signal by a decoding operation from an input signal will be described.

The output line (vertical line) of the non-coincidence judging circuit is high in advance due to precharge (PC signal). According to the input signal input from the input line (horizontal line), all Nc connected in series to one vertical line
When h · Tr is turned on, the potential of the vertical line becomes Vss, and the output changes to Low.

For example, it is assumed that the pattern shown in FIG. 28A is employed as a scanning pattern.

When XPC is High, data 1 to data
If all of a4 are High, all the Nch-Trs in the first column of the ROM 5 circuit are turned on, and are connected to Vss.
Is output. The other columns include Nch Trs that are not turned on, do not connect to Vss, and remain High.

As described above, the output can be selected depending on where the Nch Tr is placed. That is, Nc
Depending on the arrangement of h · Tr, it is possible to decode an input signal and convert it to selection voltage data.

Here, the ROM circuit 5 is a ROM that handles only the case where the number of mismatches between the scanning pattern and the display data is 4, that is, all are different. Therefore, even if a different scanning pattern is applied four times, the total number of outputs is only four. For this reason, a four-column configuration is sufficient for the ROM circuit 5.

Similarly, the configuration of other ROM circuits is determined according to the number of output cases. For example, the ROM circuit 1, R
The OM circuit 2, the ROM circuit 3, and the ROM circuit 4 are 4,
A configuration of 9, 16, and 9 columns may be used.

When the scanning voltage pattern is changed from FIG. 28A to FIG. 28B, for example, Nc
The arrangement of h · Tr may be changed. Such an arrangement change can be easily performed by changing a mask for manufacturing a ROM.

FIG. 23 is a diagram showing an internal circuit configuration of PC circuit 10 of FIG. The configuration is such that the input / output terminals IN1 and IN2 can be selected by the inverter 303 connected to the FR signal and the two Nch Trs 301 and 302.

When the FR signal is high, the signal input to the terminal IN1 is selected. When the FR signal is low, the signal input to the terminal IN1 is selected.
The signal input to N2 is selected.

The Pch Tr 304 receives the PC signal,
RO connected to terminal IN1 or terminal IN2
It functions to precharge the M circuit.

There are a Pch-Tr 305 and an inverter 306 for output. The Pch Tr 305 is provided for stabilizing the output.

Here, the PC circuit 8 in FIG. 21 only needs to select the voltage level VY3 (for example, ground), so that it is not necessary to select the input signal by the FR signal.
Therefore, Nch Trs 301 and 30 for input selection are selected.
2 and there is no Pch
It is configured to be directly connected to the source of Tr304.

FIG. 24 is a timing chart for explaining the operation of the number-of-mismatch determination circuit. From this figure,
Input signals data1 to data4, pattern identification signal P
D0, PD1, 1 selection period signal LP, precharge signal PC, inversion signal FR, frame memory W / R (Hig
The correlation between the respective signals (writing with h and reading with Low) is clarified.

The operation of the circuit will be described with reference to FIGS.

Description will be made with reference to the LP (one selection period) signal. After the fall of LP, there is a read period in which data for the simultaneously selected lines is read from the frame memory after a write period in which data is written in the frame memory. During this read period, the output data data1 to data4,
The FR signal and the PD0 and PD1 signals are determined. In order to erase and reset the data before the determination, the PC (precharge) signal becomes low at the timing of transition from before the determination to after the determination. According to the PC signal, the PC circuits 6 to 1
0 turns on Pch.Tr, and N in the ROM circuits 1 to 5
The channel Tr is precharged and raised to High (Vdd). Thereafter, data data1 to data
4 and the pattern identification signals PD0 and PD1
5, and as a result, a signal (sw1 to sw5) for selecting a voltage level to be applied to the data line is determined.

Here, in a conventional general ROM, a precharging Pch / Tr is required for every Nch / Tr column. However, RO used in the mismatch number determination circuit
In the M circuit, as described with reference to FIG. 22, the outputs of all columns cannot change at the same time. Therefore, only one Pch • Tr for precharging is required for each ROM circuit. That is, if there is one PC circuit in each ROM circuit, a sufficient precharge operation can be performed. Therefore, in the present invention, there is only one in the PC circuit. According to the present invention, the number of Pch transistors larger in area ratio than the Nch transistors is further reduced, and a smaller circuit can be realized.

As described above, the ROM circuit including only the Nch-Tr and the number of outputs can be reduced, and the PC circuit using one Pch-Tr for precharging, It has been confirmed that the area is 40% smaller than that of a circuit having a conventional gate configuration.

In the above description, simultaneous selection of four lines has been described. However, when the number of simultaneously selected lines increases or decreases, it can be handled by increasing or decreasing the number of rows and columns in the ROM circuit. When the simultaneous selection is four or more lines, the scanning pattern identification signals (PD0, PD
1) becomes very small. For example, in the case of 32 lines, conventionally, if the scanning pattern identification signal is 32 lines, only 5 lines are required. Therefore, the number of wirings is reduced.

Next, a modification of the third embodiment will be described with reference to FIG.

In the modification of FIG. 25, the precharge (PC) signal in the number-of-mismatch determination circuit shown in FIG. 21 is transmitted by a delay line (polysilicon line) to reduce power consumption. In response to the PC signal in FIG. 21, the Pch-Tr is turned on, and the drain of the Nch-Tr is charged up.
The data line driving circuit with a built-in RAM has the number of mismatch circuits for determining the number of outputs for driving the data lines. For this reason, Nch-Trs for the number of outputs are charged up at the same time by precharging, and a large current flows. However, by using a delay line for the data line that transmits this precharge signal to all of the mismatch determination circuits, a large inrush current flows by flowing current averagely during the delay time without charging up all at once. Thus, a data line driving circuit with lower power consumption can be realized.

That is, as shown in FIG. 25, the power consumption can be reduced by forming the signal lines 501 and 502 of the precharge signal with polysilicon. In addition, by using a delay line for the pre-charging wiring, the inrush current can be averaged, and a low power consumption mismatch number determination circuit can be obtained.

Next, a fourth embodiment will be described.

(Embodiment 4) (A) Features of this Embodiment In this embodiment, a voltage is turned off in the data line drive circuit so that all the voltage levels output to the data lines by the external input are the same. A circuit is provided.

A retrace period detection circuit is provided in the data line drive circuit, and all voltage levels output to the data lines are kept the same by the retrace period signal from the retrace period detection circuit or by an external input. It is characterized in that it can be made to be.

(B) Problems identified by the present inventor Even when the liquid crystal display device is in an operating state, there may be a period that is not necessary for display.

For example, a period corresponding to a blanking period of a CRT, a period between one frame period and the next frame period, a period between one field period and the next one field period, There is a period to take the interface. These periods are referred to as blank periods. Then, these periods may be appropriately referred to as a retrace period.

If the above-described decoder 258 is operated normally during this blanking period (blank period), various voltages are applied to the liquid crystal of the display panel during this period, causing crosstalk and the like, and Adversely affect

Hereinafter, a specific description will be given.

Normally, the number of selection period signals LP of the liquid crystal drive signal sent from the controller or the like in one frame is larger than the number of selection periods for performing actual display, as shown in FIG. In the drawing, as an example, a case is shown in which multi-line driving is performed in which a display panel having 240 scanning lines is simultaneously selected for four lines. By selecting 4 lines at the same time,
In order to display a display device of 240 scanning lines,
One full scan is completed in 240/4 = 60 selection periods. This is one field. In order to independently display all four lines of pixels, at least four fields are required. Therefore, for display, 60 × 4 fields = 24
0 selection period is required.

However, as shown in FIG. 40, the number of selection periods in one frame period is 245, which is larger than the selection period (240) required for display.

This is for the purpose of sharing the display control with another type of display device such as a CRT or the like, in the period (return period) for completing the scanning on the CRT and returning to the initial scanning line. This is because a corresponding period is added.

In the control for displaying, when adjusting the input / output of the display data with the CPU for generating the display data,
The number of selection periods may increase. The retrace period described above is a period that is not necessary for display on the panel. During this period, the voltage applied to the liquid crystal of the display panel has a bad influence on the display.

In the conventional MPX drive, if the potential of the scanning line in the flyback period is not selected, that is, if the potential of the scanning line is zero potential, the effective potential applied to the liquid crystal is maintained regardless of the potential of the data line VMY1 or VMY2. Since the voltages are the same, the contrast is reduced (the ON / OFF voltage ratio is reduced), but the display does not greatly differ depending on the selected potential.

However, when performing multi-line driving, M
As compared with the PX drive, the selection potential of the data line is higher and the number of potentials to select is larger. That is, if the number of scanning lines to be selected simultaneously is h (h is an integer), a voltage level of h + 1 is required on the data line side. Therefore, the display greatly differs depending on the potential selected by the data line during the flyback period.

For example, when a selection potential different from that of an adjacent data line is applied to a data line during a flyback period, it looks like crosstalk. Unlike the conventional MPX drive, even if the whole (2
The applicant has found that even a short period (5H) of 45H) clearly affects the display and has a problem that can be observed as crosstalk.

That is, in the conventional MPX driving, if the potential of the scanning line during the flyback period is not selected, that is, if the potential of the scanning line is zero potential, as shown in FIG. 39A, the potential of the data line is set to either VMY1 or VMY2. However, the effective voltage applied to the liquid crystal is the same. Therefore, although the contrast is reduced, the display does not greatly differ depending on the selected potential.

However, when performing multi-line driving,
As shown in FIG. 39B, the absolute value of the selection potential of the data line is larger than the MPX driving, and the number of potentials to be selected is larger. Therefore, the display greatly differs depending on the potential selected by the data line during the flyback period.

For example, when a selection potential different from that of an adjacent data line is applied to a data line during a flyback period, it looks like crosstalk. Unlike the conventional MPX drive, even if the whole (2
It was found that even a short period (5H) of 45H) clearly affected the display and could be observed as crosstalk.

(C) Contents of this Embodiment FIG. 29 shows the overall configuration of the data line drive circuit of this embodiment.

A feature of the configuration of FIG. 29 is that a display-off (DSP_OFF) signal is input to the decoder 258, and the voltage applied to the data line is kept constant during the retrace period. A voltage-off circuit 266 is provided in the decoder 258 to make the voltage applied to the data line constant.

First, display off (DSP_OF)
F) A case where a signal is directly input to the voltage-off circuit 266 without passing through a retrace period detection circuit will be described. In this case, the switch 8000 in FIG. 29 is switched to the (a) side. The module controller 2340 shown in FIG. 2 generates a display off (DSP_OFF) signal, and this display off (DSP_OFF)
The signal is directly input to the voltage-off circuit 266.

The configuration of the voltage off circuit will be described.

FIGS. 30A and 30B show examples of the circuit configuration of a voltage-off circuit corresponding to one output. If there are 160 outputs, 160 circuits of FIGS. 30A and 30B are arranged in parallel.

FIG. 30A shows a case where four lines are simultaneously selected.
OB indicates a voltage-off circuit for three lines simultaneously.

As shown in FIG. 30A, when four lines are selected simultaneously, the five-level potentials (VY1 to VY1 to
Signals sw1 to sw5 for selecting VY5) are output and input to the voltage-off circuit. That is, sw1, sw2, sw
4 and the signal of sw5 are AND gates 2700 and 271
0, 2730 and 2740, respectively. Also,
The SW3 signal is input to the OR gate 2720.

On the other hand, when the external signal DSP_OFF is AND
Gates 2700, 2710, 2730, and 2740 are commonly input. In addition, the OR gate 2720 includes a DSP
An inverted signal of the _OFF signal is input.

That is, if the DSP_OFF signal is High, the signals sw1 to sw5 are output as they are.
If the SP_OFF signal is Low, only the sw3 signal is H
It becomes igh. Therefore, the DSP_OFF signal is set to Low.
As a result, VY3 (see FIG. 39B) is applied to the data line by the voltage selector connected to sw3 that has become High.

In the case of simultaneous selection of four lines, Vx3, which is equal to the zero potential of the non-selection level of the scanning line, is applied to the data line during the retrace period, so that no voltage is applied to the liquid crystal and crosstalk can be prevented. .

In the case of an even number of simultaneously selected lines such as four lines, the same potential as the non-selection level on the scanning line side can be selected on the data line side, and this potential can be selected by the data line during the retrace period. desirable. However, in the case of an odd number of lines such as simultaneous selection of 3, 5, and 7 lines, the same potential level as the non-selection level of the scanning line is not present in the voltage level of the normal data line. The following two methods are available as countermeasures in this case.

1) The non-selection level on the scanning side is input to the data line driving circuit, and the data line selects the non-selection level during the flyback period.

2) The data line selects the potential level closest to the non-selection level on the scanning side during the retrace period.

To realize the method 1) by simultaneous selection of three lines, the sw3 of the circuit for selecting four lines shown in FIG.
The signal (selection signal corresponding to VY3) may be set to High, the data line drive potentials VY1 and VY2 may be changed to voltages for three lines, and VY4 and VY5 may be changed to VY3 and VY4 for three lines.

On the other hand, in order to realize the method 2), FIG.
The circuit diagram of B is adopted. This is a circuit for selecting VY2 of four voltage levels (VY1, VY2, VY3, VY4) in a flyback period.

As described above, crosstalk can be eliminated even in the case of odd simultaneous selection.

Next, a case where a display-off (DSP_OFF) signal is input to the voltage-off circuit 266 via the retrace period detection circuit 272 will be described with reference to FIG.

In this case, the switch 8000 in FIG. 29 is switched to the (b) side, and the display is turned off (DSP_
OFF) signal is input to the retrace period detection circuit 272.

As shown in FIG. 31, the retrace period detecting circuit 272 receives a frame signal YD, a field signal FS, and an externally input DSP_OFF signal. The retrace period detection circuit 272 has a function of generating a signal corresponding to the DSP_OFF signal by itself even when there is no externally input DSP_OFF signal.

FIG. 31 is a diagram showing a circuit configuration example of the flyback period detection circuit 272, and FIG.
6 is a timing chart showing the operation of No. 2.

The retrace period detecting circuit 272 is a 3-bit counter that counts the FS signal and is reset by YD. In the case of simultaneous selection of four lines, four fields are required for display.

Since each field is distinguished by the FS signal, the output Q3 of the last three bits of the counter is H
The period during which the signal is high is the retrace period. By taking the NOR of the counter output Q3 and the external input DSP_OFF, an external input is also possible, and a data line drive circuit that does not need to create a retrace period by an external device such as a controller can be provided.

When the retrace period detection circuit 272 shown in FIG. 31 is used, when the NOR gate 2830 is High, VY3 is selected as the data line drive voltage.

The blanking period detection circuit 272 operates if the YD, FS, and DSP_OFF signals are input.
The present invention can be applied not only to a data line driving circuit equipped with a RAM but also to a data line driving circuit of a type for sequentially inputting data from the outside.

Next, a modification of the fourth embodiment will be described.

FIG. 33 is a diagram showing another configuration example of the retrace period detecting circuit 272, in which the retrace period detecting circuit is further downsized.

In the configuration of FIG. 33, the retrace period detecting circuit 27
2 is D flip-flop (DFR) with reset 3
It is composed of individual pieces.

As shown in FIG. 34, the blanking period detecting circuit 272 can be configured to detect the blanking period by decoding the address value of the row address register 257. In this case, the retrace period detecting circuit 272 is configured as shown in FIG.
As shown in FIG. 5, an address signal (RA signal) is received from the row address register 257, and the decoder 2850 detects a flyback period from 241H to 245H. The address signal (RA signal) has 8 bits (RA1 to RA1).
RA7) Yes. Of these, by taking the AND of the upper 4 bits, 240 or more (241H period) of the address value starting from 0 can be detected. Further, since the circuit can be constituted by one 4-input AND gate, the circuit can be made compact.

Further, as shown in FIG. 36, a voltage decision circuit 26 integrating the functions of the number-of-mismatches detection circuit and the voltage-off circuit.
7, the voltage during the retrace period can be set to a constant level.

FIG. 37 is a circuit diagram of a voltage determination circuit 267 having a gate configuration in the case of simultaneous selection of four lines.

In the scanning pattern generation circuit 91, C1
To C4 are determined. The four EX_OR gates 92 to 95 detect a mismatch between the image data for four lines output from the frame memory and the scanning pattern, and the adder circuit 96 outputs three bits (D2,
D1, D0). The 3-bit mismatch number is decoded by the decoding circuit 97 into signals sw1 to sw5 for selecting five levels of potentials (VY1 to VY5). The D_OFF signal is input to the decoding circuit 97. When this signal is Low, only the signal sw3 becomes High and VY3 is selected. D_
When the OFF signal is High, a voltage level corresponding to the detected number of mismatches is selected.

Further, as described in the third embodiment, voltage determining circuit 267 can be constituted by a ROM.

FIG. 38 shows the structure of the voltage determination circuit 267.

The voltage determination circuit 267 has the ROM
05 and PC circuits 606 to 610. The details of this configuration have already been described with reference to FIGS.

A display off signal (D_OFF signal) is input to these ROM circuits 601 to 605,
When the F signal is low, VY3 is selected, and when the D_OFF signal is high, the voltage is determined by the number of mismatches.

When the D_OFF signal is Low, D_OFF
All the N-channel transistors connected to the OFF signal are turned off, the output of the ROM circuit becomes High, and Vx5
Is not selected.

When only the level of the D_OFF signal is low in the ROM 603, the normal output is cut off and Vss is turned off.
By creating a path leading to (Low), a low-level output can also be performed.

As described above, according to the present embodiment, even when the multi-line driving method is employed, crosstalk can be eliminated by setting all the voltage levels of the data line driving voltages to be the same.

Next, a fifth embodiment will be described.

(Embodiment 5) (A) Features of this embodiment This embodiment relates to a scanning line driving circuit (X driver). According to this embodiment, the shift register operates with low power consumption without requiring a high-frequency clock, and the number of stages of the shift register is m / h (m is the number of scan outputs, and h is the number of scan lines selected simultaneously). ), It is possible to provide a scanning line driving circuit (X driver) with lower power consumption and reduced size.

(B) Problems Revealed by the Inventor FIG. 59 is a diagram showing the configuration of a scanning line drive circuit (X driver) studied by the present inventor before the present invention.

As shown in FIG. 59, the scanning line driving circuit (X driver) includes three IC chips 900, for example.
0, 9010, 9020 connected in cascade (cascade connection)
It is composed. The IC chip 9000 is the leading chip, and the IC chips 9010 and 9020 are subordinate chips. In the figure, FS is a terminal for outputting a carry signal,
FSI is a terminal for receiving a carry signal. The carry signal output from the IC chip 9020 is
Returned to 00.

In the case where two scanning lines are driven at the same time,
FIG. 51 shows an example of the internal configuration of the C chip 9000. FIG.
As described in the above, the IC chip constituting the scanning line driving circuit includes a code generator 1201, a first shift register 1202, a second shift register 1203, a level shifter 1204, a decoder 1205, and a voltage selector. 1206.

The driving voltage of the scanning line is, for example, “+ V1” or “−V1” when selected, and is “0” when not selected, and thus has a total of three levels. In addition,
“V1” and “−V1” are “Vx1” and “−Vx1” in FIG. 39B.
Has the same meaning as Therefore, in order to select one of these three levels, two bits of control information are required, and two-stage shift registers 1202 and 1203 are provided in FIG.

Since there are n scanning lines X1 to Xn, the number of bits in each of the shift registers 1202 and 1203 is n. For example, if the total number of scanning lines handled by one IC chip is 120, the number of bits of the shift registers 1202 and 1203 is 120 bits.

The configuration of the IC chip in the case of four-line simultaneous driving is, for example, as shown in FIG. 52. As the number of simultaneously driven scanning lines increases, the capacity of the shift register increases.

(C) Contents of the Embodiment FIG. 41 is a diagram showing the overall configuration of a liquid crystal display device. In the scanning line driving circuit 2200 of this embodiment, unlike the conventional case, only one shift register 102 is required. Moreover,
The number of bits of the shift register 102 may be n / h (n is the total number of scanning lines, and h is the number of scanning lines driven at the same time), which significantly simplifies the circuit configuration as compared with the related art.

This is the result of separating and processing data necessary for selecting a scanning line and data necessary for determining a voltage to be supplied to the scanning line.

In other words, conventionally, information on what number of scanning lines are to be driven and information on what driving potential is to be driven are collectively stored in the shift register.

On the other hand, the present embodiment focuses on the fact that the MLS drive sequentially drives h adjacent scanning line groups, and considers the h scanning line groups as one scanning line. When considered in this way, the number of bits of the shift register that stores information for specifying the scanning line to be driven is n / h (n is the total number of scanning lines, and h is the number of scanning lines to be driven simultaneously). Is enough.

On the other hand, the data for specifying the drive voltage can be easily generated from the code generator, and the data for specifying the drive voltage and the data for specifying the scanning line are input to the decoder. By decoding, a scanning line control signal similar to the conventional one can be generated. As shown in FIG. 51, it is sufficient for the decoder to slightly improve the existing one, so that the circuit can be simplified by the reduced number of bits of the shift register.

That is, as shown in FIG. 41, the data output from the shift register 102 is selection data for sequentially selecting one group in which four scanning lines are grouped. Data D0 to D3 indicating whether to select the voltage output V1 or to select -V1 for the four scanning lines in one group are input to the decoder 103 in parallel. With this configuration, the number of bits of the shift register is 30 bits. Therefore, power consumption is reduced and the circuit scale can be reduced.

(D) Specific Circuit Configuration of this Embodiment A case in which four scanning lines are simultaneously selected and one IC chip drives 120 scanning lines will be specifically described.

FIG. 42 shows the scanning line driving circuit 2200 of FIG.
3 is a specific circuit diagram of FIG. The code generation unit 101
A counter 201 which is reset by a signal and counts a selection pulse LP; a pattern decoder 202 composed of a ROM which outputs data D0, D1, D2 and D3 according to the address of the counter 201 and the FR signal; and a latch which latches the data. 203, buffer inverters 204 and 205 that operate using the LP signal as a clock, a circuit 206 that generates data SD to be input to the shift register from the head chip identification signals MS, YD signal, and FSI signal, and a delay line 207. And is constituted by.

Next, the decoder 103 and the level shifter 10
4. The voltage selector 105 will be described. The circuit shown in FIG. 42 uses the first four scanning lines (X1, X2, X3, X
4) shows a circuit for outputting.

The first output of the shift register is SH1. This SH1 is input commonly to each decoder. The data D1, D2, D3, D4 are input to the decoder 103. A DOFF signal for forcibly setting the voltage to 0 potential is also input to the decoder 103.

The data (D0, D0)
1, D2, D3) are decoded and become switch signals of respective voltages, and + Vx1, 0, -Vx1 are selected by the level shifter 104 and the voltage selector 105, and X1, X2,
It is output to X3 and X4.

The logic operation can be summarized as follows.
Is a signal indicating whether Y1 to Y4 are selected (High) or not selected (Low). SH1 is L
In the case of ow, the signals D0 to D3 are High and Lo.
Regardless of w, the output potentials of Y1 to Y4 are determined.
For example, when D0 is High, Y1 represents V1 and D1 represents D1.
When 0 is Low, -V1 is output. Similarly, voltages of Y2 to Y4 are determined according to D1 to D3, respectively.

FIG. 43 is a timing chart when four scanning lines are simultaneously selected.

One frame period is 240 scanning periods (LP)
And In this case, two IC chips shown in FIG.
Cascaded. When the YD signal is input to the first chip, the SH1 signal first becomes High for one LP period.

The shift register 102 shifts data for each LP. 240 scanning lines, 1
Times, in order to finish scanning all, 60 selection pulses LP
Is required, and this is defined as one field.

When the scanning of one field is completed, the FS signal of the cascaded subordinate chip is input as the FSI signal of the first chip as shown in FIG. As a result, the SH1 signal becomes High again, and the operation of sequentially selecting four scanning lines again starts.

As described above, two fields, three fields, and four fields are selected, and the operation of one frame is completed. The operation after one frame is a repetition of the operation described above.

The case where four scanning lines are selected at the same time has been described above. However, the present invention is not limited to this case.
In the case of simultaneous selection of 0 stages and 8 lines, it can be configured as 15 stages. Obviously, the present invention can be applied to the case where the number of simultaneously selected scanning lines is two or more.

Next, a modification of the fifth embodiment will be described.

FIG. 44 shows a configuration of the modification. In FIG. 41, the level shifter 104 is located after the decoder 103. FIG. 44 shows a configuration in which the decoder 504 is provided after the level shifter 503.

The input to the level shifter 503 is 30 signals of the outputs (SH1 to SH30) of the shift register 502 and 4 signals of the data (D0 to D3) from the code generator 501. Therefore, the total number of bits of the level shifter is only 34 bits. In FIG. 41, 120 × 3 =
Since a 360-bit level shifter is required, the circuit can be further simplified.

FIG. 45 shows the structure of another modification.

In FIG. 45, the inside of the code generator 601 is divided into a register controller 601 and a pattern decoder 6.
02.

The pattern decoder 602 has an input terminal for inputting the scanning voltage pattern data PD1, PD0.

Scan pattern data PD1 and PD0 are sent from data line drive circuit (Y driver) 2100.

Data line drive circuit (Y driver) 2100
Even if the pattern to be used is changed in the non-coincidence detecting circuit, the change in the scanning voltage pattern is notified to the scanning line driving circuit (X driver) as pattern data PD1 and PD0. Even without changing the circuit configuration of the driver, the output order of the column patterns can be changed in accordance with the scanning pattern used in the data line driving circuit (Y driver) 2100. This will be described in detail in a sixth embodiment described later.

Also, the counter 201 which is required in the preceding stage of the pattern decoder 202 is not required, and the pattern decoder itself does not need to count, for example, 240 selection pulses LP. Therefore, there is an advantage that the size of the liquid crystal driving device can be further reduced.

FIGS. 46 and 47 show the pattern decoder 602.
The following shows an example of the circuit. FIGS. 48A and 48B schematically show scanning patterns.

The pattern decoder 602 shown in FIG.
The pattern decoder 602 of FIG. 47 decodes the scanning voltage pattern of FIG. 48A, and decodes the scanning voltage pattern of FIG. 48B.

A case where display is performed using the scanning voltage pattern of FIG. 48A will be described. The scanning voltage pattern in FIG. 48A schematically shows the selection voltages of the four scanning lines to be selected. “+” Indicates “V1”, and “−” indicates “−V1”.
Means

For example, all the scanning lines selected in the first field select V1. The first and second lines selected in the second field select V1, and the third and fourth lines select -V1.

However, if the same pattern for one field is selected and displayed as described above, crosstalk,
It is known to cause flicker. Therefore, 1
The display starting from the field and successively becoming the pattern of the fourth field is applied to the scanning lines of 1 to 16 lines.
In some cases, display starting from the field and displaying the patterns in the third, fourth, and first fields in order is applied to the next 17 to 32 scanning lines using an output voltage pattern.

In this case, lines 1 to 16 are selected by the first four selection pulses LP, and lines 17 to 32 are selected by the next four LPs. The display described above can be performed only by inputting a signal for distinguishing a pattern for every 4LP to the input terminals PD1 and PD0.

When it is desired to change to the scanning voltage pattern of FIG. 48B, as shown in FIG.
It can be easily changed only by changing the input of the D gate. Also, AC driving that alternately selects “V1” and “−V1” by the FR signal is possible.

Although the pattern decoder circuit using the gate circuit has been described above, the same effect can be obtained by using a ROM.

FIG. 49 shows another modification.

A modification of FIG. 49 is a circuit diagram showing an internal configuration of register controller 601 shown in FIG. FIG. 50 is a timing chart showing the operation of the circuit of FIG.

The selection pulse (LP) 24 corresponds to one frame period.
In the case where the number of scanning lines corresponds to zero, as shown in FIG. 43, each scanning line is normally selected four times in one frame period, and the voltage V
1 or 0 or -V1 is applied. However, when the retrace period is included (one frame in FIG. 50 corresponds to 245 LPs), the display is disturbed.

This is because an unnecessary voltage is applied to the liquid crystal display panel because the counting of the counter proceeds even during the flyback period and the scanning line selection operation is restarted. To make this display normal, during the retrace period, the DOFF signal is forcibly input from the outside and the potential of the SD signal is set to 0V.
It is necessary to

In FIG. 49, in order to save the trouble of forcibly inputting the DOFF signal from the outside, the blanking period processing circuit 100
1 is added.

The operation of blanking period processing circuit 1001 of FIG. 49 will be described with reference to the timing chart of FIG. In FIG. 50, the number of scanning lines to be driven is 240, one frame period is a period corresponding to 245 selection pulses (LP), and a retrace period is a period corresponding to five selection pulses (LP). I have.

Since the total number of scanning lines is 240,
Two IC chips having zero outputs are cascaded. FIG. 50 shows the timing of the change of the FSI, FS, etc. of the first chip.

First, when the YD signal is input, scanning starts with an LP signal (not shown). Up to 30 LPs, scanning of the 120 outputs of the first chip is completed, and a high-level FS signal is input to the cascaded subordinate chips. When the scanning of the dependent chip is completed, the high-level FS signal of the dependent chip is input as the FSI signal of the leading chip, and the scanning shifts from one field to two fields. The above operation is repeated to scan up to four fields.

At this time, Q in the flyback period processing circuit 1001
The signals 10, Q20, and Q30 are reset by the YD signal and become low, and then become high at the rise of the FSI signal in the first, second, and third fields, respectively. The G10 signal is a signal for latching the Q30 signal. Due to this G10 signal, at time t4 during the flyback period, the FSI signal is changed to the AND gate 100 shown in FIG.
2, thereby preventing unnecessary display during the flyback period.

Next, a sixth embodiment of the present invention will be described.

(Embodiment 6) In the case of implementing the MLS driving method, determination of the number (h) of scanning lines to be simultaneously driven and selection of a scanning voltage pattern are the most basic and important items. In this embodiment, a description will be given of the number of simultaneous drive lines and a scanning voltage pattern which are preferably employed when a liquid crystal display device is formed using the circuit configurations of Embodiments 1 to 5 described above.

(A) According to the study of the present inventor, the number of simultaneously selected lines is preferably four (h = 4) from the viewpoint of preventing the circuit from becoming complicated, reducing power consumption and preventing crosstalk. Further, as shown in FIG. 60A (FIGS. 28B and 48B), the scanning voltage pattern in the case of four
It is preferable to adopt a pattern in which the polarity of one of the four selection pulses for selecting a book is opposite to the polarity of the other three selection pulses. For example, in FIG. 60A, the pattern in the first column (vertical pattern)
Is (+, +,-, +).

When such a pattern is adopted, for example, when a display is performed in which all the pixels located on one data line are turned on, the selection voltage is substantially uniformly applied to the pixels during one frame period. This means that the voltage has been applied. Further, a change in luminance within one frame period is also suppressed. Therefore, when displaying black characters on a white screen,
It is possible to reduce flicker, improve contrast, and improve image quality. Further, it is also advantageous when performing gradation display by the frame gradation method.

In order to realize the MLS drive based on the above-described scanning voltage pattern, the ROM (decoder) 5 in the data line drive circuit (Y driver) shown in FIG. And it is sufficient. In response to this, the scanning line driving circuit (X
Pattern decoder (ROM) 20 in the driver 101
2 may also be configured as shown in FIG. As shown in FIG. 60C, the pattern of each row (horizontal pattern)
Thus, the same effect can be obtained even if the polarity of one selection pulse is made different from the polarity of another selection pulse.

(B) When the scanning voltage pattern is periodically changed, the occurrence of high-frequency components and low-frequency components due to MLS driving is reduced, and crosstalk and flicker are reduced.
It is further reduced. This is also described in the fifth embodiment with reference to FIG.

A technique for periodically changing the scanning voltage pattern will be specifically described. As shown in FIG. 60B, let the patterns in each column be a, b, c, and d.

As shown in FIG. 62B, when one frame period is made up of four field periods, and a driving method of selecting all the scanning lines once during one field period is adopted, one frame period is used during one field period. It is preferable to drive a scan line using a plurality of different scan voltage patterns.
That is, aabbc, bbcc illustrated in FIG.
d, ccdda, ddab, a pattern that changes periodically, abcda, bcdab, cdabc, dabc
A pattern that changes periodically with d can be adopted. This suppresses a change in the luminance of the liquid crystal panel during one frame period, prevents flickering of an image, and reduces occurrence of crosstalk.

As shown in FIG. 62A, if one pattern is used within one field period,
High frequency components and low frequency components are more likely to occur than in the case of FIG. 62B.

FIG. 63 shows a system configuration for realizing the above-described method of periodically changing the scanning voltage pattern.

One of the features of FIG. 63 is that by transmitting pattern data signals (pattern identification signals) PD0 and PD1 from a data line driving circuit (Y driver) 9300 to a scanning line driving circuit (X driver) 2200, the scanning voltage is reduced. The change of the pattern is performed by the data line driving circuit (Y driver) 9300.
Only by inputting a control signal to the A scanning line driving circuit (X) using pattern data signals PD0 and PD1
The operation on the driver (2200) side is described in FIGS.
Embodiment 7 is described in detail in Embodiment 5.

One of the features of the system shown in FIG.
The scan line drive circuit (X driver) 2200 transmits a carry signal (FS signal) from the scan line drive circuit (Y driver) 2200 to the data line drive circuit (Y driver) 9300 as a field identification signal (CA signal).
And the data line driving circuit (X driver) 9300 can easily transmit information. That is, it is not necessary to newly add a special control signal.

FIG. 65 is a diagram showing a configuration example of a circuit for generating pattern data PD0 and PD1 for periodically changing a scanning voltage pattern.

This circuit comprises an address counter 9500
, A selector 9510, and 2 which functions as a divide-by-2 circuit.
Two D-type flip-flops 9520 and 9530, logic circuits 9540 and 9550, two D-type flip-flops 9560 and 9570, and an exclusive OR circuit 958
0.

The circuit of FIG. 65 operates at the timing shown in FIG.

The selector 9510 selects and outputs any one of a plurality of types of clocks sent from the address counter 9500 by a control signal from the outside, for example. The clock output from the selector 9510 functions as an operation clock for the two D-type flip-flops 9560 and 9570.

The field identification signal CA sent from the scanning line driving circuit and the YD signal indicating the start of the frame period are frequency-divided by two D-type flip-flops 9520 and 9530. Clock signals CC1 and CC2 are formed, and pattern data PD0 and PD2 are generated based on these clock signals CC1 and CC2.
1 is generated.

Then, as shown in the lower part of FIG. 64, one of the patterns a to d shown in FIG. 62B is selected according to the combination of the voltage levels of the pattern data PD0 and PD1. That is, when both PD0 and PD1 are at the low level, the pattern “a” is selected, and when PD0 is at the high level and PD1 is at the low level, the pattern “b” is selected, and when PD0 is at the low level and PD1 is at the high level. Sometimes pattern “c” is selected and PD0, P
When both D1 are at the high level, the pattern "d" is selected.

As described above, by employing the configurations shown in FIGS. 63 and 65, it is possible to perform MLS driving while periodically changing the scanning voltage pattern.
When the liquid crystal is driven by the liquid crystal driving method according to the present embodiment, even when a gray scale display is performed using a liquid crystal display with high responsiveness, a gray scale display with high display quality with less crosstalk and flickering can be performed. .

Therefore, if the liquid crystal display device of this embodiment is used as a display device in a device such as a personal computer, the value of a product is improved.

Note that the present invention is not limited to the above-described embodiment, and can be variously modified. For example, various voltage levels can be adopted as the selection voltage or the non-selection voltage of the scanning line.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining an outline of the present invention.

FIG. 2 is a diagram illustrating an overall configuration of a display device of the present invention.

FIG. 3A is a diagram illustrating one arrangement example of a circuit for driving a data line, and FIG. 3B is a diagram illustrating another arrangement example of a circuit for driving a data line.

FIG. 4A is a diagram for explaining a problem when a conventional technique for accessing a frame memory is used, and FIG. 4B is another diagram for explaining a problem with the conventional technology. .

FIG. 5A is a diagram for explaining a conventional access technology to a frame memory, and FIG. 5B is a diagram for explaining an access technology in the first embodiment of the present invention.

FIG. 6A is a diagram for explaining a conventional access technology to a frame memory, and FIG. 6B is a diagram for explaining an access technology in a second embodiment of the present invention.

FIG. 7 is a diagram for explaining the reason why the inconvenience is solved by the access technique to the frame memory according to the second embodiment shown in FIG. 6B;

FIG. 8 is a diagram showing a circuit configuration for realizing access to a frame memory as shown in FIG. 6B.

FIG. 9 is a diagram illustrating an input buffer circuit 201 in FIG. 8;
3 is a timing chart showing the operation of FIG.

FIG. 10 is a timing chart showing the operation of the input buffer circuit 2011 in FIG. 8;

FIG. 11 is a circuit diagram of the input buffer circuit 2 shown in FIG. 8;
FIG. 11 is a diagram illustrating an example of a circuit configuration of part of FIG.

FIG. 12 is a timing chart illustrating the operation of the circuit in FIG. 11;

FIG. 13 is a diagram illustrating the input buffer circuit 2 shown in FIG. 8;
FIG. 11 is a diagram illustrating another example of the circuit configuration of part of FIG.

FIG. 14 is a timing chart illustrating the operation of the circuit in FIG. 13;

FIG. 15 is a timing chart showing the operation of the circuit of FIG. 13;

FIG. 16 is a diagram illustrating an input buffer circuit 2 shown in FIG. 8;
FIG. 11 is a diagram illustrating still another example of the partial circuit configuration of No. 011;

FIG. 17 is a timing chart illustrating the operation of the circuit in FIG. 16;

FIG. 18 is a timing chart illustrating a control example of the display device when three scanning lines are simultaneously selected.

FIG. 19 is a diagram showing a circuit according to a third embodiment of the present invention.

FIG. 20 is a diagram showing a more specific configuration of the circuit of FIG. 19;

FIG. 21 is a circuit diagram for explaining features of the third embodiment of the present invention (the decoder is configured by a ROM).

FIG. 22 is a diagram illustrating a configuration example of a ROM illustrated in FIG. 21;

FIG. 23 is a circuit diagram illustrating an example of a circuit configuration of the precharge circuit 10 of FIG. 21;

FIG. 24 is a timing chart showing an operation of the ROM shown in FIG. 21;

FIG. 25 is a diagram showing characteristics of a transmission line of a precharge (PC) signal of the ROM shown in FIG. 21;

FIG. 26 is a diagram showing a configuration of a conventional decoder.

FIG. 27 is a diagram illustrating voltage values used for selection when four scanning lines are simultaneously driven.

28A and 28B are diagrams each showing an example of a scanning pattern.

FIG. 29 is a block diagram illustrating an overall configuration of a data line drive circuit according to a fourth embodiment of the present invention.

30A is a diagram illustrating an example of a configuration of a voltage off circuit, and FIG. 30B is a diagram illustrating another example of a configuration of a voltage off circuit.

FIG. 31 is a diagram illustrating an example of a configuration of a flyback period detection circuit;

FIG. 32 is a timing chart showing the operation of the circuit of FIG. 31;

FIG. 33 is a block diagram illustrating another example of the configuration of the flyback period detection circuit;

FIG. 34 is a diagram illustrating a configuration (an entire configuration of a data line driving circuit) according to a modification of the fourth embodiment;

FIG. 35 is a diagram showing still another example of the configuration of the flyback period detection circuit.

FIG. 36 is a block diagram showing a configuration of another modification example of the fourth embodiment.

FIG. 37 is a diagram illustrating the voltage determination circuit 26 in FIG. 36;
7 is a circuit diagram illustrating a configuration example of FIG.

FIG. 38 is a diagram illustrating an example in which the voltage determination circuit 267 is configured by a ROM.

FIG. 39A is a diagram showing a driving potential of a data line in multiplex driving, and FIG. 39B is a diagram showing a driving potential of a data line in multi-line driving.

FIG. 40 is a timing chart showing the timing of data transfer to the data line driving circuit.

FIG. 41 is a diagram showing an overall configuration of a fifth embodiment of the present invention.

FIG. 42 is a diagram illustrating a configuration example of a main part of a fifth embodiment of the present invention.

FIG. 43 is a timing chart for explaining the operation of the circuits of FIGS. 41 and 42;

FIG. 44 is a diagram extracting and showing a part of the circuit shown in FIG. 41;

FIG. 45 is a diagram illustrating a configuration (a configuration example of a scanning line driving circuit) according to a modification example of the fifth embodiment;

FIG. 46 is a pattern decoder 602 of FIG.
FIG. 3 is a diagram showing an example of the configuration of FIG.

FIG. 47 is a diagram illustrating the pattern decoder 602 in FIG. 45;
FIG. 9 is a diagram showing another example of the configuration of FIG.

FIG. 48A is a diagram illustrating an example of a scanning pattern, and FIG. 48B is a diagram illustrating another example of a scanning pattern.

FIG. 49 is a diagram showing the register controller 6 shown in FIG. 45;
It is a figure which shows an example of a structure of No. 01.

FIG. 50 is a timing chart showing the operation of the circuit of FIG. 49;

FIG. 51 is a diagram showing an example of a configuration of a scanning line driving circuit studied by the present inventors before the present invention.

FIG. 52 is a diagram showing another example of the configuration of the scanning line driving circuit studied by the present inventors before the present invention.

FIG. 53 is a diagram showing an arrangement of electrodes in a liquid crystal display panel.

FIG. 54 is a diagram for explaining an advantage when the multi-line driving method is adopted;

FIG. 55 is a diagram for explaining the content of the multi-line driving method.

FIG. 56 is a timing chart for explaining an operation of a driving circuit when a multi-line driving method is used.

FIG. 57 is a timing chart showing an operation of inputting and outputting data to and from a frame memory included in the data line driving circuit when the multi-line driving method is used.

FIG. 58 is a timing chart showing an operation of inputting data to a frame memory included in the data line driving circuit when the multi-line driving method is used.

FIG. 59 is a block diagram illustrating an example in which a scanning line driver circuit is configured by cascading a plurality of IC chips.

FIG. 60A is a diagram showing an example of a scanning voltage pattern (selection voltage pattern) in the case of four-line simultaneous driving according to the sixth embodiment of the present invention, and FIG. 60B shows an arrangement of column patterns. FIG. 60C is a diagram illustrating an example of a scanning voltage pattern (selection voltage pattern) in the case of simultaneous driving of three lines.

FIG. 61 is a decoder (RO) of a data line drive circuit (Y driver) according to the sixth embodiment of the present invention;
FIG. 3M is a diagram showing the configuration of FIG.

FIG. 62A is a diagram illustrating an example of a conventional scanning voltage pattern, and FIG. 62B is a diagram illustrating a change in the scanning voltage pattern according to the sixth embodiment of the present invention.

FIG. 63 is a diagram illustrating an example of the overall configuration of a liquid crystal display device according to a sixth embodiment of the present invention.

FIG. 64 is a timing chart for explaining the operation of the circuit shown in FIG. 65;

FIG. 65 is a diagram showing a configuration of a pattern data creation circuit in a data line drive circuit according to a sixth embodiment of the present invention.

[Explanation of symbols]

 252 Frame memory 258 Decoder 266 Voltage off circuit (data line off circuit) 267 Voltage determination circuit 272 Retrace period detection circuit (blank period detection circuit) 2100 Data line drive circuit 2200 Scan line drive circuit 2250 Matrix panel

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) G09G 3/20 623 G09G 3/20 623R 631 631C (31) Priority claim number Japanese Patent Application No. Hei 7-199826 (32) Priority date August 4, 1995 (August 1995) (33) Priority claiming country Japan (JP) (72) Inventor Shingo Isozaki 3-5-5 Yamato, Suwa-shi, Nagano Seiko Epson Corporation (72 Inventor Satoru Ito 3-3-5 Yamato, Suwa-shi, Nagano Pref. Seiko Epson Corporation

Claims (12)

[Claims] A plurality of scanning lines, a plurality of data lines, a display element driven by the scanning signal and the data signal,
A scanning line driving circuit for simultaneously selecting a plurality of the scanning lines and applying a scanning voltage having a predetermined selection voltage pattern; and turning on / off the selection voltage pattern and display elements of the matrix panel. A data line drive circuit that determines a voltage to be applied to the data line based on comparison with display data indicating the data line, and applies the determined voltage to the data line. The display device, wherein the drive circuit includes a data line off circuit for applying a common voltage to all data lines during a period in which the display does not contribute to display on the matrix panel. 2. The display device according to claim 1, wherein the operation of the data line off circuit is controlled by a control signal input from the outside. 3. The data line drive circuit according to claim 1, further comprising a blank period detection circuit, wherein the data line off circuit is configured to output all data while the blank period detection circuit detects a blank period. A display device, which performs control necessary for applying a common voltage to lines. 4. The display device according to claim 3, wherein the blank period detection circuit includes a counter for counting the number of field status signals (FS) indicating the start of the field period. 5. The display device according to claim 3, wherein the blank period detection circuit includes a decoder for decoding an address value of the frame memory. 6. The display device according to claim 1, wherein the number h of scanning lines selected at the same time is expressed by the following equation. h = 2 ^k (where k is a natural number) 7. The display device according to claim 1, wherein the number of scanning lines selected simultaneously is four (= 2 ² ). 8. A display element driven by a plurality of scanning lines, a plurality of data lines, a scanning signal and a data signal,
A scanning line driving circuit for simultaneously selecting a plurality of the scanning lines and applying a scanning voltage having a predetermined selection voltage pattern; and turning on / off the selection voltage pattern and display elements of the matrix panel. A data line drive circuit that determines a voltage to be applied to the data line based on comparison with display data indicating the data line, and applies the determined voltage to the data line. The drive circuit has a function of performing control for applying a common voltage to all the data lines during a period not contributing to display on the matrix panel, and a function of controlling the number of data lines according to the number of mismatches between the selected voltage pattern and the display data. A display device comprising a voltage determination circuit having a function of determining a voltage to be applied. 9. The display device according to claim 8, wherein the number h of scanning lines selected at the same time is expressed by the following equation. h = 2 ^k (where k is a natural number) 10. The display device according to claim 8, wherein the number of scanning lines selected simultaneously is four (= 2 ² ). 11. The voltage determination circuit according to claim 8, wherein the voltage determination circuit is a ROM (Read Only Memory).
This ROM comprises a first input line for inputting a control signal for causing a common voltage to be applied to all data lines, and a ROM for inputting the display data and the selected voltage pattern information. A second input line, and a plurality of output lines formed by connecting a source / drain path of the insulated gate transistor in series. The first input line and the plurality of insulated gate transistors The configuration of the ROM can be programmed by connection / disconnection with the gate of the first input line, the first input line is commonly connected to the plurality of output lines, and the first input line The level of each output of the plurality of output lines can be fixed at a common potential by setting the voltage level of the control signal input via the control signal to a predetermined level. A display device for. 12. An electronic apparatus comprising the display device according to claim 1.