JP2001235851A - Photomask, exposure device, exposure method and method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a photomask which is transferred with the pattern in an effective pattern region and is capable of transferring dummy patterns to the circumference of an exposure object, an exposure device and an exposure method as well as a method for manufacturing a semiconductor device utilizing this photomask. SOLUTION: The photomask 200 has the effective pattern region 210 and the dummy pattern regions 220 disposed at least in part of the circumference of the effective pattern region 210. The dummy pattern regions 220 are formed along the outer circumference of the effective pattern region 210. A light shielding zone 230 is disposed between the effective pattern region 210 and the dummy pattern regions 220.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a photomask, an exposure apparatus, an exposure method, and a method for manufacturing a semiconductor device.
In particular, the present invention relates to a photomask, an exposure apparatus, an exposure method, and a method for manufacturing a semiconductor device using the exposure apparatus used in a lithography technique.

[0002]

2. Description of the Related Art When a semiconductor device is manufactured, a photolithography process and an etching process are performed to pattern a semiconductor substrate or a layer formed on the semiconductor substrate into a predetermined shape. This photolithography step is performed by exposing and developing a photoresist. In the case of using a light exposure technique when exposing the photoresist, the exposure is performed through a photomask between the light source and the photoresist. By exposing the photoresist, the pattern of the photomask is transferred to the photoresist.

[0005] As schematically shown in FIG. 15, the photomask 400 includes an effective pattern area 410 and a light-shielding band 420 provided around the effective pattern area 410. This photomask 400 is used, for example, for exposure in a repeat and step method.

[0004] Taking the exposure of a semiconductor wafer 500 as an example,
Generally, as shown in FIG. 16, only the chip region 520 is exposed, and the non-chip region 522 (the region shown by hatching in FIG. 16) is not exposed.

[0005]

SUMMARY OF THE INVENTION It is an object of the present invention to transfer a dummy pattern around an area of an object to be exposed on which a pattern of an effective pattern area is transferred.
An object of the present invention is to provide a photomask, an exposure apparatus, an exposure method, and a method for manufacturing a semiconductor device using the photomask.

[0006]

Means for Solving the Problems (Photomask) A photomask according to the present invention is provided in an effective pattern region and at least a part around the effective pattern region.
And a dummy pattern region.

[0007] Here, the effective pattern area refers to, for example, an area having a pattern to be transferred to a product area of the object to be exposed. Specifically, the effective pattern region refers to a region having a pattern transferred to a chip region when the photomask is applied to, for example, manufacturing of a semiconductor device. The dummy pattern region is, for example, a region having a pattern to be transferred to a non-product region of an exposure target. Specifically, the dummy pattern region refers to a region having a pattern transferred to a non-chip region when a photomask is applied to, for example, manufacturing of a semiconductor device.

[0008] The photomask of the present invention has a dummy pattern region provided at least partially around the effective pattern region. Therefore, according to the photomask of the present invention, the pattern of the effective pattern area is transferred to the surface of the exposure object, and the pattern of the dummy pattern area is transferred around the area where the pattern of the effective pattern area is transferred. can do.

[0009] The dummy pattern area may be formed along an outer periphery of the effective pattern area. Thereby, the pattern of the dummy pattern area can be transferred along the outer periphery of the area where the pattern of the effective pattern area is transferred on the exposure target.

[0010] The dummy pattern area can be formed continuously. Since the dummy patterns are continuous, a continuous pattern of the dummy pattern area can be transferred around the area where the pattern of the effective pattern area is transferred.

A light-shielding band may be provided between the effective pattern area and the dummy pattern area. By providing the light-shielding band, for example, even if a misalignment occurs between a blind and a photomask for concealing a predetermined area of the dummy pattern area, the pattern of the dummy pattern area that is not desired to be transferred is exposed to the exposure target. Transfer can be reliably prevented.

(Exposure Apparatus) An exposure apparatus according to the present invention is an exposure apparatus including a light source and a photomask, wherein the photomask is the photomask according to any one of claims 1 to 4.

According to the exposure apparatus of the present invention, the pattern of the effective pattern area is transferred onto the surface of the object to be exposed, and at the same time, the pattern of the dummy pattern area is transferred around the area where the pattern of the effective pattern area is transferred. can do.

[0014] The exposure apparatus may further include a blind, and the blind may be provided between the light source and the photomask. According to this, by controlling the blind, the area where the pattern of the dummy pattern area is transferred can be more reliably controlled.

(Exposure Method) The exposure method of the present invention is an exposure method for exposing an object to be exposed using a light source and a photomask, wherein the photomask is any one of claims 1 to 4. It is a photomask of the description.

According to this exposure method, the pattern of the effective pattern area is transferred onto the surface of the object to be exposed,
The pattern of the dummy pattern area can be transferred around the area where the pattern of the effective pattern area is transferred.

[0017] A blind may be provided between the photomask and the light source. According to this exposure method, by controlling the blind, the area where the pattern of the dummy pattern area is transferred can be controlled.

(Method of Manufacturing Semiconductor Device) A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device using the exposure apparatus according to claim 5 or 6, wherein the semiconductor device is formed on a semiconductor wafer. (A) for exposing the exposed resist layer
Wherein the semiconductor wafer includes a chip region and a non-chip region, and in the step (A), the pattern of the effective pattern region is transferred in the chip region and the dummy pattern region is transferred in the non-chip region at the same time. And transferring the pattern.

The step (A) can be the following step.

The step (A) is a step for further forming a trench, and the transfer of the pattern of the dummy pattern region in the non-chip region is performed so that a dummy trench is formed in the non-chip region. Done.

Thus, the pattern of the dummy pattern area of the photomask is transferred to the non-chip area. As a result, in the step of polishing the insulating layer filling the trench, the uniformity within the wafer surface is improved for the reason described later.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings.

[Photomask] (Overall Configuration) First, a photomask according to the embodiment will be described. FIG.
It is a top view which shows a photomask typically.

The photomask 200 has an effective pattern area 210 and a dummy pattern area 220. The dummy pattern area 220 is formed around the effective pattern area 210. The effective pattern area 210 refers to, for example, an area having a pattern to be transferred to an area to be a product of an exposure target. Specifically, the effective pattern region 210 refers to a region having a pattern transferred to a chip region when the photomask is applied to, for example, manufacturing of a semiconductor device. Dummy pattern area 2
Reference numeral 20 denotes, for example, a region having a pattern transferred to a region of the exposure target that does not become a product. Specifically, the dummy pattern area 220 is a photomask
For example, when applied to the manufacture of a semiconductor device, it refers to a region having a pattern transferred to a non-chip region.

The dummy pattern area 220 is specifically formed along the outer periphery of the effective pattern area 210. The dummy pattern region 220 is formed along each side of the outer periphery of the effective pattern region 210.
First to fourth dummy pattern portions 222, 224, 226,
228. It is preferable that adjacent dummy pattern portions are continuous. Since the adjacent dummy pattern portions are continuous, the pattern of the continuous dummy pattern region 220 can be transferred around the region of the exposure target to which the effective pattern region 210 has been transferred.

A first light-shielding band 230 is formed between the effective pattern area 210 and the dummy pattern area 220. By forming the first light-shielding band 230, even if the position is shifted between the photomask 200 and a blind described later, the pattern of the dummy pattern portion that is not desired to be transferred is transferred to the exposure target. Can be reliably prevented. Outside the dummy pattern area 220, a second light-shielding band 240 is formed.

(Function and Effect) In the photomask 200 according to the embodiment, a dummy pattern area 220 is formed around the effective pattern area 210. Therefore, when the pattern of the effective pattern area 210 of the photomask 200 is transferred to the exposure target, the pattern of the dummy pattern area 220 can be transferred to the exposure target at the same time.

[Exposure Apparatus] (Overall Configuration) Next, an exposure apparatus according to an embodiment will be described. Specifically, an example in which the photomask of the present invention is applied to a reduction projection exposure apparatus will be described. FIG. 2 is a diagram schematically showing an exposure apparatus. FIG. 3 is a plan view showing an arrangement relationship between the blind and the photomask as viewed from above the blind.

The exposure apparatus 300 includes a light source 310, a blind 320, a photomask 200 according to the present invention, and a reduction projection lens 340. A predetermined exposure object 350 is provided below the reduction projection lens 340.

The blind 320 is interposed between the light source 310 and the photomask 200. The blind 320 defines a shot area (illumination area) for the exposure target 350. That is, the blind 320 eliminates extra illumination light. The blind 320 includes a first movable blind 322 and a second blind 322.
Movable blind 324 and the third movable blind 32
6 and a fourth movable blind 328 (see FIG. 3). First to fourth movable blinds 322, 324, 32
6 and 328 are provided to be able to advance and retreat, respectively.
Then, the first to fourth movable blinds 322, 324, 3
26 and 328 have a role of hiding and opening the first to fourth dummy pattern portions 222, 224, 226 and 228, respectively. Movable blinds 322, 32
4, 326, 328 are connected to blind drive units 332, 334, 336, 338, respectively. The first and third blind driving units 332 and 336 cause the first and third blinds 322 and 326 to be ±
Move in the Y direction. Further, the second and fourth blind driving units 334 and 338 move the second and fourth blinds 324 and 328 in the ± X direction.

The reduction projection lens 340 is connected to the photomask 2
00 and the object 350 to be exposed. The reduction projection lens 340 has a function of reducing the pattern image of the photomask formed by passing the illumination light through the photomask 200 at a predetermined scale.

(Operation and Function and Effect) The operation and function and effect of the exposure apparatus according to the embodiment will be described below.

The illumination light emitted from the light source 310 passes through the blind 320, so that extra illumination light is eliminated. At this time, only the illumination light that irradiates only the shot area of the exposure object 350 passes through the blind 320.
Next, the passed illumination light passes through the photomask 200. When the illumination light passes through the photomask 200, a pattern image of the photomask 200 is formed.
Then, the pattern image of the photomask 200 is reduced at a predetermined scale by the reduction projection lens 340, and the pattern image of the photomask 200 is formed on the exposure target 350.

An exposure apparatus 300 according to the embodiment includes a photomask 200 according to the present invention. For this reason, for example, when exposing the resist layer formed on the semiconductor wafer 10 shown in FIG. 5, the following operation and effect can be obtained. That is, as described later in detail, simultaneously with the exposure of the shot area (the area defined by the broken line) in the outermost area of the chip area 20 (the area indicated by cross (x)), the non-chip area adjacent to the chip area 20 Exposure can also be performed on the region 22 (the region indicated by oblique lines). That is, the non-chip region 22 can be exposed without lowering the throughput of the exposure process.

By controlling the shape of the dummy pattern area 220 of the photomask 200, the exposure area of the non-chip area 22 can be controlled. For this reason,
The photomask 20 is placed on the non-chip region 22 so as not to overlap with a pattern such as printing formed on the non-chip region 22.
It becomes easy to transfer the pattern of 0.

Further, by controlling the shape of the dummy pattern area 220 so that the pattern transfer area of the dummy pattern area 220 does not protrude outside the semiconductor wafer 10, the focus can be accurately obtained, Difficult to focus. Therefore, problems such as peeling of the pattern do not occur.

[Manufacturing Method of Semiconductor Device] (Manufacturing Process) Hereinafter, a manufacturing process of a semiconductor device using the exposure apparatus according to the present invention will be described. Specifically, a method for forming a trench element isolation region using the exposure apparatus according to the present invention will be described. 4 and 7
11 to 11 are cross-sectional views schematically showing manufacturing steps of the semiconductor device according to the present embodiment.

(1) First, a description will be given with reference to FIG. A pad layer 12 is formed on a semiconductor wafer 10.
As a material of the pad layer 12, for example, silicon oxide,
Silicon oxynitride and the like can be given. When the pad layer 12 is made of silicon oxide, thermal oxidation, CV
It can be formed by the D method or the like. When the pad layer 12 is made of silicon oxynitride, it can be formed by a CVD method or the like. The thickness of the pad layer 12 is, for example, 5 to 20 nm.

Next, a polishing stopper layer 14 is formed on the pad layer 12. The polishing stopper layer 14 may have a single-layer structure or a multilayer structure. Examples of the single-layer structure include any of a silicon nitride layer, a polycrystalline silicon layer, and an amorphous silicon layer.
The multilayer structure has at least two layers selected from a silicon nitride layer, a polycrystalline silicon layer, and an amorphous silicon layer.
Examples include a multilayer structure composed of seeds. As a method for forming the polishing stopper layer 14, a known method such as a CVD method can be used. Polishing stopper layer 1
Reference numeral 4 has a film thickness sufficient to function as a stopper in polishing the insulating layer later, for example, a film thickness of 50 to 250 nm.

Next, a resist layer R1 is applied on the polishing stopper layer 14 by a known method.

(2) Next, as shown in FIG. 5, the resist layer R1 is exposed. FIG. 5 is a plan view for explaining an exposed area of the semiconductor wafer 10.

This exposure is performed not only in the chip area 20 but also in the chip area 20.
This is also applied to a part of the non-chip area 22 (area indicated by oblique lines). Specifically, in this exposure, the pattern of the effective pattern area 210 of the photomask 200 is transferred to the chip area 20 for each shot area. Further, the pattern of the dummy pattern area 220 of the photomask 200 is transferred to the non-chip area 22. Chip area 2
The exposure of 0 and the non-chip region 22 is specifically performed as follows.

The exposure of the chip area 20 is performed by performing a shot for each shot area. Examples of the method of exposing the chip area 20 include a method using a reduction projection exposure apparatus and a method using a 1: 1 exposure apparatus. As a method using the reduction projection exposure apparatus, a step-and-repeat method or a step-and-scan method is preferable. In the exposure of the chip area 20 other than the outermost area (the area indicated by the cross (x)), the blind and the photomask have an arrangement relationship as shown in FIG. Specifically, all of the first to fourth dummy pattern portions 222, 224, 226, 228
It is covered by four blinds 322, 324, 326, 328. Therefore, in the chip area 20,
In the exposure of an area other than the outermost area, the pattern of the dummy pattern area 220 is not transferred to the resist layer R1. The exposure of the outermost area of the chip area 20 is performed simultaneously with the exposure of the non-chip area 22. Therefore, the exposure of the outermost region will be described with reference to the exposure of the non-chip region 22.

The exposure of the non-chip area 22 is performed in the chip area 2
0 is performed along the outer circumference. That is, a non-chip area adjacent to the chip area is exposed. The exposure of the non-chip region is performed in the non-chip region 22 such that a dummy trench 42 described later is formed.

The method of exposing the non-chip area will be described by taking the exposure of the area A10 as an example. FIG. 6 is a plan view showing an arrangement relationship between a blind and a photomask in exposure of the area A10. The exposure of the non-chip area 22 in the area A10 is performed simultaneously with the shot of the shot area of the chip area 20 in the area A10. More specifically, the exposure of the shot area and the non-chip area in the area A10 is performed as follows. Before the exposure of the area A10, the blind 320 is controlled first. That is, as shown in FIG. 6, the first and second dummy pattern portions 22 are formed.
2 and 224 are not hidden in a plane by the first and second movable blinds 322 and 324, respectively. That is, the first and second dummy pattern portions 22
2,224 are released. In addition, the third and fourth dummy pattern portions 226 and 228 are hidden in a plane by the third and fourth movable blinds 326 and 328. As a result, by performing the exposure in the area A10, the exposure of the non-chip area 22 in the area A10 is performed simultaneously with the exposure of the chip area 20 in the area A10. That is, in the chip area 20 in the area A10, the pattern of the effective pattern area 210 is transferred, and at the same time, in the non-chip area 22, the pattern of the dummy pattern 220 is transferred. The exposure of the other non-chip region 22 can be performed only by controlling the blind 320, as in the exposure of the region A10.

Next, the resist layer R1 is developed, and FIG.
As shown in (a), a resist layer R1 having a predetermined pattern is formed.

(3) Next, as shown in FIG. 7B, the polishing stopper layer 14 and the pad layer 12 are etched using the resist layer R1 as a mask. This etching is
For example, it is performed by dry etching.

(4) Next, as shown in FIG. 8A, the resist layer R1 is removed. The resist layer R1 is removed by, for example, ashing. Next, using the polishing stopper layer 14 as a mask, the semiconductor wafer 10 is etched to form trenches 32 and 42. Specifically, the trench 32 is formed in the chip region 20, and the dummy trench 42 is formed in the non-chip region 22. The depth of the trenches 32 and 42 varies depending on the device design, but is, for example, 300 to 500 nm. The etching of the semiconductor wafer 10 can be performed by dry etching. The cross-sectional shape of the protrusion 60 formed between the trenches 32 and 42 is preferably tapered. Since the cross-sectional shape of the convex portion 60 is tapered, it is easy to bury the insulating layer 52 in the trenches 32 and 42, which will be described later. It is preferable that the taper angle α of the cross-sectional shape of the projection 60 is 70 degrees or more and less than 90 degrees.

Next, although not shown, the pad layer 12 interposed between the semiconductor wafer 10 and the polishing stopper layer 14 is formed.
Is etched.

(5) Next, as shown in FIG. 8B, the exposed surfaces of the semiconductor wafer 10 in the trenches 32 and 42 are oxidized by a thermal oxidation method to form a trench oxide film 34. Further, since the end portion of the pad layer 12 is etched by this thermal oxidation, the shoulder portion 10 of the convex portion 60 is formed.
a is oxidized and rounded. Trench oxide film 34
Has a thickness of, for example, 10 to 70 nm, and preferably 10 to 50 nm.

(6) Next, as shown in FIG. 9A, an insulating layer 52 is deposited on the entire surface so as to fill the trenches 32 and 42. Examples of the material of the insulating layer 52 include silicon oxide. The film thickness of the insulating layer 52 is not particularly limited as long as the film thickness fills the trenches 32 and 42 and covers at least the polishing stopper layer 14. The thickness of the insulating layer 52 is, for example, 500 to 800 nm.
It is. As a method for depositing the insulating layer 52, for example, a high-density plasma CVD (HDP-CVD) method, a thermal CVD method,
A TEOS plasma CVD method or the like can be given.

(7) Next, as shown in FIG. 9B, the insulating layer 52 is flattened by the CMP method. This flattening
The process is performed until the polishing stopper layer 14 is exposed. That is, the insulating layer 52 is planarized using the polishing stopper layer 14 as a stopper.

(8) Next, as shown in FIG. 10, the polishing stopper layer 14 is removed using, for example, a hot phosphoric acid solution.

Next, as shown in FIG.
And the upper part of the insulating layer 52 are isotropically etched with hydrofluoric acid. Thus, the trench insulating layer 50 is formed in the trench 32, and the trench element isolation region 30 is completed in the chip region 20. Trench element isolation region 3
By completing 0, the element formation region 36 is defined. At the same time, a trench insulating layer 50 is formed in the dummy trench 42, and in the non-chip region 22,
A dummy trench element isolation region 40 is formed. By forming the dummy trench element isolation region 40,
A dummy element formation region 46 is defined.

(Function and Effect) The method for manufacturing a semiconductor device according to the present embodiment includes a step of exposing the non-chip region 22 in the step (2) described above. Therefore, according to the method of manufacturing a semiconductor device according to the present embodiment, for example, the following operational effects can be obtained.

If the step (2) described above does not include the step of exposing the non-chip region 22, no trench is formed in the non-chip region. Therefore, as shown in FIG. 12, a wide convex portion 160 is formed in the non-chip region. When the wide convex portion 160 is formed, the following problem occurs.

When the insulating layer 152 is formed on the semiconductor wafer 110, the insulating layer 1
52 (the layer indicated by the broken line in FIG. 12) is deposited thickly. When the insulating layer 152 is polished in a state where the insulating layer 152 is thickly deposited on the wide convex portion 160, the insulating layer 152 (the layer shown by a solid line in FIG. 12) remains in the wide convex portion 160. Become. At the same time, the insulating layer 152 formed on the wide convex portion 160 is formed.
And the convex portion 16 adjacent to the wide convex portion 160
In 2, the insulating layer 152 remains. That is, the insulating layer remains in the convex portion 162 in the outermost region of the chip region 120. If the insulating layer 152 remains in the convex portion 162 in the outermost region of the chip region 120, the polishing stopper layer 114 cannot be removed, causing a problem that an element cannot be formed on the convex portion 162.

When the insulating layer 152 is polished in a state where the insulating layer 152 is thickly deposited on the wide convex portion 160, thinning and dishing are performed.
Such a phenomenon may occur. When these phenomena occur, problems such as variation in the thickness of the insulating layer 152 occur.

However, in the present embodiment, the non-chip region 22 adjacent to the chip region 20 is exposed, and the dummy trench 42 is formed in the non-chip region 22. For this reason, in the non-chip region 22 adjacent to the chip region 20, the thick deposition of the insulating layer 52 is suppressed. As a result, the following effects are obtained.

(A) Due to the effect of the insulating layer 52 deposited on the non-chip region 22, after the polishing of the insulating layer 52, on the polishing stopper layer 14 in the outermost region of the chip region 20,
The remaining of the insulating layer 52 is suppressed. That is,
In-plane uniformity of the insulating layer 52 in the outermost region of the chip region 20 can be improved. Therefore, when removing the polishing stopper layer 14 with hot phosphoric acid, the polishing stopper layer 14 can be reliably removed.

(B) When an isolated convex portion exists in the chip region 20, removal of the polishing stopper layer 14 at the isolated convex portion in polishing the insulating layer 52 can be suppressed. That is, in the polishing stopper layer 14 in the isolated convex portion, thinning is performed.
Can be suppressed.

(C) The occurrence of dishing at the upper portion of the insulating layer 52 can be suppressed.

(D) By the above effects (a) to (c),
The yield of chips formed in the outermost region of the chip region 20 can be improved.

The semiconductor wafer processed as described above is further subjected to a predetermined process, and
A semiconductor element (for example, a MOS element or a wiring layer) can be formed. Then, the semiconductor wafer on which the semiconductor elements and the like are formed is diced to obtain chips.

[Experimental Example] Depending on the presence or absence of exposure of the non-chip region, the thickness of the insulating layer remaining on the polishing stopper layer in the boundary region between the chip region and the non-chip region after polishing of the insulating layer So different. Hereinafter, an example in which the non-chip region is exposed is referred to as “Example”, and an example in which the non-chip region is not exposed is referred to as “Comparative Example”.

In the examples, the width of the exposure area in the non-chip area was 2 mm. In addition, the exposure of the non-chip area is performed from the boundary between the chip area and the non-chip area
The separation was performed by 0.1 mm.

The non-chip region was exposed so that the dummy element forming region 46 was arranged under the following conditions. FIG. 13 is a plan view showing an arrangement pattern of the dummy element formation region 46 in the example. (A) Assuming a first virtual straight line L1 extending along a direction intersecting with the row direction, the dummy element formation region 46
The center is arranged so as to be located on the first virtual straight line L1. (B) Assuming a second virtual straight line L2 extending along a direction intersecting the column direction, the dummy element formation region 46
The center is arranged so as to be located on the second virtual straight line L2. (C) Angle θ1 between first virtual straight line L1 and row direction
Was about 18.4 degrees. (D) The interval D1 between the first virtual straight lines L1 is about 3.2 μ
m. (E) Angle θ2 between the second virtual straight line L2 and the column direction
Was about 18.4 degrees. (F) The interval D2 between the second virtual straight lines L2 is about 3.2 μ
m. (G) Unit unit (area surrounded by square ABCD)
Is 40%. (H) The planar shape of the dummy element formation region 46 is a square. (I) One side of the planar shape of the dummy element formation region 46 is 2
μm. (J) In the adjacent dummy element forming regions 46 arranged on the same first virtual straight line L1, the interval G10 between the opposing sides is 1 μm. (K) In adjacent dummy element formation regions 46 arranged on the same second virtual straight line L2, the distance G20 between opposing sides is 1 μm. (L) In adjacent dummy element formation regions 46 arranged on the same first virtual straight line L1, the width Y10 shifted from each other in the column direction was 1 μm. (M) In adjacent dummy element formation regions 46 arranged on the same second virtual straight line L2, the width X10 shifted from each other in the row direction was 1 μm.

FIG. 14 shows the results obtained in Examples and Comparative Examples.
4 is a graph showing a distribution of a thickness of an insulating layer remaining on a polishing stopper layer. Reference point 0 is a boundary point between the chip area and the non-chip area. The area on the negative side from the reference point 0 is a chip area, and the area on the positive side from the reference point 0 is a non-chip area. The thickness of the insulating layer was based on the upper surface of the polishing stopper layer. Symbol a is a graph obtained from the data of the example, and symbol b is a graph obtained from the data of the comparative example.

In the comparative example, at reference point 0, the insulating layer remains on the polishing stopper layer. On the other hand, in the example, at the reference point 0, no insulating layer remains on the polishing stopper layer. From this, it was confirmed that the in-plane uniformity of the insulating layer can be improved in the chip region adjacent to the non-chip region by exposing the non-chip region.

[Modifications] The present invention is not limited to the above-described embodiment, and various modifications can be made within the scope of the present invention. For example, the following changes are possible.

In the above embodiment, an example has been described in which the exposure of the non-chip region is applied to the case where a dummy trench is formed in the silicon substrate in the non-chip region. However, the following changes are possible.

(A) In order to pattern the wiring layer in the non-chip region, the non-chip region may be exposed. That is, the exposure of the non-chip region may be applied to the case where a dummy wiring pattern is formed in the non-chip region.

(B) In the case of performing the damascene method, the non-chip region may be exposed in order to form a dummy opening in the interlayer insulating layer in the non-chip region.

[Brief description of the drawings]

FIG. 1 is a plan view schematically showing a photomask.

FIG. 2 is a view schematically showing an exposure apparatus.

FIG. 3 is a plan view showing an arrangement relationship between the blind and a photomask when viewed from above the blind.

FIG. 4 is a cross-sectional view schematically showing a manufacturing process of the semiconductor device according to the present embodiment.

FIG. 5 is a plan view for explaining an exposed area of the semiconductor wafer.

FIG. 6 is a plan view showing an arrangement relationship between a blind and a photomask in exposure of an area A10 in FIG. 5;

FIG. 7 is a cross-sectional view schematically showing a manufacturing process of the semiconductor device according to the present embodiment.

FIG. 8 is a cross-sectional view schematically showing a manufacturing process of the semiconductor device according to the present embodiment.

FIG. 9 is a cross-sectional view schematically showing a manufacturing step of the semiconductor device according to the present embodiment.

FIG. 10 is a cross-sectional view schematically showing a manufacturing step of the semiconductor device according to the present embodiment.

FIG. 11 is a cross-sectional view schematically showing a manufacturing step of the semiconductor device according to the present embodiment.

FIG. 12 is a cross-sectional view for explaining a problem when a step of exposing a non-chip region is not included.

FIG. 13 is a plan view showing an arrangement pattern of dummy element formation regions in the example.

FIG. 14 is a graph showing the distribution of the thickness of the insulating layer remaining on the polishing stopper layer in Examples and Comparative Examples.

FIG. 15 is a plan view showing a photomask according to a conventional example.

FIG. 16 is a plan view for explaining an exposed range of a semiconductor wafer according to a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Semiconductor wafer 12 Pad layer 14 Polishing stopper layer 20 Chip area 22 Non-chip area 30 Trench element isolation area 32 Trench 34 Trench oxide film 36 Element formation area 40 Dummy trench element isolation area 42 Dummy trench 46 Dummy element formation area 50 Trench insulating layer 52 Insulating layer 60 Convex part 200 Photomask 210 Effective pattern area 220 Dummy pattern area 222 First dummy pattern part 224 Second dummy pattern part 226 Third dummy pattern part 228 Fourth dummy pattern part 230 First light shielding Band 240 second light-blocking band 300 exposure device 310 light source 320 blind 322 first movable blind 324 second movable blind 326 third movable blind 328 fourth movable blind 332 first blind Command driving unit 334 second blind driver 336 third blind driver 338 fourth blind driver 340 reduction projection lens 350 exposure object R1 resist layer

Claims (10)

[Claims] 1. A photomask having an effective pattern area and a dummy pattern area provided at least partially around the effective pattern area. 2. The photomask according to claim 1, wherein the dummy pattern region is formed along an outer periphery of the effective pattern region. 3. The photomask according to claim 2, wherein the dummy pattern region is continuous. 4. The photomask according to claim 1, wherein a light-shielding band is provided between the effective pattern area and the dummy pattern area. 5. An exposure apparatus including a light source and a photomask, wherein the photomask is the photomask according to claim 1. Description: 6. The exposure apparatus according to claim 5, wherein the exposure apparatus further includes a blind, wherein the blind is provided between the light source and the photomask. 7. An exposure method for exposing an object to be exposed using a light source and a photomask, wherein the photomask is the photomask according to any one of claims 1 to 4. . 8. The exposure method according to claim 7, wherein a blind is provided between the photomask and the light source. 9. A method for manufacturing a semiconductor device using the exposure apparatus according to claim 5, comprising a step (A) of exposing a resist layer formed on a semiconductor wafer to the semiconductor device. The wafer includes a chip region and a non-chip region, and the step (A) includes transferring the pattern of the effective pattern region in the chip region and simultaneously transferring the pattern of the dummy pattern region in the non-chip region. A method for manufacturing a semiconductor device, comprising: 10. The method according to claim 9, wherein the step (A) is a step for further forming a trench, and the pattern transfer of the dummy pattern area in the non-chip area is performed by using a dummy in the non-chip area. A method for manufacturing a semiconductor device, wherein a trench is formed.