JP2001229696A - Semiconductor integrated circuit and its test method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve such a problem that in a large scale semiconductor integrated circuit, such constitution is well known that the number of test terminals is decreased by inputting an output signal to an exclusive OR circuit to decrease many terminals for test. However, an output of a signal is not varied and it can not be discriminated whether a test is performed or not, and also fault of even number pieces cannot be discriminated. SOLUTION: A semiconductor integrated circuit is provided with a memory, a logic gate outputting an exclusive OR signal outputted from the prescribed plural memory output terminals, a first selector selecting one signal from output signals of the memory and outputting it, and a second selector selecting either of an output of an exclusive OR signal and an output of the first selector and outputting it. The memory has eight output terminals, and output signals 0, 1, 2 and 4 are inputted to one side of a logic gate, output signals 3, 5, 6 and 7 are inputted to the other side of the logic gate out of output signals 0, 1, 2, 3, 4, 5, 6 and 7.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit and a test method thereof, and more particularly to a semiconductor integrated circuit capable of reducing the number of terminals required for testing a mounted memory and a test method thereof.

[0002]

2. Description of the Related Art In recent years, high integration and large scale of semiconductor integrated circuits have been rapidly advanced. Accordingly, the number of terminals (pins) per chip has increased, and various problems have occurred. For example, in the conventional semiconductor integrated circuit as shown in FIG. 3, it is necessary to monitor eight output signals of the memory 13 as they are, so that eight test signal terminals are required. When the number of memory test terminals increases, an LSI tester corresponding to the increase is required, and the test cost increases.

On the other hand, a configuration as shown in FIG. 4 has been proposed to reduce the number of test terminals. The memory 13 in the semiconductor integrated circuit has two test output terminals for testing eight output signals output to the input control signal group 12. That is, in this configuration, the output signals 0, 1,
2, 3 are connected to the exclusive logic gate 10, and the output signals 4,
5, 6, and 7 are connected to the exclusive logic gate 11. Here, the output signals 1 of these exclusive logic gates 10 and 11 are
The presence or absence of a defective signal is determined by 4 and 15, and a test is performed at two terminals.

[0004]

However, in the configuration shown in FIG. 4, when the output signal of the memory 13 has four types of output patterns (PAT) normally used as shown in FIG.
If the exclusive OR is simply taken, the output signals 13 and 14 each have a value of 0, and if there is no failure, it cannot be externally confirmed whether or not the test is being performed. In addition, there is a problem that even if it is detected that there is a failure, a failed output signal cannot be specified.

The present invention solves such a problem and can reduce the number of terminals required at the time of a test. At the same time, it can be confirmed that an output signal changes externally, and the presence or absence of a failure can be determined in bit units. The purpose is to enable analysis.

[0006]

According to the present invention, there is provided a semiconductor integrated circuit comprising: a memory having a plurality of output terminals; a logic gate for outputting an exclusive OR signal of a plurality of output signals of the memory; A first selector for selecting and outputting one signal from a memory output signal input to the logic gate; and a second selector for selecting and outputting either an exclusive OR signal output or an output of the first selector by an external signal. 2 selectors.

The logic gate is connected to four output terminals, and two logic gates, two first selectors, and one second selector can be arranged. The memory has eight output terminals, and among the output signals 0, 1, 2, 3, 4, 5, 6, and 7, one of output signals 0, 1, 2, and 4 is output. , And the output signals 3, 5, 6, and 7 are input to the other logic gate.

In the method for testing a semiconductor integrated circuit according to the present invention, a plurality of types of signal patterns are output from a plurality of output terminals of a memory, and an exclusive OR signal of a plurality of output signals constituting each signal pattern is provided with a predetermined expectation. A predetermined signal pattern is output from a plurality of output terminals of the memory, and each output signal constituting the signal pattern is sequentially compared with a predetermined expected value. Each output signal forming a certain signal pattern with the exclusive OR signal is switched by a selector controlled by an external signal and output from the same terminal. The output signals 0, 1, 2, 3 and the output signals 4, 5, 6, 7 output from the eight output terminals of the memory form the same signal pattern, respectively.
The exclusive OR signals 2, 4 and the exclusive OR signals of the output signals 3, 5, 6, 7 are compared with a predetermined expected value.

According to the present invention configured as described above, it is possible to confirm that the output signal changes externally during the test, and to detect the presence or absence of a failure for each bit.

[0010]

Embodiments of the present invention will be described below with reference to the drawings.

As shown in FIG. 1, the semiconductor integrated circuit of the present invention is controlled by an input control signal group 12 and outputs output signals 0 to 7
, An exclusive logic gate 10 to which output signals 0, 1, 2, and 4 are input, and output signals 0, 1, and
A selector 16 having data inputs 2 and 4 as test signals and test signals 20 and 21 as control signals; an output signal of the exclusive logic gate 10 and an output signal of the selector 16 as inputs, a test signal 22 as a control signal and an output signal 8 as output Selector 17
Is provided. An exclusive logic gate 11 having output signals 3, 5, 6, 7 as inputs; a selector 18 having output signals 3, 5, 6, 7 as data inputs and test signals 20, 21 as control signals; 11 output signals and selector 1
8 is provided with a selector 19 which receives the output signal of 8 as an input and outputs the output signal 9. In other words, the number of test terminals originally required eight is reduced to two.

Next, the test operation of the semiconductor integrated circuit will be described with reference to FIGS.

First, the case where the test signals 20, 21, 22 are 0, 0, 1 respectively will be described. In this case, since the test signal for controlling the selectors 17 and 19 is 1, both selectors output the outputs of the exclusive logic gates 10 and 11 to the output terminals 8 and 9, respectively.

The memory 13 is controlled to be read or written by the input control signal 12 as in the normal operation, and the output signals 0 to 7 change. Usually, in a memory test, a marching or checker test is performed, so that the output signals 0 to 7 are generally 00h, FFh, 55h, and AA.
Take the value of h. When the output signal pattern is 00h, all the output signals 0 to 7 take a value of 0. Therefore, the outputs of the exclusive logic gates 10 and 11 both become 0, and are output to the output terminals 8 and 9 as they are. When the output signal pattern is FFh, all of the output signals 0 to 7 take a value of 1. Therefore, the outputs of the exclusive logic gates 10 and 11 both become 0, and are output to the output terminals 8 and 9 as they are.

When the output signal patterns 0 to 7 are 55h,
Since the output signals 0, 1, 2, and 4 are input to the exclusive logic gate 10 and the output signals 3, 5, 6, and 7 are input to the exclusive logic gate 11, the output signals 8, 9 of both exclusive logic gates are Each has a value of 1. The output signal patterns 0 to 7 are A
At the time of Ah, the output signals 8 and 9 of both exclusive logic gates each take the value of 1 for the same reason.

From the viewpoint of fault detection, when an odd number (1 or 3) of the input signals of the exclusive logic gate 10 or the exclusive logic gate 11 has a defect, it can be determined as normal by the output signals 8 and 9 as a defect. However, when there is an even number (2 or 4) of defects, the defect cannot be detected.

For example, in PAT4 of FIG. 2 (when the signal pattern is AAh), the current output signals 0, 1, 2, 4
Are 0, 1, 0, 0 in this order, so that the output signal 8 is 1. Next, when the output signal 0 fails due to a failure and outputs a value of 1, the output signals 0, 1, 2, and 4 are sequentially
1, 1, 0, 0, so that the output signal 8 is 0
Becomes Therefore, in this case, the actual output value becomes 0 with respect to the expected value 1 of the output signal 8, so that an internal defect can be found in the output signal 8.

Next, when the output signals 0 and 2 fail due to a failure and both output a value of 1, the output signals 0, 1, 2, 2
4 takes values 1, 1, 1, 0 in order, and as a result, the output signal 8 becomes 1. Accordingly, in this case, since the actual output value is also 1 with respect to the expected value 1 of the output signal 8, an internal defect cannot be found in the output signal 8.

However, in a series of test patterns, the output signals 8 and 9 have both values of 1 and 0, respectively, and it can be confirmed that the test is being performed.

Next, when the test signals 20, 21, 22 are x,
The case of x, 0 will be described. Since the test signal 22 is 0, the selectors 17 and 19 correspond to the selectors 16 and 18 respectively.
Are output as output signals 8 and 9. Test signal 2
0, 21 allows the selector 16 to output signals 0, 1,
One signal is selected from 2 and 4. The selector 18 similarly selects one signal from the output signals 3, 5, 6, and 7. In this manner, failure analysis can be performed on a bit-by-bit basis.

[0021]

In a semiconductor integrated circuit equipped with a memory, the output signal of the memory may be changed externally during a test by exclusively combining the output signals of the memory and replacing some of the output signals. Confirmation can be made and the required number of terminals can be reduced. Further, by switching the mode, it is possible to analyze the memory in bit units.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration example of a semiconductor integrated circuit of the present invention.

FIG. 2 is a diagram showing states of a test signal and an output signal of the semiconductor integrated circuit.

FIG. 3 is a diagram showing a configuration example of a conventional semiconductor integrated circuit.

FIG. 4 is a diagram showing a configuration example of a conventional semiconductor integrated circuit.

FIG. 5 is a diagram showing a state of an output signal of a conventional semiconductor integrated circuit.

[Explanation of symbols]

 Reference Signs List 10 exclusive logic gate 11 exclusive logic gate 12 input control signal 13 memory 16, 17, 18, 19 selector 20, 21, 22 test signal

Claims (8)

[Claims] 1. A memory having a plurality of output terminals, a logic gate for outputting an exclusive OR signal of a plurality of output signals of the memory, and one signal from the memory output signal input to the logic gate. A semiconductor integrated circuit comprising: a first selector for selecting and outputting; and a second selector for selecting and outputting one of an output of the exclusive OR signal and an output of the first selector. . 2. The semiconductor integrated circuit according to claim 1, wherein said logic gate is connected to four output terminals of said memory. 3. The semiconductor integrated circuit according to claim 1, wherein each of said logic gate, said first selector and said second selector is arranged two by two. 4. The semiconductor integrated circuit according to claim 1, wherein said first and second selectors perform selection control by an external signal. 5. The memory has eight output terminals, and output signals 0, 1, 2, 3, 3, respectively output from the respective output terminals.
4. The output signal according to claim 3, wherein output signals 0, 1, 2, 4 are input to one of the logic gates, and output signals 3, 5, 6, 7 are input to the other logic gate. Semiconductor integrated circuit. 6. A plurality of types of signal patterns are output from a plurality of output terminals of a memory, and an exclusive OR signal of a plurality of output signals constituting each signal pattern is compared with a predetermined expected value. A method for testing a semiconductor integrated circuit, comprising: outputting a predetermined signal pattern from an output terminal; and sequentially comparing each output signal constituting the signal pattern with a predetermined expected value. 7. The semiconductor integrated circuit according to claim 6, wherein said exclusive OR signal and each output signal forming said fixed signal pattern are switched by a selector controlled by an external signal and output from the same terminal. Test method. 8. With respect to output signals 0, 1, 2, 3, 4, 5, 6, 7 output from eight output terminals of a memory, output signals 0, 1, 2, 3, and output signals 4, 5 , 6, and 7 form the same signal pattern, and output signals 0,
7. The test method for a semiconductor integrated circuit according to claim 6, wherein the exclusive OR signals of 1, 2, 4 and the exclusive OR signals of the output signals 3, 5, 6, 7 are compared with a predetermined expected value.