JP2001229679A - Ferroelectric storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a ferroelectric memory of a 1T/1C type in which a ferroelectric capacitor of a memory for reference potential hardly deteriorates. SOLUTION: A capacitor 112 for data is saturation-polarized in accordance with '0' or '1' of data, and a capacitor 112 for reference potential is partially polarized. Potentials in accordance with polarization are read out at bit lines BL1, BL2 by turning on transistors 111, 121 and turning a plate line voltage to Vcc. A sense amplifier 140 compares a potential of the bit line BL1 with a potential of the BL2, amplifies the higher potential to Vcc and amplifies the lower potential to zero volt. Data of the capacitor 112 is rewritten in the bit line BL1 after amplification, data of the capacitor 122 is rewritten in a reference potential setting circuit 150. Deterioration of this capacitor 122 can be suppressed by partially polarizing the capacitor 122 for reference potential, that is, by not saturation-polarizing it.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ferroelectric memory device for storing binary data according to the polarity of polarization of a ferroelectric capacitor, and more particularly to a 1T / 1C (1 transistor / 1 capacitor) type ferroelectric memory device.

[0002]

2. Description of the Related Art A conventional ferroelectric memory stores binary data by causing a ferroelectric capacitor provided in a memory cell to be positively or negatively saturated and polarized. The following documents disclose ferroelectric memories, for example.

"FRAMIC Card Technology Hidemi Takasu, Toshinori Takuma 1999 Science Forum Company, pp. 35-40" Ferroelectric memories include 1T / 1C type ferroelectric memories.
A 2T / 2C type is known.

In a 1T / 1C type ferroelectric memory,
One transistor and one ferroelectric capacitor are used for one bit of data. In this type of ferroelectric memory, one reference potential memory cell is provided for each bit line. "1" or "0" is stored in the reference potential memory cell as reference data. The storage value of the data memory cell is determined by detecting whether the potential read from the data memory cell matches the potential read from the reference potential memory cell.

On the other hand, in a 2T / 2C type ferroelectric memory, two transistors and two ferroelectric capacitors are used for 1-bit data. That is, in this type of ferroelectric memory, the stored value is determined using complementary data stored in a pair of ferroelectric capacitors.

[0006]

In a 1T / 1C type ferroelectric memory, the frequency of access to a memory cell for reference potential is much higher than the frequency of access to a memory cell for data. There are drawbacks.

For example, consider a case where 256 data memory cells are connected to one bit line and data stored in each data memory cell is read. In this case, each data memory cell is accessed once, whereas the reference potential memory cell is accessed 256 times.

The high access frequency to the reference potential memory cell causes deterioration of the ferroelectric capacitor provided in the reference potential memory cell. Then, due to this deterioration, the amount of polarization of the ferroelectric capacitor is reduced, so that the reference potential applied to the bit line is reduced, and therefore, the reliability of read data is reduced.

On the other hand, in the 2T / 2C type ferroelectric memory, the storage value is determined by using the complementary data, so that the frequency of accessing a specific memory cell does not become extremely high. There is no disadvantage as in the case of the 1T / 1C type. However, the 2T / 2C type ferroelectric memory has a disadvantage that the area of the memory cell array is large.

For these reasons, there has been a demand for a 1T / 1C type ferroelectric memory in which the ferroelectric capacitor of the reference potential memory cell hardly deteriorates.

[0011]

SUMMARY OF THE INVENTION The present invention provides a data memory cell having a data ferroelectric capacitor and outputting a potential corresponding to the polarization of the data ferroelectric capacitor to a data bit line; A reference potential memory cell having a ferroelectric capacitor for reference potential and outputting a potential corresponding to the polarization of the ferroelectric capacitor for reference potential to a bit line for reference potential; A data writing means for negatively polarizing the polarization, a reference potential setting means for partially or positively polarizing the ferroelectric capacitor for reference potential to positive or negative, and a magnitude of the potential of the data bit line and the potential of the reference potential bit line. A sense amplifier that determines the storage data of the data memory cell by detecting the relationship.

In the ferroelectric memory device according to the present invention, the ferroelectric capacitor for reference potential is not polarized in saturation but is partially polarized. That is, in the present invention, the absolute value of the polarization amount of the ferroelectric capacitor for reference potential is made smaller than the absolute value of the polarization amount of the ferroelectric capacitor for data. Thereby, the influence of the deterioration of the ferroelectric capacitor for reference potential can be suppressed.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the size, shape, and arrangement of each component are only schematically shown to an extent that the present invention can be understood, and numerical conditions described below are merely examples. .

First Embodiment A ferroelectric memory according to a first embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 is a circuit diagram schematically showing a structure of a ferroelectric memory according to this embodiment.

As shown in FIG. 1, this ferroelectric memory includes a data memory cell 110, a reference potential memory cell 120, an equalizing circuit 130, a sense amplifier 140,
The reference potential setting circuit 150, the data bit line BL1,
Bit line BL2 for reference potential, word line WL for data
1, a word line WL2 for a reference potential and a plate line PL.

Bit lines BL1 and BL2, word lines WL
A plurality of 1, 1 and WL2 and plate lines PL are respectively formed in one ferroelectric memory. However, in FIG. 1, for simplicity, one each is shown.

The data memory cell 110 includes one transistor 111 and one ferroelectric capacitor 112. The transistor 111 has a gate connected to the data word line WL1, a source connected to one end of the ferroelectric capacitor 112, and a drain connected to the data bit line BL1. Ferroelectric capacitor 112
Is connected to the plate line PL. The data memory cell 110 usually has one data bit line BL.
Many are connected to one, but only one is shown in FIG.

The reference potential memory cell 120 includes one transistor 121 and one ferroelectric capacitor 122.
And The transistor 121 has a gate connected to the reference potential word line WL2, a source connected to one end of the ferroelectric capacitor 122, and a drain connected to the reference potential bit line BL2. The other end of ferroelectric capacitor 112 is connected to plate line PL. In this embodiment, as the ferroelectric capacitor 122,
Ferroelectric capacitor 111 of data memory cell 110
The same structure and the same size can be used. Only one reference potential memory cell 120 is connected to one reference potential bit line BL2.

The equalizing circuit 130 includes two transistors 131 and 132. The transistor 131 is
The equalizing signal EQ is input from the gate, the source is connected to the data bit line BL1, and the drain is grounded. The transistor 132 receives the equalizing signal EQ from the gate, the source is connected to the reference potential bit line BL2, and the drain is grounded.

When the signal SA is at a high level, the sense amplifier 140 compares the potentials of the bit lines BL1 and BL2. Then, the higher bit line potential is amplified to the power supply potential Vcc, and the lower bit line potential is amplified to zero volt.

The reference potential setting circuit 150 is used to partially polarize the ferroelectric capacitor 122 for generating a reference potential. The reference potential setting circuit 150 controls the control signal R
When V is at a high level, a predetermined set potential is output.
Due to the potential difference between the set potential and the potential of the plate line PL, the ferroelectric capacitor 122 is partially polarized. As will be described later, it is desirable that the polarization amount of the ferroelectric capacitor 122 be about half of the saturation polarization.

Next, the operation principle of the ferroelectric memory shown in FIG. 1 will be described.

First, the operation principle of the data memory cell 110 will be described.

FIG. 2 is a characteristic diagram for explaining the state shift of the ferroelectric capacitor 112. The horizontal axis represents the voltage V [volt], and the vertical axis represents the polarization Q [C]. As shown in FIG. 2, the relationship between the voltage V and the polarization Q draws a hysteresis curve H. The slope of the hysteresis curve H indicates the capacitance [q / V] of the ferroelectric capacitor 112.

When no voltage is applied between the terminals of the data capacitor 112, the polarization (saturation polarization) of the capacitor 112 is P0 or P1. In this embodiment, P0 is a stored value "0", and P1 is a stored value "1".
And Further, since the reference potential capacitor 122 is partially polarized, the polarization of the capacitor 122 when no voltage is applied between the terminals is, for example, Pr.

When the voltage Vcc is applied to the plate line PL with the transistors 111 and 121 turned on, a potential is output to the bit lines BL1 and BL2. At this time, when the polarization is P0, the potential of the bit line BL1 becomes a straight line Cb0.
When the polarization is P1, it coincides with the V coordinate V1 at the intersection between the straight line Cb1 and the hysteresis curve P1 -P2. Here, the straight line Cb0 is a straight line that passes through the point (−Vcc, P0) and has an inclination θ, and the straight line Cb1 is a point (Vcc,
P1) and has a slope of θ. θ is determined according to the capacitance of bit line BL1. When the voltage Vcc is applied to the plate line PL, the potential of the bit line BL2 is represented by a straight line Cbr and a hysteresis curve Pr.
It coincides with the V coordinate Vr at the intersection with -P2. The straight line Cbr is
It is a straight line passing through the point (-Vcc, Pr) and having an inclination of θ with respect to the V axis. In this embodiment, bit lines BL1, B
The capacitance of L2 is the same. Therefore, the slope of the straight line Cbr is the same as the slope θ of the straight lines Cb0 and Cb1. That is, in the ferroelectric memory according to this embodiment, since the reference potential capacitor 122 is partially polarized, the potential Vr of the bit line BL2 always becomes V0 <Vr <V1.

Next, a read operation and a rewrite operation of the ferroelectric memory shown in FIG. 1 will be described with reference to a timing chart of FIG.

First, at time t0, the equalizing signal EQ is set to the high level to turn on the transistors 131 and 132. Thereby, the potentials of the bit lines BL1 and BL2 are charged to zero volt.

At time t1, the equalizing signal EQ is set to a low level to set the bit lines BL1 and BL2 in a floating state, and the potentials of desired word lines WL1 and WL2 are set to a high level to set the transistors 111 and Turn on 121. Thereby, capacitors 112 and 122 are connected to bit lines BL1 and BL2.

At time t2, the power supply voltage Vcc is applied to the plate line PL. Thereby, the bit lines BL1, BL2
, A read potential is output. As described above, the potential V0 or the potential V1 is read out to the bit line BL1,
The potential Vr is read to the bit line BL2 (see FIG. 2).

At time t3, when the potential of the signal SA is changed to a high level, the sense amplifier 140 is activated. As described above, sense amplifier 140 amplifies the higher bit line potential to power supply potential Vcc and the lower bit line potential to zero volts. Therefore, when the potential of bit line BL1 at time t2 is V0, the potential of bit line BL1 is amplified to zero volts, and bit line BL2 is set to Vcc.
Is amplified. On the other hand, bit line BL1 at time t2
, The potential of bit line BL1 is amplified to Vcc, and the potential of bit line BL2 is amplified to 0 volt.

At time t4, the word line WL2 is set to low level, and the signal RV is set to high level. As a result, the reference potential capacitor 122 is connected to the bit line BL2
And the output potential of the reference potential setting circuit 150 is applied. Then, rewriting to the reference potential capacitor 122 is performed. As described above, the output potential of reference potential setting circuit 150 is set to a potential at which reference potential capacitor 122 is partially polarized.

When the stored value of the data capacitor 112 is “0”, the rewriting of the capacitor 112 is executed in parallel with the rewriting of the reference potential capacitor 122. When the stored value of the data capacitor 112 is "0", the potential of the bit line BL1 becomes zero volt at time t3. Therefore, the voltage between the terminals of the data capacitor 112 becomes -Vcc, and "0" is rewritten to this capacitor 112 (see point P2 in FIG. 2). When the stored value of the data capacitor 112 is “1”, the voltage between terminals becomes zero volt, so that rewriting is not performed.

Subsequently, at time t5, the potential of the plate line PL is returned to the low level. When the storage value of the data capacitor 112 is “1”, the plate line PL is returned to a low level, thereby executing rewriting. When the stored value of the data capacitor 112 is “1”, the voltage between the terminals of the data capacitor 112 becomes + Vcc when the potential of the plate line PL becomes low level (that is, zero volt). Is rewritten (see point P3 in FIG. 2).

At time t6, the signal SA goes low, and at time t7, the equalization signal EQ goes high. As a result, the bit lines BL1 and BL2 become low level. Therefore, the voltage between the terminals becomes zero volt, and the polarization of the data capacitor 112 becomes P0 or P1.
(See FIG. 2).

At time t8, the equalizing signal EQ is set to the low level, and at time t9, the potential of the word line WL1 and the potential of the signal RV are set to the low level, and the operation is completed.

As described above, in the ferroelectric memory of this embodiment, the reference potential capacitor 122 is partially polarized. This partial polarization must be set so that the difference between the potential of the bit line BL1 and the potential of the bit line BL2 is larger than the sensitivity of the sense amplifier 140. That is, assuming that the allowable range of the partial polarization is Pi <Pr <Pj, Pi and Pj are determined as follows.

As shown in FIG. 4, the potential of the bit line BL2 when the polarization of the reference potential capacitor 122 is Pi is Vi, and the potential of the bit line BL2 when the polarization of the reference potential capacitor 122 is Pj. Vj, and the minimum detection potential difference of the sense amplifier 140 is Vmin. At this time, Vi and Vj must satisfy the following two equations.

| Vi |-| V1 |> Vmin | V0 |-| Vj |> Vmin That is, even if the partial polarization Pr varies within a range satisfying these equations, the ferroelectric memory operates normally. However, in order to use a low-sensitivity sense amplifier 140, it is desirable that the partial polarization Pr be about half of the saturation polarization.

Since the state of partial polarization is unstable, the amount of polarization of the reference potential capacitor 122 changes to zero (Q = 0) with time. The ferroelectric memory according to this embodiment operates normally if V0 <Vr <V1 and the above two equations are satisfied, so that no problem occurs even if the polarization amount is reduced.

The reference potential capacitor 122 includes:
Since the polarization inversion is repeated due to the fluctuation of the potential of the bit line BL2 (amplification to the power supply potential Vcc or zero volt) and the rewriting operation, a fating (that is, a phenomenon in which the polarization of the capacitor is reduced) occurs. However, in the ferroelectric memory according to this embodiment, V0 <Vr <V1
If the above two equations are satisfied, the operation is normal, so that no problem occurs even if the amount of polarization is reduced.

In addition, since the reference potential capacitor 122 is partially polarized, the influence of imprint (that is, a failure mode in which the hysteresis characteristic shifts in the holding polarization direction) can be reduced.

Further, the ferroelectric memory according to this embodiment drives the reference potential cell 120 at a low voltage. As a result, the reliability of the memory can be improved. This is very important in a reference potential cell that is frequently accessed.

The reference potential cell may be provided for each memory cell block. In order to make the capacitance of the reference potential bit line BL2 the same as that of the data bit line BL1, for example, a dummy cell may be used. In this case, the capacitance of the reference potential bit line BL2 can be adjusted by adjusting the size and the number of the dummy cells.

Second Embodiment Next, a ferroelectric memory according to a second embodiment of the present invention will be described with reference to FIGS.

FIG. 5 is a circuit diagram schematically showing the structure of the ferroelectric memory according to this embodiment.

In FIG. 5, the components denoted by the same reference numerals as those in FIG. 1 indicate the same components as those in FIG. The ferroelectric memory of FIG. 5 includes a transistor 201 for writing a reference potential. This transistor 20
In No. 1, a gate is connected to a word line, a source is connected to a bit line BL3, and a drain is connected to one end of the ferroelectric capacitor 122.

Hereinafter, a read operation and a rewrite operation of the ferroelectric memory shown in FIG. 5 will be described with reference to FIGS. FIG. 6 is a timing chart showing the operation of the ferroelectric memory. FIGS. 7A and 7B are state shift diagrams of the reference potential capacitor 122. FIG. 7A shows a case where the stored value of the data capacitor 112 is “0”, and FIG. 7B shows a state where the stored value of the data capacitor 112 is “1”. Is shown.

First, at time t0, the equalizing signal EQ is set to the high level to turn on the transistors 131 and 132, thereby charging the bit lines BL1 and BL2 to zero volts. At this time, capacitors 112 and 122
Is zero volt, the polarization of the reference potential capacitor 122 is in the state shown by the point 0 in FIGS. 7A and 7B.

At time t 1, the equalizing signal EQ is set to the low level to set the bit lines BL 1 and BL 2 in the floating state, and the potentials of the word lines WL 1 and WL 2 are set to the high level to turn on the transistors 111 and 121 of the memory cells 110 and 120. Turn on. Thereby, capacitors 112 and 122 are connected to bit lines BL1 and BL2.

At time t2, the power supply voltage Vcc is applied to the plate line PL. Thereby, the bit lines BL1,
The read potential is output to BL2. At this time, a voltage between terminals is generated in the capacitors 112 and 122. The ratio between the read voltage of the data bit line BL1 and the voltage between the terminals of the data capacitor 112 is determined by the capacitance ratio between the bit line BL1 and the capacitor 112. Similarly, the ratio of the read voltage of the reference potential bit line BL2 to the inter-terminal voltage of the reference potential capacitor 122 is:
It is determined by the ratio of the two capacitances. As in the first embodiment, the read potential of the bit line BL1 is
The data written to the data capacitor 112 (FIG. 2)
(See P0 and P1 of FIG. 2), and becomes V0 or the potential V1. The read potential of the bit line BL2 becomes Vr, as in the first embodiment. The generation of the inter-terminal voltage causes the polarization of the reference potential capacitor 122 to be in the state shown by the point 2 in FIGS. 7A and 7B.

At time t3, when the potential of the signal SA is changed to the high level, the sense amplifier 140 is activated. As described above, sense amplifier 140 amplifies the higher bit line potential to power supply potential Vcc and the lower bit line potential to zero volts.

That is, the bit line BL at time t2
1 is V0 (that is, the data capacitor 1
12 is "0"), the potential of the bit line BL1 is amplified to zero volts, and the bit line BL2 is set to Vcc.
Is amplified. Therefore, the reference potential capacitor 12
Since the voltage between the terminals 2 becomes zero volt, the polarization of the capacitor 122 is in the state shown by the point 3 in FIG.

On the other hand, when the potential of bit line BL1 at time t2 is V1 (ie, data capacitor 112).
Is "1"), the potential of the bit line BL1 is amplified to Vcc and the bit line BL2 is amplified to 0 volt. Therefore, since the voltage between the terminals of the reference capacitor 122 becomes -Vcc, the polarization of the capacitor 122 becomes a state shown by a point 3 in FIG. 7B.

At time t4, the word line WL2 is set to low level, and the word line WL3 is set to high level. Thereby, the reference potential capacitor 122 is connected to the bit line BL.
2 and connected to the bit line BL3. Further, at time t4, a set potential (here, Vcc / 2) is supplied to the bit line BL3. As a result, rewriting to the reference potential capacitor 122 is performed.

The voltage between the terminals of the reference potential capacitor 122 is -Vcc / 2. Therefore, when the stored value of the data capacitor 112 is “0”, the polarization of the capacitor 122 is in the state shown by the point 4 in FIG. On the other hand, when the storage value of the data capacitor 112 is “1”, the polarization of the capacitor 122 of the reference potential capacitor 122 is in a state shown by a point 4 in FIG. 7B.

As in the first embodiment, when the stored value of the data capacitor 112 is “0”, rewriting of the capacitor 112 is performed in parallel with rewriting of the reference potential capacitor 122. Be executed.

Subsequently, at time t5, the potential of the plate line PL is returned to the low level. As in the first embodiment, when the stored value of the data capacitor 112 is “1”, the plate line PL is returned to a low level, thereby executing rewriting.

By returning the potential of the plate line PL to the low level, the voltage between the terminals of the reference potential capacitor 122 becomes + Vcc / 2. Therefore, the polarization of the reference potential capacitor 122 is in a state shown by a point 5 in FIGS. 7A and 7B. That is, the state of polarization at time t5 is independent of the stored value of the data capacitor 112.
Will be the same.

At time t6, the signal SA is set to low level. Thereby, the potentials of the bit lines BL1 and BL2 become zero volt.

Further, at time t7, the word line WL1 is set to the low level, and immediately thereafter, the plate line PL is set to the high level. As a result, the data capacitor 112 is disconnected from the word line WL1 with the terminal voltage being zero volts, and the terminal voltage of the reference potential capacitor 122 becomes -Vcc / 2. Since the voltage between the terminals of the data capacitor 112 is zero volt, it is maintained in the state indicated by P0 or P1 in FIG. On the other hand, the reference potential capacitor 1
Reference numeral 22 in FIG. 7A indicates that the terminal voltage is -Vcc / 2,
The state shown by the point 7 in FIG.

At time t8, the potential of the plate line PL is changed to V
cc / 2. Thereby, the reference potential capacitor 12
FIG. 7A shows that the voltage between terminals becomes zero volt,
The state shown by the point 8 in FIG.

At time t9, the word line WL3 is set to low level. Thus, the reference potential capacitor 122
It is disconnected from the bit line BL3 when the terminal voltage is zero volt.

Thereafter, at time t10, the plate line PL and the bit line BL3 are set to low level, and the operation is completed.

As described above, the ferroelectric memory according to the present embodiment uses the reference potential capacitor 122 with partial polarization. Since the partial polarization state has poor polarization retention characteristics, the polarization amount of the reference potential capacitor 122 is
It becomes smaller as the elapsed time from writing to reading is longer. In the ferroelectric memory according to this embodiment, as shown in FIG. 8, a read margin is ensured even when the polarization amount becomes zero (Q = 0), and therefore, no inconvenience occurs due to a decrease in the polarization amount.

Further, according to the reference potential capacitor 122, the influence of the fertig can be reduced.
When the memory cell is deteriorated due to the fertility, the read potential V0 in the non-inversion direction hardly changes, but the read potential V1 in the inversion direction changes in a direction approaching V0. On the other hand, according to the ferroelectric memory according to the present embodiment, by setting the magnitude of the reference potential Vr closer to V0 than the middle between V0 and V1, the influence of the fertig is reduced. It is possible.

In addition, according to this embodiment, since the reference potential capacitor 122 is partially polarized, the reference potential capacitor 122 is saturated (ie, is polarized to the state of P0 or P1 in FIG. 2). The influence of imprint can be reduced as compared with the case of FIG.

Further, in the ferroelectric memory according to this embodiment, the reliability of the memory can be improved by driving the reference potential cell 120 at a constant voltage. This is because in a reference potential cell having a large number of accesses,
Very important.

The reference potential cell may be provided one for each memory cell block. In order to make the capacitance of the reference potential bit line BL2 the same as that of the data bit line BL1, for example, a dummy cell may be used. By adjusting the size and number of the dummy cells, the capacitance of the reference potential bit line BL2 can be adjusted. As shown in FIG. 9, by increasing the capacitance of the reference potential bit line BL2, the slope of the straight line Cbr can be increased and the magnitude of the reference potential Vr can be closer to V0. Thereby, as described above, the influence of the fertig can be reduced.

Third Embodiment Next, a ferroelectric memory according to a third embodiment of the present invention will be described with reference to FIGS. 5, 10, and 11. FIG.

The structure of the ferroelectric memory according to this embodiment is the same as that of the ferroelectric memory according to the second embodiment, and a description thereof will be omitted.

The ferroelectric memory according to the present embodiment
Read and rewrite operations are different from those of the ferroelectric memory according to the above-described second embodiment.

The read operation and the rewrite operation of the ferroelectric memory according to this embodiment will now be described with reference to FIG.
This will be described with reference to FIG. FIG. 10 is a timing chart showing the operation of the ferroelectric memory. Also,
FIGS. 11A and 11B are state shift diagrams of the reference potential capacitor 122. FIG. 11A illustrates a case where the stored value of the data capacitor 112 is “0”, and FIG. 11B illustrates a case where the stored value of the data capacitor 112 is “1”. Is shown.

First, at time t0, the equalizing signal EQ is set to a high level to turn on the transistors 131 and 132, thereby charging the bit lines BL1 and BL2 to zero volts. At this time, capacitors 112 and 122
Is zero volt, the polarization of the reference potential capacitor 122 is in the state shown by the point 0 in FIGS. 11A and 11B.

At time t 1, the equalizing signal EQ is set to the low level to set the bit lines BL 1 and BL 2 in the floating state, and the potentials of the word lines WL 1 and WL 2 are set to the high level to turn on the transistors 111 and 121 of the memory cells 110 and 120. Turn on. Thereby, capacitors 112 and 122 are connected to bit lines BL1 and BL2.

At time t2, power supply voltage Vcc is applied to plate line PL. Thereby, the bit lines BL1,
The read potential is output to BL2. Bit lines BL1,
The read potential output to BL2 is the first and second potentials described above.
Is determined in the same manner as in the embodiment. At this time, the polarization of the reference potential capacitor 122 changes as shown in FIG.
The state shown by the point 2 in FIG.

At time t3, when the potential of the signal SA is changed to the high level, the sense amplifier 140 is activated. As described above, sense amplifier 140 amplifies the higher bit line potential to power supply potential Vcc and the lower bit line potential to zero volts.

That is, the bit line BL at time t2
1 is V0 (that is, the data capacitor 1
12 is "0"), the potential of the bit line BL1 is amplified to zero volts, and the bit line BL2 is set to Vcc.
Is amplified. Therefore, the reference potential capacitor 12
Since the voltage between the terminals 2 becomes zero volts, the polarization of the capacitor 122 is in the state shown by the point 3 in FIG.

On the other hand, when the potential of bit line BL1 at time t2 is V1 (ie, data capacitor 112).
Is "1"), the potential of the bit line BL1 is amplified to Vcc and the bit line BL2 is amplified to 0 volt. Therefore, since the voltage between the terminals of the reference capacitor 122 becomes -Vcc, the polarization of the capacitor 122 becomes a state shown by a point 3 in FIG. 11B.

At time t4, the word line WL2 is set to low level, and a set potential (here, Vcc / 2) is supplied to the bit line BL3.
Set 3 to high level. As a result, rewriting to the reference potential capacitor 122 is performed.

The voltage between the terminals of the reference potential capacitor 122 is -Vcc / 2. Therefore, when the stored value of the data capacitor 112 is “0”, the polarization of the capacitor 122 is in the state shown by the point 4 in FIG. On the other hand, when the storage value of the data capacitor 112 is “1”, the polarization of the capacitor 122 of the reference potential capacitor 122 is in a state indicated by a point 4 in FIG.

As in the first embodiment, when the stored value of the data capacitor 112 is “0”, the rewriting of the capacitor 112 is performed in parallel with the rewriting of the reference potential capacitor 122. Be executed.

Subsequently, at time t5, the potential of the plate line PL is returned to the low level. As in the first and second embodiments, when the stored value of the data capacitor 112 is “1”, the plate line PL is returned to a low level, thereby performing rewriting.

By returning the potential of the plate line PL to the low level, the voltage between the terminals of the reference potential capacitor 122 becomes + Vcc / 2. Therefore, the polarization of the reference potential capacitor 122 is in a state shown by a point 5 in FIGS. 11A and 11B.

Subsequently, at time t6, the signal SA is set to low level, and at time t7, the signal EQ is set to high level and the bit line BL3 is set to low level. As a result, the bit lines BL1, BL2, BL3 become zero volt. At this time, since the voltage between the terminals of the data capacitor 112 is zero volt, it is maintained in the state shown in P0 or P1 in FIG. On the other hand, the reference potential capacitor 122
In FIG. 11A, since the voltage between terminals is -Vcc / 2,
The state shown by the point 6 in FIG.

Next, at time t8, the equalizing signal EQ is returned to the low level, and at time t9, the word line WL is turned off.
1, WL3 is set to low level, and the operation is completed.

As described above, the ferroelectric memory according to this embodiment uses the reference potential capacitor 122 with partial polarization. Since the partial polarization state has poor polarization retention characteristics, the polarization amount of the reference potential capacitor 122 is
It becomes smaller as the elapsed time from writing to reading is longer. In the ferroelectric memory according to this embodiment, as shown in FIG. 8, a read margin is ensured even when the polarization amount becomes zero (Q = 0), and therefore, no inconvenience occurs due to a decrease in the polarization amount.

Further, according to the reference potential capacitor 122, the reference potential capacitor 122 is partially polarized, so that the reference potential capacitor 122 is saturated (ie, is polarized to the state of P0 or P1 in FIG. 2). The influence of imprint can be reduced as compared with the case of FIG. In addition, the polarization of the reference potential capacitor 122 changes only within the range of the partial polarization when it is swung in the positive direction (see point 5 in FIGS. 11A and 11B), but swings in the negative direction. In this case, saturation polarization occurs temporarily (Fig. 1
1 (B), point 3), it is possible to automatically recover from imprint by a normal operation.

Further, in the ferroelectric memory according to this embodiment, the reliability of the memory can be improved by driving the reference potential cell 120 at a constant voltage. This is because in a reference potential cell having a large number of accesses,
Very important.

The reference potential cell may be provided for each memory cell block. In order to make the capacitance of the reference potential bit line BL2 the same as that of the data bit line BL1, for example, a dummy cell may be used. By adjusting the size and number of the dummy cells, the capacitance of the reference potential bit line BL2 can be adjusted.

[0092]

As described above in detail, according to the present invention, it is possible to provide a ferroelectric memory device in which the ferroelectric capacitor of the reference potential memory cell is hardly deteriorated.

[Brief description of the drawings]

FIG. 1 is a circuit diagram schematically showing a structure of a ferroelectric memory device according to a first embodiment.

FIG. 2 is a state diagram for explaining an operation of the ferroelectric memory device according to the first embodiment.

FIG. 3 is a timing chart for explaining the operation of the ferroelectric memory device according to the first embodiment.

FIG. 4 is a state diagram for explaining an operation of the ferroelectric memory device according to the first embodiment.

FIG. 5 is a circuit diagram schematically showing a structure of a ferroelectric memory device according to a second embodiment.

FIG. 6 is a timing chart for explaining an operation of the ferroelectric memory device according to the second embodiment.

FIG. 7 is a state diagram for explaining an operation of the ferroelectric memory device according to the second embodiment.

FIG. 8 is a state diagram for explaining an operation of the ferroelectric memory device according to the second embodiment.

FIG. 9 is a state diagram for explaining the operation of the ferroelectric memory device according to the second embodiment.

FIG. 10 is a timing chart for explaining an operation of the ferroelectric memory device according to the third embodiment.

FIG. 11 is a state diagram for explaining an operation of the ferroelectric memory device according to the third embodiment.

[Explanation of symbols]

 Reference Signs List 110 data memory cell 111 data transistor 112 data capacitor 120 reference potential memory cell 121 reference potential transistor 122 reference potential capacitor 130 equalizing circuit 131, 132 transistor 140 sense amplifier 150 reference potential setting circuit 201 reference potential writing Transistor WL1, WL2, WL3 Word line BL1, BL2, BL3 Bit line PL Plate line

Claims (3)

[Claims] 1. A data memory cell having a data ferroelectric capacitor and outputting a potential corresponding to the polarization of the data ferroelectric capacitor to a data bit line, and a reference potential ferroelectric capacitor. A reference potential memory cell for outputting a potential corresponding to the polarization of the reference potential ferroelectric capacitor to the reference potential bit line; and a data for positively or negatively saturation-polarizing the data ferroelectric capacitor. Writing means; reference potential setting means for partially or positively polarizing the reference potential ferroelectric capacitor; and detecting a magnitude relationship between the potential of the data bit line and the potential of the reference potential bit line. And a sense amplifier for determining storage data of the data memory cell. 2. The method according to claim 1, wherein the reference potential setting means applies a predetermined voltage to the reference potential ferroelectric capacitor, and a voltage is applied between the voltage applying means and a terminal of the reference potential ferroelectric capacitor. The ferroelectric memory device according to claim 1, further comprising a switch transistor provided. 3. The ferroelectric memory device according to claim 1, further comprising a dummy cell for adjusting a capacitance of the reference potential bit line.