JP2001229080A - Mpu direct coupled type bus tracer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a bus tracer capable of collecting a log in a failure by an information processor single body without using any tester such as a logic analyzer of in-circuit emulator by board diagnosis on a production line. SOLUTION: This bus tracer is mounted so as to be interposed between an MPU and an MPU socket, and the state of a signal on a bus connected to the MPU is monitored, and the value of the bus signal is held when any failure is detected, and the value is recorded in a non-volatile memory by a prescribed data format as failure information. This non-volatile memory is extracted from the memory socket, and memory contents are read by an ROM writer or the like, and displayed at a display device so that the cause of the failure can be analyzed. Also, the failure information can be easily read by a note-sized personal computer or the like without using any exclusive device such as an ROM writer by adopting a memory card slot and a non-volatile memory card instead of the memory socket and the non-volatile memory.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus equipped with an MPU board, which detects a fault on a bus connected to the MPU, and detects the fault.
The present invention relates to a bus tracer that records fault information in a memory.

[0002]

2. Description of the Related Art After a board mounted on an information processing apparatus is manufactured on a production line, board diagnosis is performed. This board diagnosis is roughly divided into a method using a diagnostic jig,
There is a method based on actual equipment confirmation.

As a method using a diagnostic jig, generally, there are three methods.
There are point probers, boundary scans, in-circuit testers, and the like.

In the method based on actual machine confirmation, a diagnostic program is operated using an MPU in an information processing apparatus to test the function of a board to be diagnosed. If a failure is detected during the test, an error message is displayed,
The diagnostician specifies the failure part based on the error message and the like.

[0005] The board diagnosis using the former diagnostic jig has the merit that a failure site can be pointed out in detail, but a diagnostic jig and equipment are required for each board type, and the manufacturing cost increases. Not suitable.

[0006] The latter board diagnosis by checking the actual machine has the merit that a test can be performed by the information processing apparatus alone. However, if a component around the MPU is broken, an error message or the like may not be displayed. When such a failure occurs, it is necessary to use a tester such as a logic analyzer or an in-circuit emulator to investigate the failure site.

The logic analyzer has an LS having a large number of pins.
When a probe is attached to the I or the like, the number of probe cables increases, and it is difficult to mount the board in the information processing apparatus in this state. In addition, since the in-circuit emulator generally has a large probe, it is physically difficult to mount the board on the information processing apparatus while the probe is mounted on the board. Therefore, it is difficult to use a tester such as a logic analyzer or an in-circuit emulator for board diagnosis of a product.

[0008] In order to solve the above problems and to make the analysis of the cause of a failure as easy as possible, there are a number of diagnostic devices capable of collecting a log at the time of a failure by the information processing device alone.

As a conventional example 1, Japanese Patent Application Laid-Open No. 8-147195
There is a failure detection / recording device disclosed in Japanese Unexamined Patent Publication (Kokai) Publication.

FIG. 5 is a block diagram showing the configuration of the entire system of the first conventional example.

In FIG. 5, 101 is an MPU, 104 is a main storage memory, 105 to 106 are input / output control devices, 50
0 is a system bus, 501 is a system controller that controls the use of the system bus 500, 502 is a fault detection / recording device, and 503 is a fault recording memory.

The fault detecting / recording device 502 monitors the system bus 500, and when a fault occurs on the bus, records the contents in the fault recording memory 503.

Since the failure detection / recording device 502 is mounted in advance as one circuit of the information processing device, the failure information log alone can be used without using a tester such as a logic analyzer or an in-circuit emulator. By reading the fault information recorded in the fault recording memory 503 by another device, the cause of the fault can be analyzed.

As a second conventional example, Japanese Patent Application Laid-Open No. H10-30
There is a bus tracer disclosed in the 7763 publication.

FIG. 6 is a configuration diagram according to a second embodiment of the related art.

In FIG. 6, reference numeral 600 denotes a system bus;
01 is a bus tracer, 602 to 603 are boards corresponding to control devices constituting an actual system, and 610 is a board 60
Bus slots 1 to 603 are mounted.

The bus tracer 601 includes a system bus 60
0, and records information of the transaction in a storage device in the bus tracer 601.

The bus tracer 601 includes a system bus 60
0, and the information processing apparatus alone can collect a log at the time of a failure, similarly to the failure detection / recording apparatus of the first conventional example.

[0019]

A conventional example 1 shown in FIG.
Alternatively, according to Conventional Example 2 shown in FIG. 6, a log at the time of failure can be collected by the information processing apparatus alone without using a tester such as a logic analyzer or an in-circuit emulator.

However, in the conventional example 1 shown in FIG. 5, since the fault detection / recording device 502 is mounted in advance as one circuit of the information processing device, extra parts are mounted on the board, and the cost of the board increases. In addition, problems such as a decrease in mounting efficiency and a decrease in reliability due to an increase in the number of components occur.

On the other hand, in the conventional example 2 shown in FIG. 6, since the bus tracer 601 is mounted in an empty slot of the system bus 600, the problem shown in the conventional example 1 does not occur. However, there is a limit to the number of bus slots installed in the information processing apparatus, and if option boards are installed in all bus slots, there is no empty slot, so that the bus tracer 601 cannot be installed. There is a problem.

Further, there is a problem that the bus tracer 601 cannot be applied to a bus having no bus slot such as a processor bus.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems of the prior art, and to prevent a failure in the information processing apparatus alone without using a tester such as a logic analyzer or an in-circuit emulator in board diagnosis or the like on a production line. An object of the present invention is to provide a bus tracer capable of collecting a log of time.

A second object is to mount no extra components for diagnosis on the board, to increase the cost of the board, to reduce the mounting efficiency, and to increase the reliability by increasing the number of components. It is an object of the present invention to provide a bus tracer that can collect a log at the time of a failure with a single information processing device without lowering the performance.

Another object of the present invention is to provide a bus tracer which does not require a dedicated bus slot and can be applied to diagnosis of a bus having no bus slot such as a processor bus.

[0026]

The present invention uses the following means to achieve the above object.

In general, today's information processing apparatuses are equipped with an MPU socket as a standard on an MPU board so that the MPU can be attached and detached. According to the present invention, the joint part having the same shape and the same pin specification as the standardized MPU socket and the state of the signal on the bus connected to the MPU are monitored via the joint part. A bus monitoring circuit for holding a state; a data recording circuit for recording fault information output from the bus monitoring circuit in a memory; and a memory unit including a memory socket and a non-volatile memory, and a joint between the MPU and the MPU socket. Mount with the part sandwiched.

Further, the joint board includes a joint board on which a joint portion is mounted, a logic board on which a bus monitoring circuit, a data recording circuit, and a memory section are mounted, and a connector for connecting these two boards. By connecting the logic board via a connector, when mounted with a joint between the MPU and the MPU socket, the logic board is shaped so as not to come into contact with components arranged around the MPU socket.

Next, the operation of the present invention will be described.

According to the present invention, the state of the signal on the bus connected to the MPU is monitored, the value of the bus signal is held when a failure is detected, and this value is recorded in the nonvolatile memory as failure information in a predetermined data format. . The cause of the failure can be analyzed by removing the nonvolatile memory from the memory socket, reading the contents of the memory with a ROM writer or the like, and displaying the contents on a display device.

Further, by adopting a memory card slot and a nonvolatile memory card instead of the memory socket and the nonvolatile memory, trouble information can be easily obtained on a notebook computer or the like without using a dedicated device such as a ROM writer. Can be read.

[0032]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is an embodiment of the present invention.

The MPU board 100 shown in FIGS. 1 and 2
Comprises an MPU socket 102, a main storage memory 104, and input / output control devices 105 to 106, and includes an MPU socket 102, a main storage memory 104, and an input / output control device 105.
Are connected by a bus 103. Usually M
An MPU 101 is mounted on a PU socket 102, operates according to a program stored in a main storage memory 104, and operates as an input / output control device 105 connected to a bus 103.
To 106 are accessed.

1 and 2, the bus tracer 110 of the present invention is mounted between the MPU 101 and the MPU socket 102.

A joint portion 111 having the same shape and the same pin specifications as the MPU socket 102 is mounted on the bus tracer 110.
The MPU 101 is mounted on the MPU 101 and the pin side of the joint portion 111 is inserted into the MPU socket 102.
It is mounted in between. In this state, the MPU 101
Is connected to the bus 103 via the joint part 111 and the MPU socket 102. It should be noted that the pins of the joint portion 111 are long enough to be securely inserted into the MPU socket 102.

The bus tracer 110 is provided with the MPU 10
A bus monitor circuit 112 for monitoring the state of the signal on the bus 103 connected to the bus 1 via a joint portion 111 and holding the state of the bus signal when a failure is detected;
2 includes a data recording circuit 113 for recording the failure information output from the memory 2 in a memory, and a memory unit 114 including a memory socket and a nonvolatile memory.

The memory section 114 employs a non-volatile memory so that the contents of the memory are not erased even when the power of the information processing apparatus is turned off, and a non-volatile memory is mounted on the bus tracer 110 by mounting a memory socket. It is designed to be removable.

Next, a block diagram of one embodiment of the present invention shown in FIG. 1 will be described.

MPU mounted on joint part 111
101 is a main storage memory 104 on the MPU board 100
Is operated by a program stored in the
It is assumed that the input / output control devices 105 to 106 which are connected to are accessed.

The bus monitoring circuit 11 in the bus tracer 110
2 constantly monitors the state of address / data lines on the bus 103 connected to the MPU 101, the state of control signals such as address strobe signals, and the like, and detects a bus failure when accessing the input / output control devices 105 to 106 from the MPU 101. Upon detection, the value of the address / data line and the control signal on the bus 103 at the time of the failure detection is held, and this value is output to the data recording circuit 113 as failure information. At the same time, a bus failure detection stage for notifying that a failure has occurred on the bus 103 is generated and output to the data recording circuit 113.

The bus failure that can be detected by the bus monitor circuit 112 includes, for example, a bus timeout due to access to an unmounted address, a parity error of an address / data line, and the like. When such a failure occurs, a bus error signal, an interrupt signal, and the like on the bus 103 are reflected. Therefore, if these signals are monitored, the bus monitoring circuit 112 can detect the bus failure. .

Data recording circuit 1 in bus tracer 110
13 receives the fault information from the bus monitoring circuit 112 and the bus fault detection stage, and starts the internal operation. Inside the data recording circuit 113, there is an address counter,
The value of the address counter is incremented each time it receives the bus failure detection stage, and is output to the memory unit 114 as an address line. Further, the failure information from the bus monitoring circuit 112 is converted into a predetermined data format, the converted data is output to the memory unit 114, and the memory control signal is output simultaneously with the above-described memory address line. The data is recorded in a nonvolatile memory in the memory unit 114.

When a failure occurs on the bus 103 temporarily and then returns, and the MPU 101 continues to operate without stopping, the failure information is stored in the nonvolatile memory in the memory unit 114 every time a failure occurs. Are accumulated in order. If the storage capacity of the non-volatile memory is exceeded, new fault information is overwritten on the oldest recorded fault information.

Next, the means for reading the fault information recorded in the memory unit 114 will be described.

The nonvolatile memory is taken out of the memory socket of the memory unit 114, mounted on a memory socket of a device such as a ROM writer which can read out the memory contents, and the contents of the nonvolatile memory are read out by a memory dump command or the like, and the contents are displayed. Display on the device.

In the above-described data format conversion in the data recording circuit 113, if values such as addresses and data are converted into ASCII codes, the fault information displayed on the display device is easy to see and the fault analysis is facilitated. Can be.

A memory card slot is provided instead of the memory socket of the memory section 114, and a general-purpose nonvolatile memory card is mounted here. The above-described data recording circuit 113 records failure information on this nonvolatile memory card when a bus failure is detected. To read the fault information recorded in the nonvolatile memory card, remove the nonvolatile memory card from the memory card slot of the memory unit 114, mount it in a memory card slot of a notebook computer or the like, and execute the nonvolatile memory card by a memory dump command or the like. Is read out. If a nonvolatile memory card is employed as described above, a dedicated device such as a ROM writer is not required, so that the failure information can be read anywhere with a notebook computer or the like.

Next, the shape of the bus tracer 110 will be described with reference to FIGS.

The MPU board 100 shown in FIGS. 3 and 4
Has an MPU socket 102 mounted therein.
Around the PU socket 102, an electric component 303 such as a main storage memory 104 and a capacitor / resistance is mounted.

As shown in FIGS. 3 and 4, the bus tracer 110 monitors the state of signals on the bus connected to the MPU 101 and the joint board 300 on which the joint part 111 is mounted, and detects a bus when a failure is detected. A logic board 301 mounted with a bus monitoring circuit for holding a signal state, a data recording circuit for recording fault information output from the bus monitoring circuit in a memory, and a memory unit including a memory socket and a nonvolatile memory; It comprises a connector 302 for connecting these two boards.

By connecting these two boards via the connector 302, when mounted with the joint part 111 interposed between the MPU 101 and the MPU socket 102, the components arranged around the MPU socket 102 It is shaped so that it does not touch.

In FIGS. 3 and 4, the bus monitoring circuit and the data recording circuit are shown as one LSI.

In the bus tracer 110 shown in FIG. 3, the logic board 301 is mounted horizontally on the joint board 300. Therefore, the logic board 3
Under 01, a tall component such as the main storage memory 104 cannot be mounted.
It is necessary to mount short electric components 303 such as capacitors / resistances. On the other hand, there is an advantage that mounting is possible even if the space on the MPU board 100 is low. This shape is suitable for a built-in board or the like mounted on a bus slot.

In the bus tracer 110 shown in FIG. 4, the logic board 301 is mounted vertically to the joint board 300. For this reason, the MPU board 100
There is a disadvantage that mounting is not possible if the space above is low.
There is an advantage that even if a tall component such as the main memory 104 is mounted around the PU socket 102, it does not come in contact with the PU socket 102. This shape is suitable when the space on the MPU board 100 is sufficiently high, such as a desktop personal computer.

For a quantitative explanation, the MPU board 1
A is the height of the space above 00, B is the height of the bus tracer 110 (= the height from the bottom of the joint board 300 to the top of the logic board 301), and the logic board is the bottom of the joint board 300. Assuming that the height to the bottom surface of 301 is C, the height of the MPU socket 102 is D, and the height of the electric component 303 is E, the shape shown in FIG.
The condition of B + D <A and C+D> E is a condition, and the condition of B + D <A is a condition in the shape shown in FIG.

For example, in the shape of FIG. 3, A is 55 (mm) and B is 4 in consideration of a general mounting board.
0 (mm), C is 22 (mm), D is 10 (mm), E
Is set to 15 (mm). In this case, B + D = 50 (m
m) <A, C + D = 32 (mm)> E, which indicates that the bus tracer 110 of the present invention is suitable for a mounting board or the like.

When an air-cooling fan is mounted on the MPU 101, B + D <
If the height to the top of the air-cooling fan when not mounted on the U board 100 and the condition of C + D> E are satisfied, the bus tracer 110 of the present invention will
Regardless of the height A on the 00, any MPU board can be supported.

In the shape of FIG. 4, A is set to 120 (mm) and B is set in consideration of a general desktop personal computer.
Is 100 (mm) and D is 10 (mm). In this case, B + D = 110 (mm) <A, which indicates that the bus tracer 110 of the present invention is suitable for an information processing device such as a desktop personal computer.

[0059]

According to the present invention, a failure log can be collected by the information processing apparatus alone without using a tester such as a logic analyzer or an in-circuit emulator for board diagnosis or the like on a production line. it can.

Further, no extra parts for diagnosis are mounted on the board, the cost of the board is not increased, the mounting efficiency is not reduced, and the reliability is not reduced by increasing the number of parts. In addition, a log at the time of a failure can be collected by the information processing apparatus alone.

Further, no special bus slot is required,
The present invention can be applied to diagnosis of a bus having no bus slot such as a processor bus.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing an embodiment of the present invention.

FIG. 3 is a diagram showing an example of the shape of the present invention.

FIG. 4 is a view showing another example of the shape of the present invention.

FIG. 5 is a block diagram showing the configuration of the entire system of Example 1 of the related art.

FIG. 6 is a configuration diagram according to an embodiment of Example 2 of the related art.

[Explanation of symbols]

100: MPU board, 101: MPU, 102: MP
U socket, 103 bus, 104 main memory, 1
05 · 106 · I / O control device, 110 · Bus tracer, 111 · Joint part, 112 · Bus monitoring circuit,
113 data recording circuit, 114 memory unit, 300
Joint board, 301 ... Logic board, 30
2 Connector, 303 Electrical parts, 500 System bus, 501 System controller, 502 Fault detection / recording device, 503 Fault recording memory, 600 System bus, 601 Bus tracer, 602, 603 Real system Board, 610 ... Bus slot.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Masayuki Kuramoto 1st Horiyamashita, Hadano-shi, Kanagawa Prefecture Inside the Enterprise Server Division, Hitachi, Ltd. (72) Inventor Masataka Kaneko 1st Horiyamashita, Hadano-shi, Kanagawa Japan (72) Inventor Tataka Unno 1 Horiyamashita, Hadano-shi, Kanagawa F-term (reference) in Hitachi Information Technology Co., Ltd. 5B042 GA13 GA32 GA33 GC17 HH03 JJ05 KK14 LA20 MA06 MA08 MC09 MC15 5B048 AA12 DD01 5B083 AA04 BB06 CC10 CE00 DD01 DD14 EE02 EE03 EE06 EE11 GG08

Claims (3)

[Claims] A bus tracer for connecting an MPU to one or more input / output control devices via a bus, wherein the MPU monitors a bus on an MPU board mounted on the board via an MPU socket; A joint having the same shape and the same pin specifications as the socket, and the MP
A bus monitoring circuit that monitors the state of a signal on a bus connected to U via the joint portion and retains the state of the bus signal when a failure is detected; and stores failure information output from the bus monitoring circuit in a memory. A data recording circuit, a memory unit comprising a memory socket and a non-volatile memory,
A bus tracer which is mounted with the joint part interposed between the MPU and the MPU socket. 2. The bus tracer according to claim 1, wherein
A joint board mounting the joint portion,
A logic board on which the bus monitoring circuit, the data recording circuit, and the memory unit are mounted; and a connector for connecting the two boards, and the joint board and the logic board are connected via the connector. When the MPU is mounted with the joint portion interposed between the MPU and the MPU socket,
2. The bus tracer mounting method according to claim 1, wherein the bus tracer is formed so as not to contact a component disposed around the socket. 3. The bus tracer according to claim 1, wherein
A memory card slot and a non-volatile memory card are provided instead of the memory socket and the non-volatile memory of the memory unit, and a dedicated device such as a ROM writer is required by attaching and detaching the non-volatile memory card to and from the memory card slot. 2. The recording method of a bus tracer according to claim 1, wherein the failure information recorded on the nonvolatile memory card can be read out by a notebook computer or the like without performing.