JP2001229046A - Test circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a test circuit capable of continuously confirming an inside state in the real time processing of a DSP. SOLUTION: An LSI chip (1000) is provided with a test circuit (1400), and the inside state of a DSP (1100) is transferred to a Data-ROM (1200) according to a designated break point, and transferred from the Data-RAM to an outside PC (1600). Thus, it is possible to easily verify the inside state of the DSP in real time processing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test circuit used for verifying the operation of a program in a DSP or a microprocessor (hereinafter referred to as a DSP).

[0002]

2. Description of the Related Art For the purpose of verifying the operation of a program in a DSP, for example, a verification method using a JTAG circuit (boundary scan circuit) has been used (document:
Test Synthesis Workshop (March 1995),
PP. 96-97: Synopsys Japan Ltd.). This J
As shown in a schematic diagram in FIG. 17, the TAG circuit is provided with a serial scan chain on a boundary line (I / O pad) of an LSI chip (DSP), and a T tag connected to the outside is provided.
Arbitrary instructions can be executed by the AP controller. Conventionally, in order to perform operation verification (debugging) of an application program using this circuit, the operation of the LSI chip (DSP) is temporarily suspended, and the state inside the LSI chip (DSP) is temporarily stopped by an externally connected TAP controller. A method of confirming and confirming the program flow thereafter by single step execution or the like was used.

[0003]

However, in the conventional verification method, the DSP is temporarily suspended, and the internal state of the DSP at that time is checked, so that it is impossible to verify the DSP inside during the real-time operation. .
For example, when data sampled at a fixed period, such as audio data, is input to a DSP, it is necessary to continuously check whether or not the data is normal.
It was not possible to continuously check the intermediate results of the computations performed inside the SP (if filter computations were being performed, filter inputs and filter outputs, etc.).

An object of the present invention is to solve the above-mentioned problems and to provide a test circuit capable of continuously confirming an internal state in real-time processing of a DSP.

[0005]

In order to solve the above-mentioned problems, a test circuit according to the present invention is mounted on the same chip in order to verify in real time the operation of a DSP mounted on an LSI chip. A test circuit, wherein D
Means for holding a specified breakpoint of a program whose internal state of the SP is to be detected, and means for detecting a match between the breakpoint held in the holding means and a program counter value inside the DSP in the operating state of the DSP Means for switching the operation program of the DSP to a test program for extracting internal state data of the DSP when a match is detected by the detection means, and switching the operation program of the DSP to a test program by the switching means. It is characterized in that the internal state of the DSP is extracted in real time.

[0006]

Embodiments of the present invention will be specifically described below with reference to the drawings.

<First Embodiment><Configuration> FIG. 1 is a configuration diagram of a circuit showing a first embodiment of the present invention, and an LSI chip (1000) is a DSP (1).
100), Data-RAM (1200), Progr
am-ROM (1300), test circuit (1400),
It is constituted by a program selection circuit (1500).
Further, a PC is used to control the test circuit (1400).
(1600) is connected.

The DSP (1100) includes a program counter (1101) and an instruction register (1102), and has a program counter output terminal (1130), a Wait input terminal (1131), and a program input terminal (1132).

The test circuit (1400) comprises a program counter comparison circuit (1401), a break register (14
02), a test control circuit (1403), a test step register (1404), a test program memory (14
05), test program output circuit (1406), Da
a ta-RAM control circuit (1407), a PC interface circuit (1408), a program counter input terminal (1430), a Wait output terminal (1431), a test program selection output terminal (1432), a test program output terminal (1433), Data-RAM access terminal (1434) and PC interface terminal (143)
5).

FIG. 1 shows connections related to a test operation, and detailed connections of a clock system and a data system are omitted.

<Operation> The operation procedure of the test method using the test circuit of FIG. 1 will be described below. In the following description, the processing of the mark * is performed under the control of the PC (1600).

(1) An area for temporarily storing the internal state of the DSP (1100) "temporary storage area" is a Data-RA
M (1200). Furthermore, "temporary storage area"
The first word assigned to the “Write-po”
(see FIG. 2A). For example, 0x3 of the Data-RAM (1200) is defined.
From address 000 (0x indicates hexadecimal notation) to 0x3ff
If address f is a “temporary storage area”, address 0x3000 is a “Write-pointer storage field”.

(2) “Wri” assigned in (1)
In the “te-pointer storage field”, the value of “the start address of the temporary storage area + 1” (0x30 in the above example)
01) is stored *.

(3) In the processing of the application program, the program address of the place where the internal state is to be confirmed is set to the break register (140) of the test circuit (1400).
* Stored in 2). For example, Program of FIG.
The instruction at address 0x0100 shown in the m-ROM (the instruction to transfer the input data of the DSP to the a0 register (a0 is the DSP
To check the contents of the a0 register in the internal register)), set the address 0x0100 to the break register (1
402).

(4) At the breakpoint set in (3), an instruction for transferring the internal state of the DSP to the "temporary storage area" is stored in the test program memory (1405) of the test circuit (1400). *. here,
Write-point stored in “Write-pointer storage field” allocated in (1)
The writing position in the “temporary storage area” is controlled using t.

The internal state a0 register of the DSP is set to Data
-The operation sequence of the test program will be described below, taking as an example the case of transferring to the "temporary storage area" of the RAM. (4-1) “Writ” of Data-RAM (1200)
Read the Write-point stored in the “e-pointer storage field”. (4-2) Transfer the internal state a0 register of the DSP (1100) to the address indicated by the Write-point. (4-3) Write Increment -point (4-4) If "Write-point> last address of temporary storage area", then Write-p
point is “the first address of the temporary storage area + 1”. (4-5) Write-point is changed to “Write-p
pointer storage field ".

(5) The number of program steps stored in the test program memory (1405) in (4) is stored in the test step register (14) of the test circuit (1400).
04).

(6) The operation of the DSP (1100) is started, and the application programs are sequentially executed. A program counter comparison circuit (1401) in the test circuit (1400) is a program counter value (a value of the program counter (1101)) output from a program counter output terminal (1130) of the DSP (1100).
And the value stored in the break register (1402) one by one.

(7) If the result of the program counter comparison circuit (1401) is "matched" in (6), a Wait signal is output from the Wait output terminal (1431) of the test circuit (1400), and the DSP (1100) To Wa
Set to the it state. Further, a signal indicating that the test program is selected is output from the test program selection output terminal (1432). Program selection circuit (150
0) is switched by a signal output from the test program selection output terminal (1432) of the test circuit (1400), and the test program output terminal (143) is switched.
The test program output from 3) is a DSP (110)
0) and is transferred to the instruction register (1102). Test circuit (1
The output of the test program from (400) supplies the number of steps stored in the test step register (1404) to the DSP (1100). The operation sequence of the test program is as shown in (4), and the supply of the test program is output every execution cycle.

(8) After writing the internal state of the DSP in the "temporary storage area" by (7), the signals output from the Wait output terminal (1431) and the test program selection output terminal (1432) are restored to the original state. Return to the state, D
The operation of the SP is restarted.

(9) After the operations (7) and (8) are repeated, the DSP (1100) is stopped. DSP
After the stop of (1100), the PC (1600) sends the Data-RAM control circuit (140) of the test circuit (1400).
7), the data stored in the “temporary storage area” of the Data-RAM (1200) is read.

(10) The operation is verified using the data read on the PC (1600) in (9) (ie, the result of continuously outputting the internal state of the DSP (1100)).

In this embodiment, the test circuit (140
Although the test program memory (1405) is provided in (0), the memory may be constituted by a register group, FIFO, or the like.

<Effects> As described above, according to the first embodiment, by using the test circuit (1400), D
The internal state in the real-time processing of the SP (1100) can be confirmed, and operation verification can be easily performed. Also, the DS transferred to the PC (1600)
The result of the internal state of P (1100) is transferred to PC (1600).
It is also possible to display a waveform using the tool described above and to analyze a frequency component by FFT analysis. In the present embodiment, data stored in the “temporary storage area” of the Data-RAM (1200)
When the internal state of the SP (1100) is continuously written and the entire “temporary storage area” is written, the internal state of the next DSP (1100) is written by overwriting. For this reason, the DSP (1100) is stopped when it is desired to check the internal state of the DSP (1100), and the Data-RA
By transferring the data stored in the “temporary storage area” of M (1200) to PC (1600), it is possible to check the internal state of DSP (1100) at an arbitrary time.

Further, by changing the program stored in the test program memory (1405) of the test circuit (1400), an arbitrary test can be executed. In the present embodiment, the test circuit (140
Although the test program memory (1405) is provided in (0), the test program memory (1405) may be constituted by a register group or FIFO in addition to the memory.

<Second Embodiment><Structure> FIG. 3 is a circuit diagram showing a second embodiment of the present invention, in which an LSI chip (2000) is a DSP (2).
100), Data-RAM (2200), Progr
am-ROM (2300), test circuit (2400),
It is constituted by a program selection circuit (2500).
Further, a PC for controlling the test circuit (2400) is used.
(2600) is connected.

The DSP (2100) includes a program counter (2101) and an instruction register (2102), and has a program counter output terminal (2130), a Wait input terminal (2131), and a program input terminal (2132).

The test circuit (2400) includes a program counter comparison circuit (2401), a break register (24
02), a test control circuit (2403), a test step register (2404), and a break end register (240
5), a test completion flag (2406), a test program memory (2407), a test program output circuit (2406)
408), Data-RAM control circuit (2409), P
A C interface circuit (2410), a program counter input terminal (2430), and a Wait output terminal (2
431), a test program selection output terminal (243
2), test program output terminal (2433), Dat
It has an a-RAM access terminal (2434) and a PC interface terminal (2435).

FIG. 3 shows connections related to the test operation, and detailed connections of the clock system and the data system are omitted.

<Operation> The operation procedure of the test method using the test circuit of FIG. 3 will be described below. In the following description, the processing of the mark * is performed under the control of the PC (2600).

(1) An area for temporarily storing the internal state of the DSP (2100) "temporary storage area" is a Data-RA
M (2200). Furthermore, "temporary storage area"
The first word assigned to the “Write-po”
inter storage field ", the second word is" Br "
eek-counter storage field "(see FIG. 4A). For example, a Data-RAM (22
00) 0x3000 (0x indicates hexadecimal notation)
From 0x3ffff to "temporary storage area"
Address 0x3000 is “Write-pointer storage field” and address 0x3001 is “Break-co
unter storage field ".

(2) “Write” assigned in (1)
In the “pointer storage field”, the value of “the start address of the temporary storage area + 2” (0x300 in the above example)
2) Write zero to “Break-counter storage field” *.

(3) In the processing of the application program, the program address of the place where the internal state is to be checked is stored in the break register (24) of the test circuit (2400).
02). For example, Prog shown in FIG.
Instruction at address 0x0100 shown in the ram-ROM (DSP
(A0 is a D
To check the contents of the a0 register in the register inside the SP)), the address 0x0100 is stored in the break register (2402).

(4) When the breakpoint set in (3) occurs a specified number of times, the internal state of the DSP (2100) is changed to the Data-RAM (2
In order not to transfer to the “temporary storage area” of (200), the designated end number is stored in the break end register (2405) of the test circuit (2400) *.

(5) At the breakpoint set in (3), an instruction for transferring the internal state of the DSP to the "temporary storage area" is stored in the test program memory (2407) of the test circuit (2400). *. here,
Write-point stored in “Write-pointer storage field” allocated in (1)
The control of the write position in the “temporary storage area” using t is performed by using the Break-count stored in the “Break-counter storage field”.
The internal state of P (2100) is stored in Data-RAM (220
0) control of transfer to the "temporary storage area".

The internal state a0 register of the DSP is set to Data
-The operation sequence of the test program will be described below by taking as an example the case of transfer to the "temporary storage area" of the RAM. (5-1) If the test completion flag (2406) in the test circuit (2400) is "enable", the processing up to (5-10) is not performed. (5-2) “Writ” of Data-RAM (2200)
The Write-point stored in the “e-pointer storage field” is read. (5-3) The internal state a0 register of the DSP (2100) is transferred to the address indicated by the Write-point. (5-4) Write Increment -point (5-5) If "Write-point> last address of temporary storage area", then Write-p
point is “the start address of the temporary storage area + 2”. (5-6) Write-point is changed to “Write-p
(5-7) "Brea" in the Data-RAM (2200).
The Break-count stored in the “k-counter storage field” is read. (5-8) Break-point is incremented. (5-9) “Break-point> Break end register (2405) of test circuit (2400) ), The test completion flag (2406) of the test circuit (2400) is set to “enable”. (5-10) Break-point is changed to “Break-point”.
pointer storage field ".

(6) The number of program steps stored in the test program memory (2407) in the operation sequence of (5) is stored in the test step register (2404) of the test circuit (2400) *.

(7) The test completion flag (2406) in the test circuit (2400) is set to "disable" *.

(8) The operation of the DSP (2100) is started, and the application programs are sequentially executed. A program counter comparison circuit (2401) in the test circuit (2400) is a program counter value (a value of the program counter (2101)) output from a program counter output terminal (2130) of the DSP (2100).
And the value stored in the break register (2402).

(9) If the result of the program counter comparison circuit (2401) is "matched" in (8), a Wait signal is output from the Wait output terminal (2431) of the test circuit (2400) and the DSP (2100) To Wa
Set to the it state. Further, a signal indicating that the test program is selected is output from the test program selection output terminal (2432). Program selection circuit (250
0) is switched by a signal output from a test program selection output terminal (2432) of the test circuit (2400), and the test program output terminal (243) is switched.
The test program output from 3) is a DSP (210)
0) to the program input terminal (2132) and transferred to the instruction register (2102). Test circuit (2
The output of the test program from (400) supplies the number of steps stored in the test step register (2404) to the DSP (2100). The flow of the test program is as shown in (5), and the supply of the test program is output every execution cycle.

(10) After writing the internal state of the DSP in the "temporary storage area" by (9), the signals output from the Wait output terminal (2431) and the test program selection output terminal (2432) are restored to the original state. Return to the state, D
The operation of the SP is restarted.

(11) After repeating the operations (9) and (10), the DSP (2100) is stopped. DS
The stop of P (2100) is performed by setting the test completion flag (2406) in the test circuit (2400) to “enable”.
Make sure that Test complete flag (240
When 6) is "enable", it indicates that the number of breaks stored in the break end register (2405) has occurred. After stopping the DSP (2100), the PC (260)
0) via the Data-RAM control circuit (2409) of the test circuit (2400).
00), the data stored in the “temporary storage area” is read.

(12) The operation is verified using the data read on the PC (2600) in (11) (ie, the result of continuously outputting the internal state of the DSP (2100)).

In this embodiment, the test circuit (240
Although the test program memory (2407) is provided in (0), the memory may be constituted by a register group, a FIFO, or the like. Further, the test circuit (240
Although the break end register (2405) is provided in (0), a method of providing the field in the Data-RAM (2200) is also possible.

<Effects> As described above, according to the second embodiment, by using the test circuit (2400), the internal state in the real-time processing of the DSP (2100) can be confirmed, and the operation verification Can be easily performed. Also, the result of the internal state of the DSP (2100) transferred to the PC (2600) is stored in the PC (26).
It is also possible to display a waveform using the tool of (00) and to analyze a frequency component by FFT analysis. In the present embodiment, the internal state of the DSP (2100) is Dat
When transferring data to the a-RAM (2200), the transfer operation can be terminated at the specified number of break occurrences. Therefore, the internal state of the DSP (2100) at the time when the specified program address has passed the specified number of times is confirmed. It is possible to do. Further, since it is possible to determine whether the specified number of breaks has been reached using the test completion flag (2406) in the test circuit (2400),
The stop timing of the DSP (2100) can be controlled.

Further, by changing the program stored in the test program memory (2407) of the test circuit (2400), an arbitrary test can be executed. In the present embodiment, the test circuit (240
0), the test program memory (2407) is provided, but other than the memory, the test program memory (2407) may be constituted by a register group or FIFO.

<Third Embodiment><Structure> FIG. 5 shows a circuit structure according to a third embodiment of the present invention, in which an LSI chip (3000) includes a DSP (310).
0), Data-RAM (3200), Program
-It is configured by a ROM (3300), a test circuit (3400), and a program selection circuit (3500). Further, the PC (3400) is used to control the test circuit (3400).
600) is connected.

The DSP (3100) includes a program counter (3101) and an instruction register (3102), and has a program counter output terminal (3130), a Wait input terminal (3131), and a program input terminal (3132).

The test circuit (3400) includes a program counter comparison circuit (3401) and a break register (34).
02), a test control circuit (3403), a transfer start address register (3404), a transfer end address register (3405), a write-pointer storage register (3406), and a test program register (340).
7), a Data-RAM control circuit (3408), a PC interface circuit (3409), a program counter input terminal (3430), and a Wait output terminal (343).
1), test program selection output terminal (3432), test program output terminal (3433), Data-RA
It has an M access terminal (3434) and a PC interface terminal (3435).

FIG. 5 shows connections related to the test operation, and detailed connections of the clock system and the data system are omitted.

<Operation> The operation procedure of the test method using the test circuit shown in FIG. 5 will be described below. In the following description, the processing of the mark * is performed under the control of the PC (3600).

(1) An area for temporarily storing the internal state of the DSP (3100) "temporary storage area" is defined as Data-RA
M (3200) (see FIG. 6A). For example, an address from 0x3000 (0x indicates hexadecimal notation) to 0x3fff of the Data-RAM (3200) is set as a “temporary storage area”.

(2) Value of “head address of temporary storage area” allocated in (1) (0x3000 in the above example)
Into the transfer start address register (3404) of the test circuit (3400) and the value of the "end address" (0x3fff in the above example) into the transfer end address register (340).
5). Further, the value of the “head address” of the “temporary storage area” is stored in the Write-pointer storage register (3406) *.

(3) In the processing of the application program, the program address of the place where the internal state is to be checked is stored in the break register (34) of the test circuit (3400).
02). For example, Program of FIG.
The instruction at address 0x0100 shown in the m-ROM (the instruction to transfer the input data of the DSP to the a0 register (a0 is the DSP
To check the contents of the a0 register in the internal register)), add the address 0x0100 to the break register (3
402).

(4) Store an instruction for transferring the internal state of the DSP to the “temporary storage area” at the breakpoint set in (3) in the test program register (3407) of the test circuit (3400) *. For example, D
The value of the a0 register in SP (3100) is set to Data
When transferring to the RAM (3200), the “mov instruction” as the transfer instruction and the “a0 register” as the transfer source are stored in the test program register (3407) (“m
ov a0, ”is stored.) The transfer position of the“ temporary storage area ”from the DSP (3100) to the Data-RAM (3200) is determined by the transfer start address register (3404) and the transfer end address register (3405) in the test circuit (3400). ), The Write-pointer storage register (3406) is used.

As an example of transferring the internal state a0 register of the DSP to the “temporary storage area”, the DSP (310
An operation sequence for transferring the internal state of (0) to the Data-RAM (3200) will be described. (4-1) Write-po of test circuit (3400)
Read the Write-point stored in the inter storage register (3406). (4-2) The Write-point read out in (4-1) is added to the test program (“mov a0,”) stored in the test program register (3407) of the test circuit (3400) ( "Mov a
0, write-point ") and output from the test program output terminal (3433). (4-3) Write-point is incremented. (4-4)"Write-point> Value of transfer end address register (3405) ”, W
write-point is transferred to the transfer start address register (3
404). (4-5) Write-point is changed to Write-p
The pointer is stored in the pointer storage register (3406).

(5) The operation of the DSP (3100) is started, and the application programs are sequentially executed. The program counter comparison circuit (3401) in the test circuit (3400) is a program counter value (the value of the program counter (3101)) output from the program counter output terminal (3130) of the DSP (3100).
And the value stored in the break register (3402) one by one.

(6) If the result of the program counter comparison circuit (3401) is "matched" in (5), a Wait signal is output from the Wait output terminal (3431) of the test circuit (3400) and the DSP (3100) To Wa
Set to the it state. Further, a signal indicating that the test program is selected is output from the test program selection output terminal (3432). Program selection circuit (350
0) is switched by a signal output from the test program selection output terminal (3432) of the test circuit (3400), and the test program output terminal (343) is switched.
The test program output from 3) is a DSP (310)
0) and is transferred to the instruction register (3102). Test circuit (3
The output of the test program from (400) is (4-2)
The 1-word test program described in is output.

(7) After writing the internal state of the DSP in the "temporary storage area" in (6), the signals output from the Wait output terminal (3431) and the test program selection output terminal (3432) are restored to the original state. Return to the state, D
The operation of the SP is restarted.

(8) After repeating the operations (6) and (7), the DSP (3100) is stopped. DSP
After the stop of (3100), the Data-RAM control circuit (340) of the test circuit (3400) is sent from the PC (3600).
8), the data stored in the “temporary storage area” of the Data-RAM (3200) is read.

(9) The operation is verified using the data read on the PC (3600) in (8) (ie, the result of continuously outputting the internal state of the DSP (3100)).

In this embodiment, the test circuit (340)
Although the test program register (3407) is provided in (0), the test program register (3407) may be constituted by a memory or the like in addition to the register.

<Effects> As described above, according to the third embodiment, by using the test circuit (3400), it is possible to confirm the internal state in the real-time processing of the DSP (3100), and to verify the operation. Can be easily performed. The result of the internal state of the DSP (3100) transferred to the PC (3600) is stored in the PC (36).
00) to display waveforms using the tool
The analysis makes it possible to analyze the frequency components.
In this embodiment, the internal state of the DSP (3100) is Da
When transferring to the ta-RAM (3200), 1 word
DSP (3)
100) can be in a Wait state in a short time. The data stored in the “temporary storage area” continuously writes the internal state of the DSP (3100) during the real-time processing, and when the entire “temporary storage area” is written, the data of the next DSP (3100) is overwritten. The internal state is written. For this reason, the DSP (3100) is stopped when it is desired to check the internal state of the DSP (3100),
By transferring the data stored in the “temporary storage area” of the a-RAM (3200) to the PC (3600), it is possible to confirm the internal state of the DSP (3100) at an arbitrary time. In the present embodiment, the test program register (340) is included in the test circuit (3400).
Although 7) is provided, it is also possible to configure with a memory or the like in addition to the register.

<Fourth Embodiment><Structure> FIG. 7 is a circuit diagram showing a fourth embodiment of the present invention, in which an LSI chip (4000) is a DSP (4).
100), Data-RAM (4200), Progr
am-ROM (4300), test circuit (4400),
It is constituted by a program selection circuit (4500).
Further, in order to control the test circuit (4400), the PC
(4600) is connected.

The DSP (4100) includes a program counter (4101) and an instruction register (4102), and has a program counter output terminal (4130), a Wait input terminal (4311), and a program input terminal (4322).

The test circuit (4400) includes a program counter comparison circuit (4401) and a break register (44
02), a test control circuit (4403), a transfer start address register (4404), a transfer end address register (4405), a write-pointer storage register (4406), a break end register (4407),
Break counter (4408), test completion flag (4
409), test program register (4410), D
It includes an at-RAM control circuit (4411), a PC interface circuit (4412), a program counter input terminal (4430), a Wait output terminal (4431), a test program selection output terminal (4432), a test program output terminal (4433), Data-RAM access terminal (4434) and PC interface terminal (44
35).

FIG. 7 shows connections related to the test operation, and detailed connections of the clock system and the data system are omitted.

<Operation> The operation procedure of the test method using the test circuit of FIG. 7 will be described below. In the following description, the processing of the mark * is performed under the control of the PC (4600).

(1) An area for temporarily storing the internal state of the DSP (4100) “temporary storage area” is defined as Data-RA
M (4200) (see FIG. 8A). For example, an address from 0x3000 (0x indicates hexadecimal notation) to 0x3fff of the Data-RAM (4200) is set as a “temporary storage area”.

(2) Value of “head address of temporary storage area” allocated in (1) (0x3000 in the above example)
Into the transfer start address register (4404) of the test circuit (4400) and the value (0x3fff in the above example) of the "end address" into the transfer end address register (440).
* Stored in 5). Further, the value of the “head address” of the “temporary storage area” is stored in the Write-pointer storage register (4406) *.

(3) In the processing of the application program, the program address of the place where the internal state is to be checked is stored in the break register (44) of the test circuit (4400).
02). For example, Program of FIG.
The instruction at address 0x0100 shown in the m-ROM (the instruction to transfer the input data of the DSP to the a0 register (a0 is the DSP
To check the contents of the a0 register in the (internal register)), set the address 0x0100 to the break register (4
402).

(4) If the breakpoint set in (3) occurs a specified number of times, the internal state of the DSP (4100) is changed to the Data-RAM (4
In order not to transfer to the "temporary storage area" of the test circuit (200), the number of designated end times is stored in the break end register (4407) of the test circuit (4200) *.

(5) At the breakpoint set in (3), an instruction for transferring the internal state of the DSP to the “temporary storage area” is stored in the test program register (4410) of the test circuit (4400). *. For example, the value of the a0 register in the DSP (4100) is
When transferring data to the data-RAM (4200), the “mov command” as a transfer command and the “a0 register” as a transfer source are stored in the test program register (4410) (“mov a0,” is stored). DSP (410
The transfer positions of the “temporary storage area” of the data-RAM (4200) from the transfer head address register (4404), the transfer end address register (4405), and the write-pointer in the test circuit (4400)
The storage register (4406) is used.

As an example of transferring the internal state a0 register of the DSP to the “temporary storage area”, the DSP (410
An operation sequence for transferring the internal state of (0) to the Data-RAM (4200) will be described. (5-1) When the test completion flag (4409) in the test circuit (4400) is "enable", the subsequent processing up to (5-9) is not performed. (5-2) Write-po of test circuit (4400)
Read the Write-point stored in the inter storage register (4406). (5-3) The Write-point read in (5-2) is added to the test program (“mov a0,”) stored in the test program register (4410) of the test circuit (4400) ( "Mov a
0, write-point ") and output from the test program output terminal (4433). (5-4) Increment write-point. (5-5)"Write-point> value of transfer end address register (4405). ”, Wr
Item-point is transferred to the transfer start address register (44
04). (5-5) Write-point is changed to Write-po
Write to the inter storage register (4406). (5-6) The break-count is read from the break counter (4408) of the test circuit (4400). (5-7) Break-point is incremented. (5-8) If “break-count> value of break end register (4407)”, the test completion flag (4409) of the test circuit (4400) is set to “e”.
(5-9) Break-point is stored in the break counter (4408).

(6) The operation of the DSP (4100) is started, and the application programs are sequentially executed. The program counter comparison circuit (4401) in the test circuit (4400) is a program counter value (the value of the program counter (4401)) output from the program counter output terminal (4130) of the DSP (4100).
And the value stored in the break register (4402).

(7) If the result of the program counter comparison circuit (4401) is "matched" in (6), the Wait output terminal (443) in the test circuit (4400)
1) Outputs a Wait signal from the DSP (4100)
In the Wait state. Further, a signal indicating that the test program is selected is output from the test program selection output terminal (4432). The program selection circuit (4500) is switched by a signal output from the test program selection output terminal (4432) of the test circuit (4400), and the test program output from the test program output terminal (4433) is converted to a DSP.
The program is supplied to a program input terminal (4132) of (4100) and transferred to an instruction register (4102). The output of the test program from the test circuit (4400) is
The 1-word test program described in (5-3) is output.

(8) After writing the internal state of the DSP in the “temporary storage area” by (7), the signals output from the Wait output terminal (4431) and the test program selection output terminal (4432) are restored to the original state. Return to the state, D
The operation of the SP is restarted.

(9) After repeating the operations (6) and (8), the DSP (4100) is stopped. DSP
After the stop of (4100), the Data-RAM control circuit (441) of the test circuit (4400) is sent from the PC (4600).
Via 1), the data stored in the “temporary storage area” of the Data-RAM (4200) is read.

(10) The operation is verified using the data read on the PC (4600) in (8) (ie, the result of continuously outputting the internal state of the DSP (4100)).

In this embodiment, the test circuit (440)
Although the test program register (4411) is provided in (0), the test program register (4411) may be constituted by a memory or the like other than the register.

<Effects> As described above, according to the fourth embodiment, the internal state in the real-time processing of the DSP (4100) can be confirmed by using the test circuit (4200), and the operation verification Can be easily performed. Also, the result of the internal state of the DSP (4100) transferred to the PC (4600) is
It is also possible to display a waveform using the tool of (00) and to analyze a frequency component by FFT analysis.

In this embodiment, when the internal state of the DSP (4100) is transferred to the Data-RAM (4200), the internal state of the DSP (4100) can be executed by a 1-word test instruction. Is short.

Further, the internal state of the DSP (4100) is
When transferring data to the data-RAM (4200), the transfer operation can be terminated at the specified number of break occurrences. Therefore, the internal state of the DSP (4100) at the time when the specified program address has passed the specified number of times is confirmed. It is possible to do.

Further, since it is possible to determine whether or not the specified number of breaks has been reached by using the test completion flag (4409) in the test circuit (4400), D
The stop timing of the SP (4100) can be controlled.

In this embodiment, the test circuit (44)
00), the test program register (4410) is provided. However, the test program register (4410) may be constituted by a memory or the like in addition to the register.

<Fifth Embodiment><Structure> FIG. 9 is a circuit diagram showing a fifth embodiment of the present invention.
Chip (5000) is DSP (5100), Data-
RAM (5200), Program-ROM (530
0), a test circuit (5400), and a program selection circuit (5500). Further, a PC (5600) is connected to control the test circuit (5400).

The DSP (5100) includes a program counter (5101) and an instruction register (5102), and has a program counter output terminal (5130), a Wait input terminal (5131), and a program input terminal (5132).

The test circuit (5400) includes a program counter comparison circuit 1 (5401), a break register 1
(5402), the program counter comparison circuit 2 (540
3), break register 2 (5404), test control circuit (5405), test step register 1 (540)
6), test step register 2 (5407), test program memory (5408), test program output circuit (5409), data-RAM control circuit (541)
0), a PC interface circuit (5411), a program counter input terminal (5430), a Wait output terminal (5431), a test program selection output terminal (5
432), test program output terminal (5433), D
It has an data-RAM access terminal (5434) and a PC interface terminal (5435).

FIG. 9 shows connections related to the test operation, and detailed connections of the clock system and the data system are omitted.

<Operation> The operation procedure of the test method using the test circuit of FIG. 9 will be described below. In the following description, the processing of the mark * is performed under the control of the PC (5600).

(1) An area for temporarily storing the internal state of the DSP (5100) “temporary storage area” is defined as Data-RA
M (5200). Furthermore, "temporary storage area"
The first word assigned to the “Write-po”
inter storage field ", the second word is" Br "
eak-counter storage field 1 ″, third WO
The rd-th is defined as “Break-counter storage field 2” (see FIG. 10A). For example, Dat
Address 0x3000 of a-RAM (5200) (0x is 1
When the address 0x3fff is set as the “temporary storage area” from the hexadecimal notation), the address 0x3000 becomes “Write-p”.
address 0x3001 is “Break-counter storage field 1”, 0
The address x3002 is “Break-counter storage field 2”.

(2) “Wri” assigned in (1)
In the “te-pointer storage field”, the value of “the start address of the temporary storage area + 3” (0x300 in the above example)
3) is stored *.

(3) In the processing of the application program, the two program addresses whose internal states are to be checked are stored in the break register 1 (5400) of the test circuit (5400).
402) and * stored in break register 2 (5404). For example, the Program-ROM shown in FIG.
The instruction at address 0x0100 (the instruction to transfer the input data of the filter operation to the a0 register (a0 is a register inside the DSP)) and the instruction at the address 0x0200 (the output data of the filter operation to the b0 register (b0 is the DSP)
To check the contents of the a0 register and the b0 register in the internal register)), the address 0x0100 is stored in the break register 1 (5402), and the address 0x0200 is stored in the break register 2 (5404).

(4) In order to transfer the internal state of the DSP to the “temporary storage area” at the breakpoints 1 and 2 set in (3), test programs corresponding to the breakpoints 1 and 2 respectively. Is stored in the test program memory (5408) of the test circuit (5400) *. Here, the write position in the “temporary storage area” is controlled using the Write-point stored in the “Write-pointer storage field” allocated in (1).

As an example, the DSP (5100) of the test program corresponding to breakpoint 1 transfers the internal state a0 register of the DSP to the “temporary storage area”.
An operation sequence for transferring the internal state of the data to the Data-RAM (5200) will be described. Breakpoint 2 is performed in a similar flow. (4-1) “Writ” of Data-RAM (5200)
Read the Write-point stored in the “e-pointer storage field”. (4-2) Transfer the internal state a0 register of the DSP (5100) to the address indicated by the Write-point. (4-3) Write Increment -point (4-4) If "Write-point> last address of temporary storage area", then Write-p
point is “the first address of the temporary storage area + 1”. (4-5) Write-point is changed to “Write-p
pointer storage field ".

(5) The number of steps of the program corresponding to each of breakpoint 1 and breakpoint 2 stored in test program memory (5405) in (4) is stored in test step register 1 (5406) of test circuit (5400). ) And test step register 2 (5
407).

(6) The operation of the DSP (5100) is started, and the application programs are sequentially executed. Program counter comparison circuit 1 (5401) and program counter comparison circuit 2 in test circuit (5400)
(5403) is the program count value (the value of the program counter (5101)) output from the program counter output terminal (5130) of the DSP (5100), and the break register 1 (5402) and the break register 2
The values stored in (5404) are compared one by one.

(7) If the result of the program counter comparison circuit 1 (5401) or the program counter comparison circuit 2 (5403) is "matched" in (6), W is output from the Wait output terminal (5431) of the test circuit (5400).
ait signal, and the DSP (5100) waits.
State. Furthermore, a test program selection output terminal (5
432), a signal indicating that the test program is selected is output. Program selection circuit (5500)
Are switched by a signal output from a test program selection output terminal (5432) of the test circuit (5400), and the test program output from the test program output terminal (5433) is switched to a program input terminal (5100) of the DSP (5100). 5132) and transferred to the instruction register (5102). Test circuit (540
0) is output from the test step register 1 (5406) or the test step register 2
The number of steps stored in (5407) is stored in the DSP (51
00). The test program flow is (4)
The test program corresponding to the generated break (breakpoint 1 or breakpoint 2) is output every execution cycle.

(8) After writing the internal state of the DSP in the “temporary storage area” by (7), the signals output from the Wait output terminal (5431) and the test program selection output terminal (5432) are restored to the original state. Return to the state, D
The operation of the SP is restarted.

(9) After repeating the operations (7) and (8), the DSP (5100) is stopped. DSP
After the stop of (5100), the Data-RAM control circuit (541) of the test circuit (5400) is sent from the PC (5600).
0), the data stored in the “temporary storage area” of the Data-RAM (5200) is read.

(10) The operation is verified using the data read on the PC (5600) in (9) (ie, the result of continuously outputting the internal state of the DSP (5100)).

In this embodiment, the test circuit (540)
Although the test program memory (5408) is provided in (0), the memory may be constituted by a register group, FIFO, or the like.

<Effects> As described above, according to the fifth embodiment, by using the test circuit (5400), the internal state in the real-time processing of the DSP (5100) can be confirmed, and the operation verification Can be easily performed. The result of the internal state of the DSP (5100) transferred to the PC (5600) is stored in the PC (56
It is also possible to display a waveform using the tool of (00) and to analyze a frequency component by FFT analysis.

In this embodiment, since two breakpoints can be set, it is possible to simultaneously confirm the input / output of the processing (operation) performed inside the DSP (5100) ( For example, input and output of filter operation). Thus, it is possible to easily confirm whether the processing (operation) inside the DSP (5100) is normally performed.

The data stored in the "temporary storage area" of the Data-RAM (5200) continuously writes the internal state of the DSP (5100) during real-time processing, and the entire "temporary storage area" is written. Then, the internal state of the next DSP (5100) is written by overwriting. For this reason, the DSP (5100) is stopped when it is desired to check the internal state of the DSP (5100), and
By transferring the data stored in the “temporary storage area” of the ta-RAM (5200) to the PC (5600),
It is possible to check the internal state of the DSP (5100) at an arbitrary time.

Further, by changing the program stored in the test program memory (5405) of the test circuit (5400), an arbitrary test can be executed.

Further, in the present system, two breakpoints can be set, but it is possible to extend to three or more breakpoints by the same method. In the present embodiment, the test program memory (5408) is provided in the test circuit (5400). However, the test circuit (5400) may be configured by a register group or FIFO in addition to the memory.

<Sixth Embodiment><Structure> FIG. 11 is a circuit diagram showing a sixth embodiment of the present invention, in which an LSI chip (6000) is a DSP.
(6100), Data-RAM (6200), Pro
Gram-ROM (6300), test circuit (640)
0) and a program selection circuit (6500). Further, a PC (6600) is connected to control the test circuit (6400).

The DSP (6100) includes a program counter (6101) and an instruction register (6102), and has a program counter output terminal (6130), a Wait input terminal (6131), and a program input terminal (6132).

The test circuit (6400) includes a program counter comparison circuit 1 (6401), a break register 1
(6402), the program counter comparison circuit 2 (640)
3), break register 2 (6404), test control circuit (6405), test step register 1 (640)
6), test step register (6407), break end register 1 (6408), break end register 2
(6409), test completion flag 1 (6410), test completion flag 2 (6411), test program memory (6412), test program output circuit (641)
3), a Data-RAM control circuit (6414), a PC interface circuit (6415), a program counter input terminal (6430), a Wait output terminal (643)
1), test program selection output terminal (6432), test program output terminal (6433), Data-RA
It has an M access terminal (6434) and a PC interface terminal (6435).

FIG. 11 shows connections related to the test operation, and detailed connections of the clock system and the data system are omitted.

<Operation> The operation procedure of the test method using the test circuit of FIG. 11 will be described below. In the following description, the processing of the mark * is performed under the control of the PC (6600).

(1) An area for temporarily storing the internal state of the DSP (6100) “temporary storage area” is defined as Data-RA
M (6200). Furthermore, "temporary storage area"
The first word assigned to the “Write-po”
inter storage field ", the second word is" Br "
eak-counter storage field 1 ″, third WO
The rd-th is defined as “Break-counter storage field 2” (see FIG. 12A). For example, Dat
Address 0x3000 of a-RAM (6200) (0x is 1
When the address 0x3fff is set as the “temporary storage area” from the hexadecimal notation), the address 0x3000 becomes “Write-p”.
address 0x3001 is “Break-counter storage field 1”, 0
The address x3002 is “Break-counter storage field 2”.

(2) “Write” assigned in (1)
In the “pointer storage field”, the value of “the start address of the temporary storage area + 3” (0x3003 in the above example)
To “Break-counter storage field 1”
And "Break-counter storage field 2"
Write zero to *.

(3) In the processing of the application program, the two program addresses whose internal states are to be checked are stored in the break register 1 of the test circuit (6400).
(6402) and break register 2 (6404). For example, Program- shown in FIG.
Instruction at address 0x0100 shown in ROM (instruction to transfer input data for filter operation to a0 register (a0 is DS
P), and an instruction (b0 to store the output data of the filter operation in the b0 register).
Are registers inside the DSP) a) and b in
To check the contents of the 0 register, the address 0x0100 is stored in the break register 1 (6402), and the address 0x0200 is stored in the break register 2 (6404).

(4) When the breakpoint 1 set in (3) occurs a specified number of times, the internal state of the DSP (6100) is changed to the Data-RAM when a break occurs thereafter.
In order to prevent the transfer to the “temporary storage area” of (6200), the designated end number is stored in the break end register 1 (6408) of the test circuit (6400) *. Similarly, break end register 2 for break point 2
(6409) is also set *.

(5) In order to transfer the internal state of the DSP to the “temporary storage area” at the breakpoints 1 and 2 set in (3), test programs corresponding to the breakpoints 1 and 2 respectively. Is stored in the test program memory (6412) of the test circuit (6400) *. Here, (1)
By using the Write-point stored in the “Write-pointer storage field” allocated in the above, the control of the writing position to the “temporary storage area” is performed by “B
"reak-counter storage field 1" or "B
Using the Break-count stored in the break-counter storage field 2 ", the DSP (6
100) is transferred to the “temporary storage area” of the Data-RAM (6200).

As an example, a case where the internal state a0 register of the DSP is transferred to the “temporary storage area”, the DSP (6100) of the test program corresponding to the breakpoint 1
An operation sequence for transferring the internal state of the data to the Data-RAM (6200) will be described. Breakpoint 2 is performed in a similar flow. (5-1) If the test completion flag 1 (6410) in the test circuit (6400) is "enable", the subsequent processing up to (5-10) is not performed. (5-2) “Writ” of Data-RAM (6200)
The write-point stored in the “e-pointer storage field” is read. (5-3) The internal state a0 register of the DSP (6100) is transferred to the address indicated by the write-point (5-4) Write Increment -point (5-5) If "Write-point> last address of temporary storage area", then Write-p
point is set to “head address of temporary storage area + 3”. (5-6) Write-point is changed to “Write-p
(5-7) "Brea" of the Data-RAM (6200).
The Break-count stored in the “k-counter storage field 1” is read out. (5-8) Break-point is incremented. (5-9) “Break-point> Break end register 1 of test circuit (6400) (Value of (6408)), the test completion flag 1 (6410) of the test circuit (6400) is set to “enable”. (5-10) Break-point is changed to “Break-point”.
Pointer storage field 1 ".

(6) The number of program steps corresponding to each of the breakpoints 1 and 2 stored in the test program memory (6412) in (5) is stored in the test step register 1 (6406) of the test circuit (6400). ) And test step register 2 (6
407).

(7) Test completion flag 1 (6410) and test completion flag 2 in test circuit (6400)
(6411) is set to “disable” *.

(8) The operation of the DSP (6100) is started, and the application programs are sequentially executed. Program counter comparison circuit 1 (6401) and program counter comparison circuit 2 in test circuit (6400)
(6403) is the program count value (the value of the program counter (6101)) output from the program counter output terminal (6130) of the DSP (6100), and the break register 1 (6402) and the break register 2
The values stored in (6404) are compared one by one.

(9) In (8), when the result of the program counter comparison circuit 1 (6401) or the program counter comparison circuit 2 (6403) is “matched”, W is output from the Wait output terminal (6431) of the test circuit (6400).
ait signal, and the DSP (6100) waits
State. Furthermore, a test program selection output terminal (6
432), a signal indicating that the test program is selected is output. Program selection circuit (6500)
Are switched by a signal output from a test program selection output terminal (6432) of the test circuit (6400), and the test program output from the test program output terminal (6433) is switched to a program input terminal ( 6132) and transferred to the instruction register (6102). Test circuit (640
0) from the test step register 1 (6406) or the test step register 2
The number of steps stored in (6407) is stored in the DSP (61).
00). Test program flow is (5)
The test program corresponding to the generated break (breakpoint 1 or breakpoint 2) is output every execution cycle.

(10) After writing the internal state of the DSP into the “temporary storage area” by (9), the signals output from the Wait output terminal (6431) and the test program selection output terminal (6432) are restored to the original state. Return to the state, D
The operation of the SP is restarted.

(11) After repeating the operations (9) and (10), the DSP (6100) is stopped. DS
The stop of P (6100) is performed by confirming that the test completion flag 1 (6410) or the test completion flag 2 (6411) in the test circuit (6400) is "enable". When the test completion flag 1 (6410) or the test completion flag 2 (6411) is “enable”, it means that the number of breaks stored in the break end register 1 (6408) or the break end register 2 (6409) has occurred. Show. After stopping the DSP (6100), the test circuit (6400) is sent from the PC (6600).
Through the Data-RAM control circuit (6414) of
The data stored in the “temporary storage area” of the data-RAM (6200) is read.

(12) The operation is verified using the data read on the PC (6600) in (11) (ie, the result of continuously outputting the internal state of the DSP (6100)).

In this embodiment, the test circuit (640)
Although the test program memory (6412) is provided in (0), the memory may be constituted by a register group, a FIFO, or the like. Further, the test circuit (640)
0), a break end register 1 (6408) and a break end register 2 (6409) are provided.
A method of providing the field in the RAM (6200) is also possible.

<Effects> As described above, according to the sixth embodiment, the internal state in the real-time processing of the DSP (6100) can be confirmed by using the test circuit (6400), and the operation verification Can be easily performed. Also, the result of the internal state of the DSP (6100) transferred to the PC (6600) is stored in the PC (66).
It is also possible to display a waveform using the tool of (00) and to analyze a frequency component by FFT analysis.

In this embodiment, since two breakpoints can be set, it is possible to simultaneously check the input / output of the processing (operation) performed inside the DSP (6100) (for example, , Filter operation input and output, etc.). Thus, it is possible to easily confirm whether the processing (operation) inside the DSP (6100) is normally performed.

Furthermore, the internal state of the DSP (6100) is
When the data is transferred to the data-RAM (6200), the transfer operation can be terminated by the number of times of occurrence of the break specified in each of the break end register 1 (6408) and the break register 2 (6409). DSP at the time of passing the specified number of times
It is possible to confirm the internal state of (6100).

Further, the test completion flag 1 (6410) or the test completion flag 2 (6411) in the test circuit (6400) determines whether or not the specified number of breaks has been reached.
Can be confirmed using the DSP (610)
The stop timing of 0) can be controlled. Further, by changing the program stored in the test program memory (6412) of the test circuit (6400), an arbitrary test can be executed.

Furthermore, in this method, two breakpoints can be set, but it is also possible to extend to three or more breakpoints by the same method. In the present embodiment, the test program memory (6412) is provided in the test circuit (6400). However, the test circuit may be constituted by a register group, a FIFO, or the like, in addition to the memory.

<Seventh Embodiment><Structure> FIG. 13 is a circuit diagram showing a seventh embodiment of the present invention, in which an LSI chip (7000) is a DSP.
(7100), Data-RAM (7200), Pro
Gram-ROM (7300), test circuit (740
0) and a program selection circuit (7500). Further, a PC (7600) is connected to control the test circuit (7400).

The DSP (7100) includes a program counter 1 (7101) and an instruction register (7102).
Program counter output terminal (7130), Wait input terminal (7131), program input terminal (7322)
Having. The test circuit (7400) includes a program counter comparison circuit 1 (7401) and a break register 1 (7
402), the program counter comparison circuit 2 (740
3), break register 2 (7404), test control circuit (7405), transfer start address register (740)
6), transfer end address register (7407), Wri
te-pointer storage register (7408), test program register (7409), test program output circuit (7410), Data-RAM control circuit (7
411), a PC interface circuit (7412), a program counter input terminal (7430),
t output terminal (7431), test program selection output terminal (7432), test program output terminal (743
3) It has a Data-RAM access terminal (7434) and a PC interface terminal (7435).

FIG. 13 shows connections related to the test operation, and detailed connections of the clock system and the data system are omitted.

<Operation> The operation procedure of the test method using the test circuit shown in FIG. 13 will be described below. In the following description, the processing of the mark * is performed under the control of the PC (7600).

(1) An area for temporarily storing the internal state of the DSP (7100) “temporary storage area” is defined as Data-RA
M (7200) (see FIG. 14A). For example, an address from 0x3000 (0x indicates hexadecimal notation) to 0x3fff of the Data-RAM (7200) is set as a “temporary storage area”.

(2) Value of “head address of“ temporary storage area ”allocated in (1) (0x300 in the above example)
0) in the transfer start address register (7406) of the test circuit (7400), and the value (0x3fff in the above example) of the “end address” in the transfer end address register (7400).
407). Further, the value of the “head address of the temporary storage area” is stored in the Write-pointer storage register (7408) *.

(3) In the processing of the application program, the two program addresses for which the internal state is to be confirmed are stored in the break register 1 of the test circuit (7400).
(7402) and * stored in break register 2 (7404). For example, Program-R in FIG.
Instruction at address 0x0100 shown in OM (Instruction to transfer input data of filter operation to a0 register (a0 is DSP
Registers a0 and b0 in the address 0x0200 (instruction for storing the output data of the filter operation in the b0 register (b0 is a register inside the DSP))
When checking the contents of the register, the address 0x0100 is stored in the break register 1 (7402), and the address 0x0200 is stored in the break register 2 (7404).

(4) In order to transfer the internal state of the DSP to the “temporary storage area” at the breakpoints 1 and 2 set in (3), test programs corresponding to the breakpoints 1 and 2 respectively. Is stored in the test program register (7409) of the test circuit (7400). For example, DSP
The value of the a0 register in (7100) is set to Data-R
When transferring to the AM (7200), the “mov instruction” as the transfer instruction and the “a0 register” as the transfer source are stored in the test program register (7409) (“mo
va a, "is stored. When transferring the b0 register," mov b0, "is stored.
The transfer positions of the “temporary storage area” in the data-RAM (7200) from the transfer start address register (7406), the transfer end address register (7407), and the write-point in the test circuit (7400)
The r storage register (7408) is used.

The DSP (7100) of the test program corresponding to breakpoint 1 is an example in which the internal state a0 register of the DSP is transferred to the “temporary storage area”.
An operation sequence for transferring the internal state of the data to the Data-RAM (7200) will be described. Breakpoint 2 is performed in a similar flow. (4-1) Write-po of test circuit (7400)
Read the Write-point stored in the inter storage register (7408). (4-2) The Write-point read out in (4-1) is added to the test program (“mov a0,”) stored in the test program register (7409) of the test circuit (7400) ( "Mov a
0, write-point ") and output from the test program output terminal (7433). (4-3) Increment Write-point. (4-4)"Write-point> Value of transfer end address register (7407) " ”, Wr
Item-point is transferred to the transfer start address register (74
06). (4-5) Write-point is changed to Write-po
The data is stored in the inter storage register (7408).

(5) The operation of the DSP (7100) is started, and the application programs are sequentially executed. Program counter comparison circuit 1 (7401) and program counter comparison circuit 2 in test circuit (7400)
(7403) is a program count value (the value of the program counter (7101)) output from the program counter output terminal (7130) of the DSP (7100), and the break register 1 (7402) and the break register 2
The values stored in (7404) are compared one by one.

(6) If the result of the program counter comparison circuit (7401) is "matched" in (5), a Wait signal is output from the Wait output terminal (7431) of the test circuit (7400) and the DSP (7100) To Wa
Set to the it state. Further, a signal indicating that the test program is selected is output from the test program selection output terminal (7432). Program selection circuit (750
0) is switched by a signal output from a test program selection output terminal (7432) of the test circuit (7400), and the test program output terminal (743) is switched.
The test program output from 3) is a DSP (710)
0) and is transferred to the instruction register (7102). Test circuit (7
The output of the test program from (400) is 1 word corresponding to breakpoint 1 or breakpoint 2.
Is output (see (4-2)).

(7) After writing the internal state of the DSP in the "temporary storage area" by (6), the signals output from the Wait output terminal (7431) and the test program selection output terminal (7432) are restored to the original state. Return to the state, D
The operation of the SP is restarted.

(8) After repeating the operations (6) and (7), the DSP (7100) is stopped. DSP
After the stop of (7100), the PC (7600) sends the Data-RAM control circuit (741) of the test circuit (7400).
Via 1), the data stored in the “temporary storage area” of the Data-RAM (7200) is read.

(9) The operation is verified using the data read on the PC (7600) in (8) (ie, the result of continuously outputting the internal state of the DSP (7100)).

In this embodiment, the test circuit (740)
0), the test program register (7409) is provided. However, the test program register (7409) may be configured by a memory or the like in addition to the register.

<Effects> As described above, according to the seventh embodiment, by using the test circuit (7400), the internal state in the real-time processing of the DSP (7100) can be confirmed, and the operation verification Can be easily performed. Also, the result of the internal state of the DSP (7100) transferred to the PC (7600) is
00) to display waveforms using the tool
The analysis makes it possible to analyze the frequency components.

In this embodiment, since two breakpoints can be set, the DSP (710)
0) It is possible to simultaneously confirm the input / output of the processing (computation) performed inside (for example, input and output of a filter computation). As a result, it is possible to easily confirm whether processing (operation) inside the DSP (7100) is performed normally.

Further, the internal state of the DSP (7100) is
When transferring data to the data-RAM (7200), 1 word
d test instruction, DSP
The time for setting (7100) to the Wait state can be short.
The data stored in the “temporary storage area” continuously writes the internal state of the DSP (7100) during the real-time processing. When the entire “temporary storage area” is written, the data of the next DSP (7100) is overwritten. The internal state is written. Therefore, the DSP (7100) is stopped when it is desired to check the internal state of the DSP (7100), and
By transferring the data stored in the “temporary storage area” of the ta-RAM (7200) to the PC (7600),
It is possible to check the internal state of the DSP (7100) at an arbitrary time.

Further, in the present system, two breakpoints can be set, but it is also possible to extend to three or more breakpoints by the same method. In the present embodiment, the test program register (7409) is provided in the test circuit (7400). However, the test circuit (7400) may be configured by a memory or the like in addition to the register.

<Eighth Embodiment><Structure> FIG. 15 is a circuit diagram showing an eighth embodiment of the present invention, in which an LSI chip (8000) is a DSP.
(8100), Data-RAM (8200), Pro
Gram-ROM (8300), test circuit (840)
0) and a program selection circuit (8500). Further, a PC (8600) is connected to control the test circuit (8400).

The DSP (8100) includes a program counter (8101) and an instruction register (8102), and has a program counter output terminal (8130), a Wait input terminal (8131), and a program input terminal (8132).

The test circuit (8400) includes a program counter comparison circuit 1 (8401), a break register 1
(8402), the program counter comparison circuit 2 (840)
3), break register 2 (8404), test control circuit (8405), transfer start address register (840)
6), transfer end address register (8407), Wri
te-pointer storage register (8408), break end register 1 (8409), break end register 2 (8410), break counter 1 (8411),
Break counter 2 (8412), test completion flag 1
(8413), test completion flag 2 (8414), test program register (8415), test program output circuit (8416), Data-RAM control circuit (8
417), a PC interface circuit (8418), a program counter input terminal (8430),
t output terminal (8431), test program selection output terminal (8432), test program output terminal (843)
3) It has a Data-RAM access terminal (8434) and a PC interface terminal (8435).

FIG. 15 shows connections related to the test operation, and detailed connections of the clock system and the data system are omitted.

<Operation> The operation procedure of the test method using the test circuit of FIG. 15 will be described below. In the following description, the processing of the mark * is performed under the control of the PC (8600).

(1) An area for temporarily storing the internal state of the DSP (8100) “temporary storage area” is defined as Data-RA
M (8200) (see FIG. 16A). For example, the address from 0x3000 (0x indicates hexadecimal notation) to 0x3fff in the Data-RAM (8200) is a “temporary storage area”.

(2) Value of “head address of temporary storage area” allocated in (1) (0x3000 in the above example)
Is stored in the transfer start address register (8406) of the test circuit (8400), and the value (0x3fff in the above example) of the “end address” is stored in the transfer end address register (840).
* Stored in 7). Further, the value of the “head address” of the “temporary storage area” is stored in the Write-pointer storage register (8408) *.

(3) In the processing of the application program, two program addresses whose internal states are to be checked are stored in the break register 1 of the test circuit (8400).
(8402) and * stored in break register 2 (8404). For example, Program-R in FIG.
Instruction at address 0x0100 shown in OM (Instruction to transfer input data of filter operation to a0 register (a0 is DSP
Instruction to store the output data of the filter operation in the b0 register (b0 is D
To check the contents of the a0 register and the b0 register in the SP), the address 0x0100 is stored in the break register 1 (8402) and the address 0x0200 is stored in the break register 2 (8404).

(4) When the breakpoint 1 set in (3) occurs a specified number of times, the internal state of the DSP (8100) is changed to the Data-RAM when a break occurs thereafter.
In order to prevent the transfer to the “temporary storage area” of (8200), the designated end number is stored in the break end register 1 (8409) of the test circuit (8200) *. Similarly, a break end register (8
410) is also set *.

(5) At the breakpoint 1 and the breakpoint 2 set in (3), in order to transfer the internal state of the DSP to the “temporary storage area”, a test corresponding to each of the breakpoint 1 and the breakpoint 2 is performed. The program is stored in the test program register (8415) from the test circuit (8400) *. For example, D
The value of the a0 register in SP (8100) is set to Data
When transferring to the RAM (8200), the “mov instruction” as the transfer instruction and the “a0 register” as the transfer source are stored in the test program register (8415) (“m
ov a0, ”is stored. When the b0 register is transferred,“ mov b0, ”is stored.
100) to the “temporary storage area” of the Data-RAM (8200), the transfer start address register (8406), the transfer end address register (8407), and the write-point in the test circuit (8100).
er storage register (8408) is used.

As an example, the DSP (8100) of the test program corresponding to the breakpoint 1 transfers the internal state a0 register of the DSP to the “temporary storage area”.
The following describes an operation sequence for transferring the internal state of the data to the “temporary storage area” of the Data-RAM (8200). Breakpoint 2 is performed in a similar flow. (5-1) If the test completion flag 1 (8413) in the test circuit (8100) is "enable", the subsequent processing up to (5-9) is not performed. (5-2) Write-po of test circuit (8400)
Read the Write-point stored in the inter storage register (8408). (5-3) The Write-point read in (4-1) is added to the test program (“mov a0,”) stored in the test program register (8415) of the test circuit (8400) ( "Mov a
0, write-point ") and output from the test program output terminal (8433). (5-4) Increment write-point. (5-5)"Write-point> value of transfer end address register (8407) ”, Wr
The item-point is transferred to the transfer start address register (84
06). (5-5) Write-point is changed to Write-po
Write to the inter storage register (8408). (5-6) Read break-count from break counter 1 (8411) of test circuit (8400). (5-7) Break-point is incremented. (5-8) When “break-count> break end register 1 (8409) value”, the test completion flag 1 (8413) of the test circuit (8400) is set to “enable”. (5-9) Break-point is stored in break counter 1 (8411).

(6) The operation of the DSP (8100) is started, and the application programs are sequentially executed. Program counter comparison circuit 1 (8401) and program counter comparison circuit 2 in test circuit (8400)
(8403) is a program count value (the value of the program counter (8401)) output from the program counter output terminal (8130) of the DSP (8100), and the break register 1 (8402) and the break register 2
The values stored in (8404) are compared one by one.

(7) If the results of the program counter comparison circuit (8401) and the program counter comparison circuit 2 (8403) match in (6), the Wait signal from the Wait output terminal (8431) in the test circuit (8400) Is output, and the DSP (8100) is
Set to the it state. Further, a signal indicating that the test program is selected is output from the test program selection output terminal (8432). Program selection circuit (850
0) is switched by a signal output from a test program selection output terminal (8432) of the test circuit (8400), and the test program output terminal (843) is switched.
The test program output from 3) is a DSP (810)
0), and is transferred to the instruction register (8102). Test circuit (8
The output of the test program from (400) is 1 word corresponding to breakpoint 1 or breakpoint 2.
Is output (see (5-3)).

(8) After the internal state of the DSP is written in the “temporary storage area” in (6), the signals output from the Wait output terminal (8431) and the test program selection output terminal (8432) are restored to the original state. Return to the state, D
The operation of the SP is restarted.

(9) After repeating the operations (6) and (7), the DSP (8100) is stopped. DSP
After the stop of (8100), the PC (8600) sends the Data-RAM control circuit (841) of the test circuit (8400).
7), the data stored in the “temporary storage area” of the Data-RAM (8200) is read.

(10) The operation is verified using the data read on the PC (8600) in (8) (ie, the result of continuously outputting the internal state of the DSP (8100)).

In this embodiment, the test circuit (840)
Although the test program register (8415) is provided in (0), the test program register (8415) may be constituted by a memory or the like in addition to the register.

<Effects> As described above, according to the eighth embodiment, the internal state in the real-time processing of the DSP (8100) can be confirmed by using the test circuit (8400), and the operation verification Can be easily performed. Also, the result of the internal state of the DSP (8100) transferred to the PC (8600) is stored in the PC (86).
It is also possible to display a waveform using the tool of (00) and to analyze a frequency component by FFT analysis.

In the present embodiment, since two breakpoints can be set, it is possible to simultaneously confirm the input / output of the processing (operation) performed inside the DSP (8100) (for example, , Filter operation input and output, etc.). Thus, it is possible to easily confirm whether the processing (operation) inside the DSP (8100) is performed normally.

Further, the internal state of the DSP (8100) is
When transferring data to the data-RAM (8200), 1 word
d test instruction, DSP
(8100) can be in the Wait state in a short time.
Further, the internal state of the DSP (8100) is changed to Data-RA
M (8200), the transfer operation can be terminated with the specified number of occurrences, so the DSP (8
100) can be confirmed.

Further, the test completion flag 1 (8413) or the test completion flag 2 (8414) in the test circuit (8400) determines whether the specified number of breaks has been reached.
Can be confirmed using the DSP (810
The stop timing of 0) can be controlled.

Further, in the present system, two breakpoints can be set, but it is also possible to extend to three or more breakpoints by the same method. In the present embodiment, the test program register (8415) is provided in the test circuit (8400). However, the test circuit (8400) may be configured by a memory or the like in addition to the register.

[0173]

As described above in detail, according to the present invention, there is provided a test circuit mounted on a single chip for verifying the operation of a DSP mounted on an LSI chip in real time. Means for holding a specified breakpoint of a program whose internal state is to be detected, and means for detecting, in the operating state of the DSP, a match between the breakpoint held by the holding means and a program counter value inside the DSP. Means for switching the operation program of the DSP to a test program for extracting internal state data of the DSP when a match is detected by the detection means, and switching the operation program of the DSP to a test program by the switching means. Because it was configured to extract the internal state of the It is possible to check the internal state of the real-time processing, it is easy to verify the operation. Further, by transferring this internal state to an external PC, it becomes possible to display a waveform of audio data using a tool on the PC, and to analyze a frequency component by FFT analysis.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a circuit according to a first embodiment of the present invention.

FIG. 2 (a) Data-R in the first embodiment
It is explanatory drawing of AM. (B) Program-RO in the first embodiment
It is explanatory drawing of M.

FIG. 3 is a configuration diagram of a circuit according to a second embodiment of the present invention.

FIG. 4 (a) Data-R in the second embodiment
It is explanatory drawing of AM. (B) Program-RO in the second embodiment
It is explanatory drawing of M.

FIG. 5 is a configuration diagram of a circuit according to a third embodiment of the present invention.

FIG. 6A shows Data-R in the third embodiment.
It is explanatory drawing of AM. (B) Program-RO in the third embodiment
It is explanatory drawing of M.

FIG. 7 is a configuration diagram of a circuit according to a fourth embodiment of the present invention.

FIG. 8A shows Data-R in the fourth embodiment.
It is explanatory drawing of AM. (B) Program-RO in the fourth embodiment
It is explanatory drawing of M.

FIG. 9 is a circuit diagram showing a fifth embodiment of the present invention.

FIG. 10A shows Data- in the fifth embodiment.
FIG. 3 is an explanatory diagram of a RAM. (B) Program-RO in the fifth embodiment
It is explanatory drawing of M.

FIG. 11 is a configuration diagram of a circuit according to a sixth embodiment of the present invention.

FIG. 12A shows Data- in the sixth embodiment.
FIG. 3 is an explanatory diagram of a RAM. (B) Program-RO in the sixth embodiment
It is explanatory drawing of M.

FIG. 13 is a configuration diagram of a circuit according to a seventh embodiment of the present invention.

FIG. 14A shows Data- in the seventh embodiment.
FIG. 3 is an explanatory diagram of a RAM. (B) Program-RO in the seventh embodiment
It is explanatory drawing of M.

FIG. 15 is a configuration diagram of a circuit according to an eighth embodiment of the present invention.

FIG. 16A shows Data- in the eighth embodiment.
FIG. 3 is an explanatory diagram of a RAM. (B) Program-RO in the eighth embodiment
It is explanatory drawing of M.

FIG. 17 is a schematic diagram of the prior art.

[Explanation of symbols]

1000, 2000, 3000, 4000, 5000,
6000, 7000, 8000 LSI chips 1100, 2100, 3100, 4100, 5100,
6100, 7100, 8100 DSP 1200, 2200, 3200, 4200, 5200,
6200, 7200, 8200 Data-RAM 1300, 2300, 3300, 4300, 5300,
6300, 7300, 8300 Program-R
OM 1400, 2400, 3400, 4400, 5400,
6400, 7400, 8400 Test circuit 1500, 2500, 3500, 4500, 5500,
6500, 7500, 8500 Program selection circuit 1600, 2600, 3600, 4600, 5600,
6600, 7600, 8600 PC

Claims (9)

[Claims] 1. A test circuit mounted on the same chip for verifying the operation of a DSP mounted on an LSI chip in real time, the breakpoint being specified in a program for detecting an internal state of the DSP. Means for detecting a match between the break point held by the holding means and a program counter value inside the DSP in the operation state of the DSP; and a DSP when the match is detected by the detection means.
Means for switching the operation program to a test program for extracting internal state data of the DSP; and a method for extracting the internal state of the DSP in real time by switching the operation program of the DSP to a test program by the switching means. circuit. 2. The test circuit according to claim 1, wherein
The internal state of the DSP is temporarily changed to Data-R on the LSI chip.
AM, and the data is transferred to the Data-RAM control circuit and the PC interface circuit on the test circuit.
By transferring RAM data to an external PC, DS
A test circuit for verifying an internal state in P real-time processing. 3. The test circuit according to claim 1, wherein
Up to the specified number of breaks for the specified breakpoint, the internal state of the DSP
a-RAM and transfer it to the Data-RAM on the test circuit.
Through the control circuit and the PC interface circuit.
A test circuit for verifying an internal state in real-time processing of a DSP by transferring data of a ta-RAM to an external PC. 4. The test circuit according to claim 1, wherein
The internal state of the DSP with respect to a specified breakpoint is described by a 1-word test instruction in the Data-RAM.
To the Data-RA via the Data-RAM control circuit and the PC interface circuit on the test circuit.
A test circuit for verifying an internal state in real-time processing of a DSP by transferring M data to an external PC. 5. The test circuit according to claim 1, wherein
The internal state of the DSP is transferred to the Data-RAM by a 1-word test instruction up to the specified number of break occurrences for the specified breakpoint, and the data is transferred via the Data-RAM control circuit and the PC interface circuit on the test circuit. A test circuit for verifying an internal state in real-time processing of the DSP by transferring data of the Data-RAM to an external PC. 6. The test circuit according to claim 1, wherein
The internal state of the DSP is transferred to the Data-RAM with respect to the two designated breakpoints, and the data of the Data-RAM is transferred to the external PC via the Data-RAM control circuit and the PC interface circuit on the test circuit. A test circuit for verifying an internal state in real time processing of a DSP by transferring the test. 7. The test circuit according to claim 1, wherein
The internal state of the DSP is changed up to the specified number of break occurrences for the specified two break points by the D
Data-R on the test circuit
A test circuit for verifying an internal state in real-time processing of a DSP by transferring data of the Data-RAM to an external PC via an AM control circuit and a PC interface circuit. 8. The test circuit according to claim 1, wherein
The internal state of the DSP with respect to the two specified breakpoints is described by the above-mentioned Data-
The data is transferred to the RAM, and the Data-RAM control circuit and the PC interface circuit on the test circuit are used to transfer the data to the RAM.
-By transferring RAM data to an external PC,
A test circuit for verifying an internal state in real-time processing of an SP. 9. The test circuit according to claim 1, wherein
The internal state of the DSP is changed by one word until the specified number of breaks has occurred for the specified two breakpoints.
rd test instruction, the data is transferred to the Data-RAM, the Data-RAM control circuit on the test circuit and the PC
A test circuit for verifying an internal state in real time processing of a DSP by transferring data of the Data-RAM to an external PC via an interface circuit.