JP2001228932A - Real-time clock device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a real-time clock device by which whether internal data is correct can be discriminated by detecting the oscillation stoppage of an oscillation circuit and the cause and the corresponding method of the oscillation stoppage of the oscillation circuit can be decided in detail. SOLUTION: The presence/absence of the clock output of the oscillation circuit 1 is detected by an oscillation stoppage detection circuit 2, whether a power voltage VDD is higher or lower than a prescribed level is detected by a power voltage dropping detection circuit 3, and the rising of a power source is detected by a power on detection circuit 4. The results of these detections are stored in registers REG1, REG2 and REG3. Based on the contents of them, the cause of oscillation stoppage and the measure for it are decided. 5 is a frequency divided circuit, 6 is a time counter, 8 is an input and output control part, 9 is a nonvolatile memory circuit, and 10 is an MPU (microprocessor unit).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to various types of computers, OA equipment with built-in microcomputers, mobile phones,
For real-time clock devices incorporated in household appliances such as video equipment, vending machines, etc., in particular, detect the oscillation stop of the oscillation circuit, judge whether the internal data is accurate or not, and also judge the cause of the oscillation stop. The present invention relates to a real-time clock device capable of performing the following.

[0002]

2. Description of the Related Art In the information processing society in recent years, mechanization has progressed in various fields, and various computers, OA devices with built-in microcomputers, and home appliances have become widespread. Such a device usually includes a real-time clock device (clock device). The real-time clock device is usually backed up by a standby power supply different from the main power supply on the MPU (microprocessor unit) side in order to stop the operation as much as possible.

In such a real-time clock device, it is necessary to constantly monitor whether or not the internal clock data is destroyed due to a drop in power supply voltage or the like. The clock data is temporarily stored in the memory, and then the clock data stored in the memory is compared with the clock data newly read from the real-time clock device. , It was determined that the clock data was incorrect.
However, in that case, an extra memory area is required, and complicated processing such as comparison processing and judgment processing must be performed by a program.

[0004] To solve this problem, Japanese Patent No. 272 is disclosed.
There is a real-time clock device (hereinafter, referred to as a prior art) disclosed in Japanese Patent No. 2507 (Japanese Patent Laid-Open No. 2-32413). FIG. 5 is a diagram showing a configuration of a real-time clock device proposed in the above-mentioned conventional technology.

In this prior art, a clock output of an oscillation circuit 10 composed of a piezoelectric vibrator such as a crystal vibrator is divided by a frequency dividing circuit 4.
In a real-time clock device which is set in registers of the logic circuit 50 through 0, an oscillation detection circuit 20 and an oscillation stop detection flag 30 (flip flop) are provided.
By detecting that the oscillation has stopped, an oscillation stop detection flag 30 is set based on this detection output, and the oscillation stop detection flag 30 is monitored from the MPU side, so that the internal clock data and data of the registers are valid. It is determined whether or not this is the case.

FIGS. 6A and 6B are diagrams for explaining the oscillation detection circuit 20. FIG. 6A shows an example of the configuration of the oscillation detection circuit 20, and FIG. 6B shows the principle thereof. In the figure, G1 is an inverter circuit, G2 is a NAND circuit, and P1 and P2 are P-channel MOS transistors (FIG. 4 (b)
, R1 and R2 are resistors, C1 and C2 are capacitors, VDD is a drain voltage, and VSS is a source voltage.

In this circuit, when the P-channel MOS transistors (P1, P2) are turned on, the charges of the capacitors (C1, C2) are transferred to the capacitors (R1, R2) through the resistors (R1, R2).
Discharge is performed according to the time constant of 1.R1 and C2.R2.
In this case, by setting the time constants of C1 · R1 and C2 · R2 to be sufficiently longer than half of the cycle of the output of the oscillation circuit 10, as long as the clock output of the oscillation circuit 10 is constantly input, the P-channel MOS Transistors P1 and P2
Are periodically and alternately turned on, and none of the inputs of the NAND circuit G2 does not become lower than the threshold voltage. Therefore, the output of the NAND circuit G2, that is, the output of the oscillation detection circuit 20 becomes low level and the oscillation continues. Show.

However, when the oscillation of the oscillation circuit 10 stops and the clock output stops, one of the inputs of the NAND circuit G2 becomes lower than the threshold voltage, and the output of the NAND circuit G2, that is, the output of the oscillation detection circuit 20 becomes It becomes high level, indicating that the oscillation of the oscillation circuit 10 has stopped. The output of the oscillation detection circuit 20 is set in the oscillation stop detection flag 30. FIG. 6 shows only one example of detecting the stop of the oscillation, and may have any configuration as long as the stop of the oscillation can be detected.

The minimum operating power supply voltage of the oscillation circuit 10 is usually set higher than the minimum data holding voltage of a counter or register in the logic circuit 5.

[0010]

According to the above-mentioned prior art, an extra memory area is not required, and comparison processing and judgment processing by a program are not required. The main purpose is to determine whether the clock data is valid or invalid. Even if it is determined that the clock data is invalid by the output of the oscillation detection circuit indicating that the oscillation circuit has stopped oscillating, the cause is unknown. Therefore, it was not clear what kind of treatment should be performed.

For example, if the cause of the oscillation circuit's oscillation stop is a drop in the power supply voltage, the battery needs to be replaced, while the cause of the oscillation circuit's oscillation stop is abnormal extraneous noise or abnormal power supply noise. Or, in the case of dew condensation, the real-time clock data must be initialized, but in the above-described conventional technology, it is only possible to determine that the oscillation of the oscillation circuit has stopped, and the cause of the oscillation stop is determined. Since it was not possible, there was a problem that it was not known what kind of countermeasures should be taken.

Further, the above-mentioned prior art is effective when the power supply voltage continuously drops due to a power failure or the like, but is effective when the power supply voltage drops momentarily (for a momentary interruption) for some reason. Not valid. That is, when an instantaneous interruption of the power supply voltage occurs, it is necessary to detect the instantaneous interruption and invalidate (clear) the clock data. However, the above-described conventional technique has a problem that such an instantaneous interruption cannot be detected.

The present invention solves the above problems, detects the oscillation stop of the oscillation circuit, determines whether the internal data is accurate or not, and determines whether the oscillation stop of the oscillation circuit was impossible in the prior art. It is an object of the present invention to provide a real-time clock device capable of determining a cause and a countermeasure (treatment method) for stopping oscillation.

Specifically, the inventions according to claims 1 and 2 are:
It is an object of the present invention to provide a real-time clock device capable of detecting oscillation stop, power-on, and power supply voltage drop of an oscillation circuit, and determining the cause of the oscillation stop and a countermeasure based on the detected results.

The invention according to claim 3 is to provide the condition of the detection level of the oscillation stop detection circuit and the power supply voltage drop detection circuit in that case. According to a fifth aspect of the present invention, there is provided a real-time clock device in which a detection result of each of the detection circuits is stored in a non-volatile manner so that subsequent analysis and analysis can be performed. The purpose is.

[0016]

According to a first aspect of the present invention, there is provided a real-time clock device for generating a real-time clock by dividing a clock output of an oscillation circuit. A counter (6) for counting a real-time clock, an oscillation stop detection circuit (2) for detecting whether or not the clock output of the oscillation circuit (1) has stopped, and a power-on detection circuit (4) for detecting power-on A power supply voltage drop detection circuit (3) for detecting a drop in power supply voltage; a first storage unit (REG1) for holding an output of the oscillation stop detection circuit (2); and an output of a power-on detection circuit (4). A second storage unit (REG3) for storing
A third storage unit (REG2) for holding an output of the power supply voltage drop detection circuit (3) is provided.

According to a second aspect of the present invention, in the real-time clock device according to the first aspect, the first storage unit (R
EG1), the contents of the second storage unit (REG3) and the contents of the third storage unit (REG2), the cause of the oscillation stop, and the means (MPU) for determining the subsequent processing contents are provided. Features.

The third aspect of the present invention is the first or second aspect.
In the real-time clock device described above, the power supply voltage level when the oscillation of the oscillation circuit (1) stops due to the decrease of the power supply voltage and the oscillation stop detection circuit (2) detects it is determined by the power supply voltage drop detector (3). ) Is set lower than the power supply voltage level at which the reduction of the power supply voltage is detected.

According to a fourth aspect of the present invention, in the real-time clock device according to any one of the first to third aspects, the oscillation stop detecting circuit (2), the power supply voltage drop detecting circuit (3), and the power-on detecting circuit are provided. The circuit (4) is provided in a single semiconductor chip.

According to a fifth aspect of the present invention, in the real-time clock device according to the fourth aspect, a non-volatile memory circuit (9) is further provided in the semiconductor chip, and the oscillation stop detecting circuit (2) provides an oscillation circuit. When the stop of the oscillation of (1) is detected, the power supply voltage drop detection circuit (3) detects the power supply voltage drop, or the power-on detection circuit (4) detects power-on. , The value of the counter (6) is transferred to the memory circuit (9) and held.

[0021]

FIG. 1 is a block diagram of a real-time clock device according to the present invention. In FIG. 1, reference numeral 1 denotes an oscillation circuit that supplies a clock from a piezoelectric vibrator such as a crystal vibrator, 2 denotes an oscillation stop detection circuit that determines the presence or absence of a clock output from the oscillation circuit, and 3 denotes whether the power supply voltage VDD is higher than a predetermined level. A power supply voltage drop detection circuit 4 for determining whether or not the power supply voltage is below is a power-on detection circuit for detecting a rise of the power supply. In general, a power-on reset mechanism for resetting (initializing) an internal circuit when power-on is detected is provided, and this mechanism and the power-on detection circuit 4 are combined to form a power-on clear circuit. I have.

Reference numeral 5 denotes a frequency dividing circuit for dividing the output of the oscillation circuit, and reference numeral 6 denotes a time counter (second, minute, hour, date, day of the week, month, year, etc.) for counting the output of the frequency dividing circuit. And 7, a register REG holding an output signal of the oscillation stop detection circuit 2, a register REG2 holding an output signal of the power supply voltage drop detection circuit 3, and a register REG3 holding an output signal of the power-on detection circuit 4. (Registers REG1 to REG3 may be separately provided as individual registers, but a partial area of a storage unit such as a RAM may be used as a register), 8 is an input / output control unit, Reference numeral 9 denotes a memory circuit capable of saving and holding the contents of the registers REG1 to REG3 and the content of the time counter 6, and reference numeral 10 denotes an MPU (microprocessor unit). The contents of the time counter 6, the register group 7, and the memory circuit 9 can be referred to from the MPU via the input / output control unit 8. The above components are provided on the same semiconductor chip.

Of these blocks, the oscillation circuits 1 and 2
The oscillation stop detecting circuit 2 and the frequency dividing circuit 5 are the same as the oscillation circuit 10, the oscillation detecting circuit 20, and the frequency dividing circuit 50 in the above-mentioned conventional technology. The present invention achieves the above object of the present invention by newly adding a power supply voltage drop detection circuit 3, a power-on detection circuit 4, and a memory circuit 9 to the above-described conventional technology. Although the time counter 6 and the register group 7 in FIG. 1 correspond to the logic circuit 50 in the above-described conventional technology, as described above,
The register group 7 in FIG. 1 is configured to hold respective outputs of the oscillation stop detection circuit 2, the power supply voltage drop detection circuit 3, and the power-on detection circuit 4.

FIG. 2 is a diagram showing an example of a circuit configuration of the power supply voltage drop detection circuit 3. As shown in FIG. The power supply voltage drop detection circuit 3
For example, as shown in the figure, a divided voltage of the power supply voltage VDD obtained from a connection point of the resistors R20 and R21 provided in series between the power supply voltage VDD and the ground potential is used as one input,
The power supply voltage drop detection signal VDE is supplied from the voltage comparator 21 having the reference voltage VR obtained from the reference voltage source 22 as the other input.
T is a circuit that obtains a power supply voltage VDD equal to or higher than a predetermined voltage level (in this case, VDD is (R20 + R21) VR
/ R21 or more), a circuit that outputs a high-level (“1”) power supply voltage drop detection signal VDET.

FIG. 3 is a diagram for explaining the power-on detection circuit 4. FIG. 3A shows an example of the circuit configuration.
FIG. 3B shows the voltage level at each point of the circuit. The power-on detection circuit 4 is, for example, as shown in FIG. 2A, a divided voltage of the power supply voltage VDD obtained from a connection point A of the resistor R30 and the capacitor C30 provided in series between the power supply voltage VDD and the ground potential. Is connected to the gates of a P-channel MOS transistor T1 and an N-channel MOS transistor T2 which are also provided in series between the power supply voltage VDD and the ground potential, and power is supplied from a connection point B between the P-channel MOS transistor T1 and the N-channel MOS transistor T2. This is a circuit that outputs an on-clear signal POC.

In this circuit configuration, as shown in FIG. 2B, when the power supply voltage VDD is 0 volt (ground potential), the potential at the point A is also 0 volt, the P-channel MOS transistor T1 is on, and the N-channel MOS transistor T2
Is off. When the power supply voltage VDD starts rising from 0 volts, the voltage at the point A is also increased accordingly, and the voltage at the point B (that is, the power-on clear signal PO) is passed through the on-state P-channel MOS transistor T1.
C) will also be raised. However, when the voltage at point A exceeds a predetermined voltage, P-channel MOS transistor T1
Turns off and the N-channel MOS transistor T2 turns on
, And the voltage at the point B (the power-on-clear signal POC) drops to 0 volt (ground potential). As a result, when the power supply voltage VDD rises, a pulse-like power-on-clear signal POC is output.

FIG. 4 is a diagram showing the relationship between the detection result of each detection circuit according to the present invention, the cause of the oscillation stop, and a countermeasure (treatment method) for the cause. In the figure, POC is a power-on clear signal output from a power-on detection circuit 4, XST is an oscillation stop detection signal output from an oscillation stop detection circuit 2, and VDET is a power supply voltage drop output from a power supply voltage drop detection circuit. The detection signals represent "1 (high level)" when active. “*” Indicates that “1 (high level)” or “0 (low level)” may be used.

FIG. 4 shows a power-on clear signal POC, an oscillation stop detection signal XST, and a power supply voltage drop detection signal VDET.
Each value, the meaning of the state, the cause of the state, and a countermeasure (treatment method) indicating how to cope when the state occurs are shown.

More specifically, FIG. 4A shows a case where the power-on clear signal POC and the power supply voltage drop detection signal VDET are "0", but the oscillation stop detection signal XST is "1". That is, it is a case where only the oscillation is stopped. As a factor in this case, it is considered that the oscillation circuit is stopped due to dew condensation or occurrence of abnormal noise. In this case, since the data is no longer correct due to the stop of the oscillation, it is necessary to initialize the data as a countermeasure (treatment method).

In (b), the power-on-clear signal POC is "0", but the oscillation stop detection signal XST and the power supply voltage drop detection signal VDET are "1", that is, the oscillation stops and the power supply voltage drops. This is a case, and the cause of this case may be that the battery is consumed. In this case, it is necessary to replace or charge the depleted battery, and since the data is no longer correct due to the stop of oscillation and the drop in the power supply voltage, it is necessary to initialize the data as a countermeasure (treatment method). There is also.

(C) shows a power-on clear signal POC,
This is a case where the oscillation stop detection signal XST and the power supply voltage drop detection signal VDET are all "0", that is, a case where no abnormality is detected in each of the above detection circuits. In this case, the real-time clock device is normal. You do not need to take any special measures.

In (d), the power-on clear signal POC and the oscillation stop detection signal XST are "0", but the power supply voltage drop detection signal VDET is "1", that is, the oscillation does not occur and the oscillation does not occur. Although the power supply voltage continues to decrease, the cause of this case may be that the battery is consumed. In this case, the spent battery needs to be replaced or charged. In this case, since the data is still normal, there is no need to initialize the data.

(E) is a case where the power-on clear signal POC and the oscillation stop detection signal XST are both "1" (the power supply voltage drop detection signal VDET may be either "1" or "0"). This means that the rise of the power supply and the stop of the oscillation have been detected, and this is a state that occurs when the power supply is newly started up. Factors that may cause this state include a case where the power is newly turned on after the recovery from the power failure and a case where the battery is replaced.
In this case, since the data has become incorrect, it is necessary to initialize the data as a countermeasure (treatment method).

(F) is a case where the power-on clear signal POC is "1" and the oscillation stop detection signal XST is "0" (the power supply voltage drop detection signal VDET is "1" or "0"). Either case may be considered), and a factor of this case may be an instantaneous interruption of the power supply. Even if the power supply is momentarily turned off for a short time, oscillation does not stop due to the characteristics of the crystal oscillator constituting the oscillation circuit 1. Also in this case, since the data has become incorrect due to a drop in the power supply voltage, it is necessary to initialize the data as a countermeasure (treatment method).

In this embodiment, as can be seen from FIG. 4, the power-on clear signal POC, the oscillation stop detection signal XST,
Depending on the value of the power supply voltage drop detection signal VDET,
It is possible to identify the cause of various abnormalities such as the stop of the oscillation and the drop in the power supply voltage, and the method of dealing with the abnormalities (method of treatment) changes depending on the cause of the abnormalities.

Accordingly, the power-on clear signal POC, the oscillation stop detection signal XST, the power supply voltage drop detection signal VDET
Each value is stored in each of the registers REG1-R of the register group 7.
By storing the values in the EG3 and recognizing and analyzing those values on the MPU side, the state of the abnormality and a method of coping with the abnormality (treatment method) can be determined, and this is displayed on a display device or the like to notify the user. If the countermeasure (treatment method) such as replacement or charging of the battery is prompted, or if the countermeasure is data initialization, the data is automatically initialized by executing the initialization program in the MPU. It is also possible to make it.

The value of the time counter 6 (second, minute,
The values (POC, XST, VDET) held in the registers REG1, REG2, REG3 in the register group are stored in, for example, a non-volatile memory circuit 9. To the MPU whenever necessary, even after power is turned off.
The data can be analyzed on the (microprocessor unit) side, displayed on a display device, or output to a printer, so that the date and time of occurrence of an abnormality, its state, a coping method, and the like can be analyzed.

Further, each time a new event occurs (PO
Each time the state of C, XST or VDET changes),
The value of the time counter 6 at that time and each register REG
1, REG2, REG3 (POC,
By storing (XST, VDET) in the memory circuit 9, it is possible to analyze the time statistic of the occurrence of an abnormality, which is extremely effective for an abnormality prevention measure.

In the above-described embodiment, an example in which an oscillation stop detection circuit, a power supply voltage drop detection circuit, and a power-on detection circuit are provided, and a processing method (treatment method) is determined based on the output results of these three detection circuits. Although shown, it is also possible to determine the processing method (treatment method) based on the output results of the oscillation stop detection circuit and the power-on detection circuit.

In this embodiment, the power supply voltage level when the oscillation of the oscillating circuit stops due to a drop in the power supply voltage and is detected by the oscillation stop detection circuit is determined by the power supply voltage drop detector. Is set lower than the power supply voltage level when it is detected that the power supply voltage has decreased. This is because, for example, when the power supply voltage gradually decreases, the clock stoppage of the oscillation circuit is stopped by the oscillation stop detection circuit, and if the decrease in the power supply voltage is not detected, incorrect clock data is recognized as correct. This is because a malfunction occurs.

[0041]

As described above, according to the present invention, the stop of the oscillation of the oscillation circuit is detected to determine whether or not the internal data is accurate. It is possible to realize a real-time clock device capable of determining the cause of the stop and the method of coping thereafter.

More specifically, according to the first and second aspects of the present invention, the stop of oscillation, power-on, and decrease in power supply voltage of the oscillation circuit are detected. It is possible to determine in detail.

According to a third aspect of the present invention, there is provided a power supply voltage level when the oscillation stop detecting circuit necessary for detecting the oscillation stops and a power supply voltage when the power supply voltage drop detecting circuit detects a drop in the power supply voltage. According to the fourth and fifth aspects of the present invention, each of the detection circuits is provided in the same semiconductor chip, and the detection result of each of the detection circuits is stored in a nonvolatile manner in a memory circuit on the same semiconductor chip. And later analysis and analysis become possible.

[Brief description of the drawings]

FIG. 1 is a block diagram of a real-time clock device according to the present invention.

FIG. 2 is a diagram illustrating an example of a circuit configuration of a power supply voltage drop detection circuit.

FIG. 3 is a diagram illustrating a power-on detection circuit.

FIG. 4 is a diagram showing a relationship between a detection result of each detection circuit in the present invention, a cause of oscillation stop, and a countermeasure (treatment method) for the cause.

FIG. 5 is a diagram showing a configuration of a real-time clock device proposed in the prior art.

FIG. 6 is a diagram illustrating an oscillation detection circuit.

[Explanation of symbols]

 1: Oscillation circuit 2: Oscillation stop detection circuit 3: Power supply voltage drop detection circuit 4: Power-on detection circuit 5: Frequency divider circuit 6: Time counter 7: Register group REG1 to REG3: Register 8: I / O controller 9: Memory Circuit 10: MPU (microprocessor unit) 21: Voltage comparator 22: Reference voltage source 100: Oscillation circuit 200: Oscillation detection circuit 300: Oscillation stop flag detection circuit 400: Frequency dividing circuit 500: Logic circuit

 ────────────────────────────────────────────────── ─── Continued on front page (72) Inventor Katsunori Yoshinaka 1-3-6 Nakamagome, Ota-ku, Tokyo F-term in Ricoh Co., Ltd. (reference) 2F002 AA00 AD03 AD06 AD07 AD08 AE01 CB02 GA04

Claims (5)

[Claims] 1. A real-time clock device for generating a real-time clock by dividing the clock output of an oscillation circuit, comprising: a counter for counting the real-time clock; and determining whether or not the clock output of the oscillation circuit has stopped. An oscillation stop detection circuit for detecting power on, a power on detection circuit for detecting power on, a power supply voltage drop detection circuit for detecting a drop in power supply voltage, and a first circuit for holding an output of the oscillation stop detection circuit.
A real-time clock device, comprising: a storage unit for storing the output of the power-on detection circuit; and a third storage unit for storing the output of the power supply voltage drop detection circuit. . 2. The real-time clock device according to claim 1, wherein the contents of said first storage unit, said second storage unit, and said third storage unit are stored.
A means for determining the cause of the oscillation stop or the content of the subsequent processing based on the contents of the storage unit. 3. The real-time computer according to claim 1 or 2,
In the clock device, the oscillation of the oscillation circuit stops due to a decrease in the power supply voltage, and the power supply voltage level when the oscillation stop detection circuit detects the oscillation is detected, and the power supply voltage drop detector detects that the power supply voltage has dropped. A real-time clock device which is set to be lower than the power supply voltage level at which the power is supplied. 4. The real-time clock device according to claim 1, wherein the oscillation stop detection circuit, the power supply voltage drop detection circuit, and the power-on detection circuit are provided in a semiconductor chip. A real-time clock device. 5. The real-time clock device according to claim 4, further comprising: a non-volatile memory circuit provided in said semiconductor chip, wherein said oscillation stop detection circuit detects oscillation stop of said oscillation circuit. When the decrease in the power supply voltage is detected by the power supply voltage drop detection circuit, or when power-on is detected by the power-on detection circuit, the value of the counter is transferred to the memory circuit and held. Featured real-time clock device.