JP2001228200A - Manufacturing method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To surely test a bare chip stably in screening. SOLUTION: A contact pin 2b is formed on the bottom face of an open-top socket 2 mounted on a burn-in board 1 so as to be connected to an electrode of the burn-in board 1. An interposer 3c for mounting the bare chip CH is arranged in a lower base 3a of an IC socket 3. The interposer 3c is constructed of a multiplayered buildup base board laminated by repeatedly forming an insulation layer and a conductor wiring layer made of a buildup material. The bare chip CH is mounted while an upper base 3a, the bare chip CH and the lower base 3b are heated at a glass transition temperature approximately. In this way, the interposer 3c is softened, and an electrode D of the interposer 3c is connected to a bump BP of the bare chip CH while sinking downward, so that a contact characteristic can be maintained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing technique, and more particularly to a technique effective when applied to a bare chip screening technique.

[0002]

2. Description of the Related Art In a semiconductor device, a so-called KGD (Known Good), which is shipped as a product in a bare chip state and is packaged at a user site.
Die).

[0003] Prior to shipment, screening is performed on KGD in order to select non-defective products satisfying specification use and defective products. This screening is performed by attaching a KGD to an IC socket provided on a burn-in board and using a burn-in device.

According to the study by the present inventor, KG
The IC socket to which the D is mounted is provided with an interposer for converting the arrangement of the electrodes formed on the KGD and connecting to the external terminals of the IC socket.

Then, the external terminals provided on the IC socket and the electrodes provided on the burn-in board are connected,
Signals required for screening are transmitted. The interposer is, for example, a TAB (Tape Automate).
d Bonding) technology.

An example that describes in detail the test technique for this type of semiconductor device is described in
Published by Press Journal Co., Ltd., Shinji Matsushita (ed.), “Monthly Semiconductor World”
d Extra Number ULSI Test Technology ”P73 to P75, which describes a burn-in test technology in memory.

[0007]

However, the inventor of the present invention has found that the above-described KGD connection technology via the interposer has the following problems.

That is, since the screening is performed at a high temperature, there is a possibility that the KGD electrode and the interposer electrode may have poor contact due to a difference in thermal expansion coefficient between the KGD and the interposer.

Further, since the wiring layer of the interposer is formed only on the front and back surfaces of the interposer, no power plane or ground plane is formed, the electrical characteristics are deteriorated, and the noise resistance of the semiconductor device is reduced. Is reduced. In addition, KG pinned to another pin
In the case of D, there is also a problem that the wiring layout area of the interposer becomes large and the IC socket becomes large.

An object of the present invention is to provide a method of manufacturing a semiconductor device capable of stably and surely testing a bare chip in screening.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0012]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, in the method of manufacturing a semiconductor device according to the present invention, a step of preparing a bare chip on which connection electrodes are formed, a step of alternately laminating an elastic material and a wiring layer, and a step of mounting the bare chip A step of preparing a first socket having a wiring board, a step of preparing a test wiring board on which a second socket for mounting the first socket is mounted, and heating the bare chip and the first socket Meanwhile, the step of mounting the bare chip on the first socket, the step of mounting the first socket on which the bare chip is mounted on the second socket, and the step of screening the bare chip mounted on the inspection wiring board are performed. Have

Further, a method of manufacturing a semiconductor device according to the present invention
A step of preparing a bare chip on which connection electrodes are formed,
Build-up materials and wiring layers are alternately laminated and formed,
A step of preparing a first socket having a multilayer wiring board on which the bare chip is mounted; a step of preparing an inspection wiring board on which a second socket for mounting the first socket is mounted; Mounting a bare chip in the first socket while heating the first socket;
The method includes a step of mounting the first socket having the bare chip mounted on the second socket, and a step of screening the bare chip mounted on the inspection wiring board.

Further, in the method of manufacturing a semiconductor device according to the present invention, a step of preparing a bare chip on which connection electrodes are formed, a step of alternately laminating a build-up material and a wiring layer, and mounting the bare chip First with multi-layer wiring board
Preparing a socket for mounting the first socket, preparing a wiring board for inspection on which the second socket for mounting the first socket is mounted, and heating the bare chip and the first socket to about the glass transition temperature. Mounting the bare chip on the first socket, mounting the first socket on which the bare chip is mounted on the second socket, and screening the bare chip mounted on the inspection wiring board. Things.

Further, a method of manufacturing a semiconductor device according to the present invention
A step of preparing a bare chip on which connection electrodes are formed,
Build-up materials and wiring layers are alternately laminated and formed,
A step of preparing a first socket having a multilayer wiring board on which a bare chip is mounted; a step of preparing an inspection wiring board on which a second socket for mounting the first socket is mounted; Mounting a bare chip on a first socket while mounting the first socket on which a bare chip is mounted to the second socket while heating the first socket to a glass transition temperature; and a wiring board for inspection. And screening the bare chip mounted on the substrate at a high temperature.

Further, in the method of manufacturing a semiconductor device according to the present invention, a step of preparing a bare chip on which connection electrodes are formed, alternately laminating a build-up material and a wiring layer, and mounting the bare chip First with multi-layer wiring board
Preparing a socket for mounting the first socket, preparing a wiring board for inspection on which the second socket for mounting the first socket is mounted, and heating the bare chip and the first socket to about the glass transition temperature. Mounting the bare chip on the first socket, mounting the first socket on which the bare chip is mounted on the second socket, and screening the bare chip mounted on the inspection wiring board at a high temperature. Contacting the connection electrode of the bare chip with the electrode provided on the multilayer wiring board by elastic force.

As described above, even at the time of screening under high temperature such as burn-in, the bare chip and the multilayer wiring board can be reliably and stably connected, and screening can be performed efficiently.

[0019]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is an explanatory view of an open socket and an IC socket mounted in a burn-in mode according to an embodiment of the present invention, and FIGS. 2 to 7 are screens of a bare chip according to an embodiment of the present invention. Process explanatory diagram in
8 to 10 are explanatory views of the connection state between the bumps of the bare chip and the electrodes of the interposer according to one embodiment of the present invention.

In this embodiment, as shown in FIG. 1, a plurality of open top sockets (second sockets) 2 are mounted on a burn-in board (inspection wiring board) 1 used in a burn-in apparatus for performing screening. Have been. IC sockets (first sockets) 3 are attached to the open top sockets 2, respectively.

The open top socket 2 is, for example,
A square insertion hole 2a into which the IC socket 3 is inserted is formed in the center of the open top socket 2.
Is provided.

A plurality of contact pins 2b are formed on the bottom surface of the open top socket 2, and one end of each of the contact pins 2b is connected to the burn-in board 1.
Are connected by solder H or the like.

The IC socket 3 has an upper base 3a and a lower base 3b. In the center of the lower base 3a, a bare chip CH to be screened such as KGD is provided.
(Multi-layer wiring board) 3c on which is mounted.

Fixed clips 3d are provided on the periphery of two opposing sides of the lower base 3b. The fixed clip 3d is rotatably mounted by a shaft or the like provided on the lower base 3b, and a clip portion of the fixed clip 3d is fitted into a clip hole provided on an upper portion of the upper base 3a. Fix CH.

A vacuum hole VH is formed in the center of the upper base 3a, and the vacuum hole VH is evacuated to transfer the upper base 3a and the bare chip CH while fixing them. Screw holes are formed near the corners of the upper base 3a and the lower base 3b. By screwing the fixing bolt KB into these screw holes,
The IC socket 3a and the bare chip CH are more securely fixed.

The interposer 3c is made up of a multi-layered build-up board in which insulating layers made of a build-up material such as an epoxy resin material and conductor wiring layers are repeatedly formed so as to be alternately stacked.

An electrode D to which a bump (connection electrode) BP formed on the bare chip CH is connected is formed on the uppermost layer of the interposer 3c, and a bump B made of a spherical solder or the like is formed on the back surface. ing.

The electrode D and the bump B are connected to the interposer 3c.
Are connected via the wiring of the build-up layer. The bump B of the interposer 3c is connected to the other end of the contact pin 2b provided on the open top socket 2.

Next, the bare chip C in the present embodiment
The manufacturing process of H will be described with reference to FIGS. 1, 2 to 7, and the connection diagram between the bump BP and the electrode D in FIGS. 8 to 10.

First, as shown in FIG.
A bare chip CH for performing screening with P formed thereon is prepared. In addition, as shown in FIG. 3, an IC socket 3 having a bump B formed on the back surface of an interposer 3c fixed to a lower base 3b is prepared.

The mounting of the bare chip CH into the IC socket 3 is performed by, for example, a mounter used for a flip chip or the like. A heater or the like is provided in the head HD of the mounter and is heated.

The heated head HD picks up the bare chip CH mounted on the chip tray after adsorbing and fixing the upper base 3a by a vacuum chuck or the like.
The upper base 3a and the bare chip CH are transported to the heating stage ST. Pickup of bare chip CH,
When the head HD evacuates the vacuum holes VH of the upper base 3a, the bare chip CH is fixed to the upper base 3a.

As shown in FIG. 4, the lower base 3b is previously mounted on a heating stage ST heated by a heater or the like. The head HD and the heating stage ST are heated to about the glass transition temperature (Tg).

After the upper base 3a and the bare chip CH conveyed by the head HD to the heating stage ST are recognized for positioning, they are mounted on the lower base 3b as shown in FIG.

At the time of this mounting, the fixing clip 3d
Are automatically fitted into and fixed to the clip holes of the upper base 3a. In addition, the worker has the upper base 3a, the lower base 3
The fixing bolt KB is screwed into the screw hole b, and the bare chip CH is pressed down to more reliably connect the bump BP of the bare chip CH and the electrode of the interposer 3c.

Then, an IC on which the bare chip CH is mounted
As shown in FIG. 1, the socket 3 is mounted on the open top socket 2 mounted on the burn-in board 1 by an inserter or the like, and burn-in is performed.

Here, the principle of connection between the electrode D of the interposer 3c and the bump BP of the bare chip CH will be described.

Prior to connection, a protrusion is formed at the tip of the bump BP as shown in FIG. 8, and as shown in FIG. Crimp the interposer 3c
Of the interposer 3c is connected to the bump BP of the bare chip CH while sinking the electrode D of the interposer 3c.

Further, under the high temperature of the burn-in,
Since the build-up material of the interposer 3c has elasticity, the bare chip CH is deformed due to thermal expansion or the like, and even if the bump BP moves away from the electrode D, the electrode D of the interposer 3c and the bump BP of the bare chip CH have high contact. It is possible to maintain the nature.

At normal temperature, the elasticity of the build-up layer in the interposer 3c increases,
Since the deformed electrode D of c is restored, the interposer 3c
Can be used repeatedly and stably, so that the life of the IC socket 3 can be prolonged, and after the burn-in is completed, even in screening at room temperature, as shown in FIG. Can be maintained.

When the screening is completed, as shown in FIG. 6, the bare chip CH is taken out of the IC socket 3, and the tip of the bump BP of the bare chip CH is crushed into a regular bump shape, and the product is shipped.

The shipped bare chip CH is connected to a predetermined printed wiring board P or the like at a user site. For example, when the bare chip CH is flip-chip connected, as shown in FIG. 7A, the bump BP of the bare chip CH is connected to the anisotropic conductive film (ACF: Anisotr).
It is connected to an electrode PD formed on a printed wiring board P via an opi-conductive film (F). Further, instead of the anisotropic conductive film F, the gap between the bare chip CH and the printed wiring board P may be filled with an underfill which is an insulating resin.

Further, when the bare chip CH is bonded and connected, as shown in FIG. 7B, the bare chip CH is bonded to the printed wiring board P via an adhesive or the like. A bonding pad BPP is formed near the periphery of the CH.

The bumps of the bare chip CH and the bonding pads BPP of the printed wiring board P are connected by bonding wires W. These bare chips C
H, the bonding wires W, and the bonding pads BPP formed on the printed wiring board P are sealed with a resin J.

Thus, in the present embodiment, even at the time of screening under a high temperature such as burn-in,
By the elasticity of the build-up material, the bump BP of the bare chip CH and the electrode D of the interposer 3c can be reliably and stably connected.

Further, in the screening at normal temperature after the burn-in, the elasticity of the build-up material becomes stronger, so that high contact between the electrode D and the bump BP can be maintained more reliably.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

For example, in the above embodiment, a bump made of a spherical solder or the like is formed on the back surface of the interposer provided in the IC socket. However, instead of the bump, an electrode such as gold is used as the interposer electrode. (Land Grid A) provided with electrode pads of
(ray).

[0050]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows. (1) According to the present invention, in screening under high temperature such as burn-in, a bare chip and a multilayer wiring board can be reliably and stably connected. (2) In the present invention, the elasticity of the multilayer wiring board is increased at room temperature, and the multilayer wiring board is restored.
The life of the socket can be extended, and the bare chip and the multilayer wiring board can be more reliably connected even in screening at room temperature. (3) Further, in the present invention, the above (1) and (2)
Thereby, screening can be performed efficiently, and the manufacturing yield of semiconductor devices can be improved.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of an open socket and an IC socket mounted in a burn-in mode according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram of a screening step in a bare chip according to one embodiment of the present invention.

FIG. 3 is an explanatory diagram of a screening step in a bare chip following FIG. 2;

FIG. 4 is an explanatory view of the screening step in the bare chip following FIG. 3;

FIG. 5 is an explanatory diagram of the screening step in the bare chip following FIG. 4;

FIG. 6 is an explanatory diagram showing a bare chip at the time of product shipment according to one embodiment of the present invention.

FIG. 7A is an explanatory diagram when a bare chip is flip-chip connected, and FIG. 7B is an explanatory diagram when a bare chip is wire-bonded.

FIG. 8 is an explanatory diagram of a state before connection between bumps of a bare chip and electrodes of an interposer according to an embodiment of the present invention.

FIG. 9 is an explanatory diagram at the time of connection between bumps of a bare chip and electrodes of an interposer according to an embodiment of the present invention.

FIG. 10 is an explanatory diagram showing a connection state between a bump of a bare chip and an electrode of an interposer at the time of screening at room temperature according to an embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 1 burn-in board (wiring board for inspection) 2 open top socket (second socket) 2a insertion hole 2b contact pin 3 IC socket (first socket) 3a upper base 3b lower base 3c interposer (multilayer wiring board) 3d fixing clip H Solder CH Bare Chip VH Vacuum Hole KB Fixing Bolt BP Bump (Connection Electrode) D Electrode B Bump HD Head ST Heating Stage F Anisotropic Conductive Film P Printed Wiring Board PD Electrode BPP Bonding Pad W Bonding Wire J Resin

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Hideyuki Sasaki 145 Nakajima, Nanae-cho, Kameda-gun, Hokkaido Inside Hitachi Hokkai Semiconductor Co., Ltd. (72) Inventor Tsukio Funaki 145 Nakajima, Nanae-cho, Kameda-gun, Hokkaido Hitachi Hokkai Semiconductor Stock In-house (72) Inventor Hiroshi Kikuchi 3-16-6 Shinmachi, Ome-shi, Tokyo F-term in the Device Development Center, Hitachi, Ltd. (reference) 2G003 AA07 AC01 AD04 AG01 AG08 AG11 2G011 AA03 AA12 AC14 AE11 AF02 4M106 AA02 AD26 BA01 DD09 DH02

Claims (5)

[Claims] A step of preparing a bare chip on which connection electrodes are formed; and forming a first socket provided with a multilayer wiring board on which the elastic material and the wiring layer are alternately laminated to form the bare chip. A step of preparing; a step of preparing a wiring board for inspection on which a second socket for mounting the first socket is mounted; and a step of heating the bare chip and the first socket while heating the first socket. Mounting the bare chip on the second socket, mounting the first socket on which the bare chip is mounted on the second socket, and screening the bare chip mounted on the inspection wiring board. A method for manufacturing a semiconductor device, comprising: A step of preparing a bare chip on which connection electrodes are formed; and a step of alternately laminating a build-up material and a wiring layer to form a bare chip.
A step of preparing a first socket including a multilayer wiring board on which the bare chip is mounted; a step of preparing an inspection wiring board on which a second socket for mounting the first socket is mounted; Mounting the bare chip on the first socket while heating the first socket; mounting the first socket on which the bare chip is mounted on the second socket; Screening the bare chip mounted on the wiring board for use in a semiconductor device. 3. A step of preparing a bare chip on which connection electrodes are formed, and alternately laminating a build-up material and a wiring layer.
A step of preparing a first socket having a multilayer wiring board on which the bare chip is mounted; a step of preparing a wiring board for inspection on which a second socket for mounting the first socket is mounted; Mounting the bare chip on the first socket while heating the first socket to about the glass transition temperature; and mounting the first socket on which the bare chip is mounted on the second socket. A method of manufacturing a semiconductor device, comprising: a step of screening the bare chip mounted on the inspection wiring board. 4. A step of preparing a bare chip on which connection electrodes are formed, and alternately laminating a build-up material and a wiring layer.
A step of preparing a first socket having a multilayer wiring board on which the bare chip is mounted; a step of preparing a wiring board for inspection on which a second socket for mounting the first socket is mounted; Mounting the bare chip on the first socket while heating the first socket to about the glass transition temperature; and mounting the first socket on which the bare chip is mounted on the second socket. And a step of screening the bare chip mounted on the inspection wiring board at a high temperature. 5. A step of preparing a bare chip on which connection electrodes are formed, and alternately laminating and forming a build-up material and a wiring layer,
A step of preparing a first socket having a multilayer wiring board on which the bare chip is mounted; a step of preparing a wiring board for inspection on which a second socket for mounting the first socket is mounted; Mounting the bare chip on the first socket while heating the first socket to about the glass transition temperature; and mounting the first socket on which the bare chip is mounted on the second socket. And a step of contacting the bare chip mounting electrode and the electrode provided on the multilayer wiring board by elastic force while screening the bare chip mounted on the inspection wiring board at a high temperature. A method for manufacturing a semiconductor device.