JP2001228189A - Noise detection circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a noise detection circuit having no upper limit of a detectable noise frequency in principal. SOLUTION: In the detection of the existence/absence of a noise possibly included in an input signal e1, an inspection signal changing periodically according to a predetermined pattern is generated on the time base. This inspection signal and the input signal are combined, and the pattern included in the combined signal is checked for detecting the existence/absence of the noise.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a noise detection circuit.

[0002]

2. Description of the Related Art In EMC, it is required that electric noise in a power supply line or the like is equal to or less than a predetermined value. In such a case, a noise detection circuit is required which calculates a threshold value of the level of the electrical noise, makes the level below a predetermined level normal, and sets the level above the predetermined level abnormal.

As this kind of noise detection circuit, for example,
Japanese Patent Application Laid-Open No. 6-245433 discloses a no-change confirmation circuit used in a device for detecting the presence or absence of motor rotation. Another method is disclosed in Japanese Patent Application Laid-Open No. 9-152356.
This publication discloses a circuit for detecting the presence or absence of low-frequency fluctuation while eliminating the influence of high-frequency noise. In this known document, while extending the monitoring frequency range to lower frequencies,
A configuration capable of eliminating the influence of high frequency noise generated by vibration or the like is shown.

However, in the case of the technique described in Japanese Patent Application Laid-Open No. Hei 6-245433, noise having a frequency higher than the frequency of a high-frequency signal superimposed on an input signal cannot be detected. The technology described in Japanese Patent Application Laid-Open No. 9-152356 is originally configured to eliminate high-frequency input changes, and therefore has an upper limit on the frequency of detectable noise. Japanese Patent Application Laid-Open No. 6-245433 discloses that noise of a frequency higher than the frequency of a high-frequency signal superimposed on an input signal cannot be detected.
This is the same as the conventional example described in the gazette. Next, this point will be specifically described with reference to FIGS.

FIG. 32 is a diagram showing a configuration example of a conventional noise detection circuit, and FIG. 33 is a time chart for explaining the operation of the conventional noise detection circuit shown in FIG. As shown in FIG. 32, the conventional noise detection circuit includes a test signal generation circuit 5
10 and a signal processing determination circuit 520. The inspection signal generation circuit 510 includes an inspection signal generation source 511, and the inspection signal Sg (FIG. 33) generated by the inspection signal generation source 511.
(See FIG. 33 (b)) and the input signal e1 (see FIG. 33 (a)), and outputs the combined signal V1 (see FIG. 33 (c)). The inspection signal generation circuit 510 further includes a resistor 51
2, 513 and the like. Reference numeral Vcc is a power supply voltage.

The signal processing determination circuit 520 has upper and lower thresholds for the input composite signal V1.
At least when the synthesized signal V1 is within the upper and lower windows,
A signal Z having a logical value 1 is generated. A signal Z with a logical value of 1 means no noise.

More specifically, the signal processing determination circuit 520
It includes a signal conversion circuit 600 and a determination circuit 700. The signal conversion circuit 600 amplifies and rectifies the synthesized signal V1 and converts it into a DC signal V2. The determination circuit 700
When the state in which the DC signal V2 supplied from the signal conversion circuit 600 is equal to or higher than the predetermined threshold value Vt continues for a predetermined time Ton, the signal Z having the logical value 1 is generated.

[0008] The determination circuit 700 regards the time when a logical value 0 occurs in the input signal V2 as noise in the input signal e1. In the drawing, the determination circuit 700 includes a window comparator 701 and an on-delay circuit 702,
The level of the input signal V2 is determined by the window comparator 701, and the signal Sc is generated. The on-delay circuit 702 is a window comparator 701
The signal Z is generated from the signal Sc supplied from the.

As a means for generating a logical value 0 in the input signal V2, the signal conversion circuit 600
02, which utilizes the phenomenon that the output Sa (see FIG. 33D) of the AC amplifier circuit 602 is saturated by noise to become a DC voltage. When the output Sa becomes a DC voltage due to the saturation operation of the AC amplifier circuit 602 (see FIG. 33D), the level of the signal V2 output from the rectifier circuit 603 connected to the subsequent stage is higher than the threshold value Vt. Is also low (see FIG. 33 (e)).

The signal conversion circuit 600 has windows WnH and WnL with respect to the input composite signal V1 (FIG. 33).
(C)). Window WnL is given by two lower thresholds, and window WnH is given by two upper thresholds. These windows WnH and WnL have the following relationship with the synthesized signal V1.

First, if the amplitude of the test signal Sg is too small and the amplitude of the synthesized signal V1 obtained by synthesizing the test signal Sg and the input signal e1 is too small, the level of the amplified rectified output signal V2 is obtained. Becomes smaller than the lower threshold value that determines the window WnL, the signal Z becomes a logical value 0, and the noise detection operation cannot be performed. Therefore, the amplitude of the inspection signal Sg (the amplitude of the composite signal) must exceed the lower limit window WnL.

Further, the amplitude of the synthesized signal V1 obtained by synthesizing the inspection signal Sg and the input signal e1 has an upper limit window WnH.
Must be within. The upper limit window WnH corresponds to the amplitude limit of the input signal at which the AC amplifier circuit 602 can perform an amplification operation without being saturated.

As described above, in the conventional noise detection circuit, when the state in which the amplitude of the test signal exceeds the lower limit window WnL and exists within the upper limit window WnH continues for a predetermined time Ton or more, the "input The signal e1 has no noise "and the amplitude of the test signal is lower than the lower limit window WnL and upper limit window WnH.
Is immediately determined as "the input signal e1 has noise". In other words, at least the input signal e1
When the composite signal V1 of the test signal Sg and the test signal Sg is within the range between the lower threshold value and the upper threshold value, a signal Z having a logical value of 1 indicating no noise is output. A signal Z having a logical value of 0 is output.

Next, a problem of the conventional noise detection circuit shown in FIG. 32 will be described with reference to FIG. First, when noise (see FIG. 34 (a)) rides on the input signal e1, the input signal e1 and the inspection signal Sg (see FIG. 34 (b))
The timing at which the amplitude of the synthesized signal V1 (see FIG. 34 (c)) obtained by combining with the window WnL by the lower threshold and the window WnH by the upper threshold is determined, and the inside of the window WnL and the window WnH. Is repeated according to the noise frequency (see FIG. 34 (c)).

The signal V1 is amplified by the AC amplifier circuit 602, and a DC voltage due to saturation is output from the AC amplifier circuit 602 at a period according to the noise frequency (FIG. 34).
(D)).

In a noise detection circuit of this type using the test signal Sg, it is common that the test signal Sg has a period of one cycle or a slightly longer holding time.
If the frequency has a cycle longer than one cycle of g, the time during which the synthesized signal V1 is outside the windows WnL and WnH is longer than the holding time. The time when the signal V1 is outside the windows WnL and WnH occurs, and the presence of noise can be detected. In other words, if the noise frequency is low, the time during which the amplitude of the composite signal V1 is outside the windows WnL and WnH becomes sufficiently long, so that the presence of noise can be detected. The holding time is obtained by the rectifier circuit 603.

However, the noise frequency becomes equal to or higher than the test signal Sg, and the time during which the synthesized signal V1 is outside the windows WnL and WnH becomes shorter than the holding time (FIG. 34 (c)). )) And the composite signal V
1 cannot detect the time outside window WnL and window WnH.

As a result, the signal V2 output from the signal conversion circuit 600 always has the logical value 1 (see FIG. 3).
4 (e)), the signal Sc and the signal Z also have the logical value 1 meaning no noise (FIG. 34 (f),
(G)). This means that the presence of noise cannot be detected despite the presence of noise.

[0019]

SUMMARY OF THE INVENTION An object of the present invention is to provide a noise detection circuit which has no upper limit in principle for a noise frequency which can be detected.

Another object of the present invention is to easily realize a fail-safe configuration that does not erroneously report the absence of noise when a circuit failure occurs, even though the noise is above a predetermined value. It is to provide a noise detection circuit.

[0021]

In order to solve the above-mentioned problems, a noise detection circuit according to the present invention detects a presence or absence of a noise that may be included in an input signal, and determines a predetermined value on a time axis. A test signal that changes periodically is generated in the pattern. The test signal and the input signal are combined, the pattern included in the combined signal is confirmed, and the presence or absence of the noise is detected.

If the input signal to be tested does not contain more than a predetermined amount of noise, the synthesized signal has the characteristics of a test signal that periodically changes in a predetermined pattern on the time axis. . Therefore, by confirming that a predetermined pattern that is a characteristic of the inspection signal exists, it is possible to generate a noise detection signal indicating that the input signal that is the inspection target signal does not include a predetermined amount or more of noise.

On the other hand, when the input signal serving as the signal to be inspected contains noise equal to or greater than a predetermined value, the synthesized signal has an inspection signal that periodically changes in a predetermined pattern on the time axis. Loses signal characteristics. As a result, a noise detection signal is generated that includes noise of a predetermined level or more.

As described above, the presence / absence of noise is detected by using the characteristic of the test signal that changes periodically in a predetermined pattern on the time axis. There is no upper limit.

Further, as is supported by the embodiment, a fail-safe configuration that does not erroneously report the absence of noise even when the input noise is equal to or higher than a predetermined value at the time of a circuit failure can be easily realized. realizable. In the present invention, the input signal is basically a DC voltage signal.

The noise detection circuit according to the present invention generally includes a test signal generation circuit and a signal processing determination circuit.
The test signal generation circuit generates a test signal that periodically changes in a predetermined pattern on a time axis. The signal processing determination circuit receives a synthesized signal obtained by synthesizing the test signal and the input signal, checks the pattern included in the synthesized signal, and detects the presence or absence of the noise.

The present invention further discloses two specific modes regarding the test signal pattern in the test signal generation circuit and its confirmation in the above-described circuit configuration.

<Noise Detection Circuit According to First Aspect>
In the aspect, the test signal generating circuit generates a test signal that alternately repeats two periods having different voltage levels. The signal processing determination circuit detects the presence or absence of noise from a combined signal obtained by combining the test signal and the input signal.

Since the test signal has a pattern in which two periods having different voltage levels are alternately repeated, one of the periods, for example, a high level period, is a test for checking that there is an input signal which is a signal to be tested. Time period,
The low level period can be used as a “noise confirmation period” for confirming the presence or absence of noise.

This test signal is combined with an input signal to be a test target signal. When the input signal serving as the signal to be inspected does not include noise equal to or greater than a predetermined value, the composite signal is characterized in that the signal level in the inspection period is higher than the signal level in the noise confirmation period. That is, the synthesized signal has a pattern in which a high-level period and a low-level period are alternately repeated. By confirming the repetition pattern, it is possible to generate a noise detection signal indicating that the input signal, which is the inspection target signal, does not include a predetermined amount or more of noise.

On the other hand, when the input signal serving as the signal to be inspected contains noise of a predetermined level or more, the level of the synthesized signal increases during the noise confirmation period, and the test is performed when the noise is not included. The difference between the level of the period becomes smaller. That is, the synthesized signal loses the feature of the pattern in which the high-level period and the low-level period are alternately repeated. As a result, a noise detection signal is generated that includes noise of a predetermined level or more.

As described above, the noise detection circuit according to the first aspect detects the presence or absence of noise by using the characteristic of a pattern in which a high level period and a low level period are alternately repeated, and thus can be detected. No upper limit is imposed on the noise frequency in principle.

Further, as is supported by the embodiment, a fail-safe configuration that does not erroneously report the absence of noise even when the input noise is equal to or more than a predetermined value at the time of a circuit failure can be easily realized. realizable.

The test signal may be a frequency signal having a shorter period than the high-level period and the low-level period,
In each of the high-level period and the low-level period, a DC signal that maintains a predetermined level given in advance may be used.

<Noise Detection Circuit According to Second Aspect>
In the aspect, the test signal generation circuit generates a test signal that alternately repeats two periods having different frequencies. The signal processing determination circuit generates the noise detection signal from a combined signal obtained by combining the test signal and the input signal.

The test signal is a pattern signal that alternately repeats two periods having different frequencies. Therefore, in one period, for example, a high frequency period, a test is performed to check that there is an input signal which is a signal to be tested. Time period,
The low frequency period can be used as a “noise confirmation period” for confirming the presence or absence of noise.

This test signal is combined with an input signal to be a test target signal. When the input signal serving as the inspection target signal does not include noise equal to or greater than a predetermined value, the synthesized signal is characterized in that the frequency during the inspection period is higher than the frequency during the noise confirmation period. That is, the synthesized signal has a pattern in which the high frequency period and the low frequency period are alternately repeated. By confirming the repetition pattern, it is possible to generate a noise detection signal indicating that the input signal, which is the inspection target signal, does not include a predetermined amount or more of noise.

On the other hand, when the input signal serving as the signal to be inspected contains noise of a predetermined level or more, the synthesized signal has a high frequency in the noise confirmation period and a frequency between the frequency in the inspection period. The difference becomes smaller. That is, the synthesized signal loses the feature of the pattern in which the high frequency period and the low frequency period are alternately repeated. As a result, a noise detection signal is generated that includes noise of a predetermined level or more.

Specifically, a signal conversion circuit is provided in the noise detection circuit, and the frequency-gain characteristic of the signal conversion circuit is used. That is, at a frequency equal to or lower than the predetermined frequency, by utilizing the characteristic that the conversion constant is reduced, the amplitude of the input composite signal is converted into a DC signal having a level multiplied by the conversion constant and output. More specifically, during a test period in which a high-frequency component is input, a high-level amplified detection output is generated by using the saturation characteristics of the signal conversion circuit. A low-level amplification detection output corresponding to the amplification factor of the conversion circuit is generated.

When the input signal to be inspected does not contain more than a predetermined amount of noise, the output signal of the signal conversion circuit is characterized in that the signal level during the inspection period is higher than the signal level during the noise confirmation period. Attached. That is, the output signal of the signal conversion circuit is a pattern signal that alternately repeats a high-level period and a low-level period. By confirming the repetition pattern, it is possible to generate a noise detection signal indicating that the input signal, which is the inspection target signal, does not include a predetermined amount or more of noise.

On the other hand, when the input signal serving as the inspection target signal contains noise of a predetermined level or more, the signal conversion circuit is saturated even during the noise confirmation period in which the low frequency component is input, and the high level Amplified detection output is generated. That is,
The amplified detection output loses the feature of a pattern in which a high level period and a low level period are alternately repeated. As a result, a noise detection signal is generated that includes noise of a predetermined level or more.

As described above, the noise detection circuit according to the second embodiment detects the presence or absence of noise by using the characteristic of a pattern in which a high frequency period and a low frequency period are alternately repeated. In principle, there is no upper limit on the frequency.

Further, as is supported by the embodiment, a fail-safe configuration that does not erroneously report the absence of noise even when the input noise is equal to or more than a predetermined value at the time of a circuit failure can be easily realized. realizable.

In the present invention, when referring to a level, it is a voltage level. The present invention further discloses a specific circuit configuration and a fail-safe circuit configuration.

[0045]

DESCRIPTION OF THE PREFERRED EMBODIMENTS <Noise Detection Circuit According to First Aspect> FIG. 1 is a block diagram showing a basic configuration of a noise detection circuit according to the present invention, and FIG. 2 is a time chart for explaining the operation of FIG. is there. The noise detection circuit shown in FIG. 1 includes a test signal generation circuit 100 and a signal processing determination circuit 120, and detects the presence or absence of noise included in the input signal e1.

The input signal e1 is supplied to the test signal generation circuit 100 via the path 110. The input signal e1 is
As shown in FIG. 2 (b), the signal becomes a signal containing noise of a predetermined value or more from time t11.

The test signal generation circuit 100 receives the input signal e1
And an inspection signal (referred to as S1), and outputs the signal as a signal S2. In the embodiment, as shown in FIG. 2C, the inspection signal S1 is alternately provided for a predetermined period T on the time axis.
C1 to TC3 and two types of voltage signals SH and SL that continue between TN1 and TN2. The periods TC1 to TC3 are an inspection period, and the periods TN1 and TN2 are noise check periods TN (TN
1, TN2). The inspection signal S1 is output during the inspection period TC.
In each of (TC1 to TC3), a DC voltage signal that maintains a constant level or a frequency signal that changes at a predetermined frequency may be used. In FIG. 2, three inspection periods TC (TC1 to TC3) are taken into account due to space limitations.
And two noise confirmation periods TN (TN1, TN2), but the inspection period and the noise confirmation period TN (T
It goes without saying that N1 and TN2) are alternately repeated during the time required for noise detection. Inspection period TC
The level of the inspection signal S1 at (TC1 to TC3) is S
H, assuming that the level of the inspection signal S1 in the noise confirmation period TN (TN1, TN2) is SL, the inspection period TC (T
The level SH in C1 to TC3) is higher than the level SL of the test signal S1 in the noise check period TN (TN1, TN2). The test signal generation circuit 100 is the same as that shown in FIG.
The input signal e1 shown in (b) is combined with the inspection signals S1 of the levels SH and SL shown in FIG. 2C to generate a signal S2 shown in FIG. 2D.

The signal processing determination circuit 120 determines the level SH,
A signal S2 obtained by synthesizing the SL inspection signal S1 and the input signal e1 is input, detects the presence or absence of noise from the input signal S2, and outputs a noise detection signal Z.

As described above, since the test signal S1 alternately repeats the test periods TC (TC1 to TC3) and the noise check periods TN (TN1, TN2) having different voltage levels, the test period TC having the high level SH is performed. (TC1 to TC
In 3), it is checked that there is an input signal e1, which is a signal to be checked, and a low-level SL noise check period TN (TN
1, TN2), the presence or absence of noise can be confirmed.

If the input signal e1 to be tested does not contain noise of a predetermined level or more, the level S
The signal S2 obtained by synthesizing the H and SL test signals S1 and the input signal e1 has a signal level in a test period TC (TC1 to TC3) and a noise check period TN (TN1, TN2).
Is characterized by being higher than the signal level of That is, the signal S2 has a high level S as shown in FIG.
H inspection period TC (TC1 to TC3) and low level SL
And the noise confirmation period TN (TN1, TN2) is alternately repeated. The signal processing determination circuit 120 converts the repetition signal into an input signal e1, which is a signal to be inspected,
It generates and outputs a noise detection signal Z having a logical value 1 indicating that noise of a predetermined level or more is not included (see FIG. 2D).

On the other hand, if the input signal e1 serving as the signal to be inspected contains noise of a predetermined level or more at time t11 (see FIG. 2A), the signal S2 has the noise confirmation period TN2 having a level of: It rises as shown by the dotted line in FIG. That is, the signal S2 loses its characteristic as a signal in which the high-level period and the low-level period are alternately repeated. As a result, as shown in FIG. 2D, a noise detection signal Z having a logical value of 0 that includes noise of a predetermined level or more is generated.

The test signals S1 of the levels SH and SL generated by the test signal generation circuit 100 correspond to the test period TC (TC1
To TC3) and the noise confirmation period TN (TN1, TN2)
A frequency signal having a shorter cycle may be used, or the inspection period TC (TC1 to TC3) and the noise confirmation period TN
In each of (TN1, TN2), a DC signal that maintains a predetermined level given in advance may be used.

As a noise detection method, it is a structure for confirming that the signal level is low at least every predetermined period, and the following three methods are possible. (A) It is determined that noise is present when the signal S2 does not go low during the noise confirmation period TN (TN1, TN2), at which the signal S2 should go low. This is referred to as a first determination method. (B) Focusing on the fact that the signal S2 is a signal that alternates between a high-level period and a low-level period, there is no noise when both periods are alternately repeated, and there is noise when there is no repetition of both periods. judge. This is referred to as a second determination method. (C) Paying attention to the fact that the signal S2 is a signal which alternately repeats a high level period and a low level period, obtains a match with the reference signal, and when there is a match, there is no noise, and when there is no match, there is noise. judge. This is referred to as a third determination method. These methods (a) to (c) will be described sequentially and individually.

FIG. 3 is a specific circuit diagram of the noise detection circuit according to the present invention, and FIG. 4 is a time chart for explaining the operation of the noise detection circuit shown in FIG. In the illustrated noise detection circuit, the inspection signal generation circuit 100 includes an inspection period TC (TC1 to TC3) and a noise confirmation period TN (TN
1, TN2) is generated.

Specifically, the test signal generation circuit 100
The first AC signal source Osc1 and the second AC signal source Osc
2, including a switch SW and resistors R12 to R13. Further, the impedance is set to R11 when the input signal e1 side is viewed from the position of the signal S2. The capacitor C11 is shown to emphasize that point, and is not essential for operation.

The test signal Sd is supplied to the second AC signal source Osc
2 is an amplitude modulation signal of the AC signal ω22 outputted from The amplitude modulation is executed by a switch SW that is turned on / off by an AC signal ω21 supplied from the first AC signal source Osc1. The cycle of the AC signal ω21 is longer than the cycle of the AC signal ω22. One end of the switch SW is connected to one end of a resistor R13, and the other end of the resistor R13 is connected to a connection point a1 connecting one end of the resistors R12 and R14. The other end of the resistor R12 is a signal processing determination circuit 1
20 and the other end of the resistor R14 is connected to the second AC signal source O
It is led to the output terminal of sc2.

When the switch SW is turned on (see FIG. 4A), the level S of the AC signal ω22 viewed at the connection point a1
d is approximately given by Sd = Vω × R13 / (R13 + R14) where Vω is the level of the AC signal ω22.

The inspection signal S1 is at the low level SL (see FIG. 4B) when the switch SW is ON, and the low level SL is SL = {Vω × R13 / (R13 + R14)} × {R11 /
(R11 + R12)}. However, in operation, R13 = 0 may be set.

On the other hand, the switch SW is turned off (FIG. 4 (a)
4), the signal S1 becomes high level SH (FIG. 4).
(See (b)). The high level SH is approximately given by SH = Vω × R11 / (R11 + R12 + R14).

As described above, ON / OFF of the switch SW is performed.
Each time, that is, in synchronization with the AC signal ω21 from the first AC signal source Osc1, two different levels SL and SH occur in the test signal S1. A test signal S1 having two levels SH and SL is superimposed on an input signal e1 to generate a signal S2.
Is generated, and the signal S2 is input to the signal processing determination circuit 120. The noise detection operation in the signal processing determination circuit 120 is as described above.

FIG. 5 is a diagram showing another circuit configuration of the test signal generation circuit 100 in the noise detection circuit according to the present invention. In the figure, the same components as those shown in FIG. 4 are denoted by the same reference numerals.

The switch SW is connected to the first AC signal source Osc
1 drives ON / OFF. The switch SW is connected to both ends of the resistor R22. One end of the resistor R22 is guided to the input side of the signal processing determination circuit 120, and the other end is connected to one end of the resistor R23. The resistor R23 is the second
Of the AC signal source Osc2. Also,
The impedance of the input signal e1 from the position of the signal S2 is R21. The capacitor C21 is provided to emphasize that point, and is not essential for operation.

In the circuit shown in FIG.
Is OFF, the inspection signal S1 becomes the low level SL.
The low level SL is a level Vω of the AC signal ω22,
Approximately, SL = Vω × R21 / (R22 + R23 + R21)

Next, when the switch SW is ON, the inspection signal S1 goes to the high level SH. The high level SH is as follows: SH = Vω × R21 / (R23 + R21) Therefore, two different levels SH, S
An L inspection signal S1 can be obtained. The inspection signal S1 is superimposed on the input signal e1 to generate the signal S2, and the signal S2
2 is input to the signal processing determination circuit 120. The noise detection operation in the signal processing determination circuit 120 is as described above.

In the circuit configuration of FIG. 5, assuming that the input impedance of the signal processing determination circuit 120 is sufficiently large, if a break occurs in the input path 110 of the input signal e1, a low level SL and a high level Level SH
In both, the level rises. If the noise level en1 increases, the low level SL and the high level SH of the signal S2
Rises further. Therefore, when the configuration for detecting the presence or absence of noise from the level of the signal S2 is adopted, the input path 1
Since the noise detection signal Z has a logical value of 0 corresponding to the disconnection of 10, no special circuit configuration for detecting a disconnection failure of the input path 110 is required.

FIG. 6 is a diagram showing still another circuit configuration of the test signal generation circuit 100 in the noise detection circuit according to the present invention. In the figures, the same components as those shown in FIGS. 4 and 5 are denoted by the same reference numerals.
The switch SW is driven ON / OFF by an AC signal ω21 supplied from the first AC signal source Osc1. A resistor R32 is connected between the output terminal of the second AC signal source Osc2 and the signal processing determination circuit 120. Further, it is assumed that the impedance is R31 when the input signal e1 is viewed from the position of the signal S2. The capacitor C31 is
It is written to emphasize that point and is not essential for operation.

The power supply voltage of the second AC signal source Osc2 is switched between the voltage V1 and the voltage V2 depending on the ON position of the switch SW, and as a result, the amplitude V of the AC signal voltage ω22 is changed.
ω changes. Here, a description will be given assuming that voltage V1> voltage V2.

When the switch SW is ON on the voltage V1 side, a high level SH is obtained as the inspection signal S1. The high level SH is approximately SH = Vω1 × R31 / (R31 + R32), where Vω1 is the level of the AC signal ω22 when ON at the voltage V1 side.

On the other hand, the switch SW is turned on on the voltage V2 side.
During this operation, a low level SL is obtained as the inspection signal S1. The low level SL is approximately SL = Vω2 × R31 / (R31 + R32), where the level of the AC signal ω22 when turned on on the voltage V2 side is Vω2. Since V1> V2, Vω1> Vω2,
As the inspection signal S1, two different levels SH and SL can be obtained. The inspection signal S1 is superimposed on the input signal e1 to generate a signal S2, and the signal S2 is input to the signal processing determination circuit 120. The noise detection operation in the signal processing determination circuit 120 is as described above.

In the circuit configuration shown in FIG. 6, when a break occurs in the input path 110 of the input signal e1, SH = Vω1 SL = Vω2 in the signal S2. However, it is assumed that the input impedance of the signal processing determination circuit 120 is sufficiently large. Here, it is configured to detect the presence or absence of noise from the level of the signal S2. For example, if Vω2 ≧ Vω1 × R31 / (R31 + R32) is set, the disconnection of the input path 110 is performed similarly to the rise of the noise level en1. Correspondingly, since the noise detection signal Z has a logical value of 0, no special circuit configuration for detecting a disconnection failure of the input path 110 is required. The same applies to FIG.

FIG. 7 is a diagram showing a specific configuration of the signal processing determination circuit 120 of the noise detection circuit shown in FIG. The illustrated signal processing determination circuit 120 includes a signal conversion circuit 200.
And a determination circuit 300.

The signal conversion circuit 200 includes the capacitor 20
1, an AC amplification circuit 202 and a detection circuit 203 are included. The signal S2 is supplied to the AC amplification circuit 20 via the capacitor 201.
2 and amplified. The amplified signal S3 is detected by the detection circuit 2
03 and is detected. The signal S4 output from the detection circuit 203 is supplied to the determination circuit 300, and the presence or absence of noise is determined. The signal S5 output from the determination circuit 300 becomes a high-level logical value 1 signal when there is no noise, and becomes a low-level logical value 0 signal when there is noise.

FIG. 8 shows a specific circuit example of the AC amplifier circuit 202 used in the signal conversion circuit 200. The illustrated AC amplifier circuit 202 includes transistors Q11 and Q11.
12. Resistors R41, R42, R43, R for determining the degree of amplification
44 and a known amplifier circuit including a feedback resistor R45 and the like.

FIG. 9 shows a specific circuit example of the AC amplifier circuit 202 used in the signal conversion circuit 200. The illustrated AC amplifier circuit 202 includes a well-known operational amplifier OP5.
This is a feedback amplifier circuit using The signal S2 is supplied to the input terminal (-) of the operational amplifier OP5 via the coupling capacitor 201 and the resistor R51, and the reference power supply E5 is supplied to the input terminal (+). A feedback resistor R52 is connected between the output terminal of the operational amplifier OP5 and the input terminal (-).

FIGS. 8 and 9 show only specific examples of amplifier circuits that can be employed in the noise detection circuit according to the present invention. In addition, it goes without saying that various circuit configurations can be adopted.

Next, a method of detecting noise in the signal processing determination circuit 120 will be described. As described above, the noise detection method includes the three methods of the level detection method, the alternation detection method, and the coincidence detection method.

<Noise Detection Circuit Using First Judgment Method>
FIG. 10 is a block diagram of a noise detection circuit employing the first determination method.
FIG . 11 is a time chart for explaining the operation of the noise detection circuit shown in FIG. 10, the same components as those shown in FIG. 1 are denoted by the same reference numerals. The test signal generation circuit 100 can be configured by any of the circuit configurations illustrated in FIGS. The signal conversion circuit 200 is represented by the block diagram shown in FIG. 7, and can be configured by any of the circuit configurations specifically shown in FIGS. The determination circuit 300 is configured as a low-level confirmation circuit.

The test signal generation circuit 100 receives the input signal e1
, And outputs the signal as a signal S2.
As shown in (a), the test signals S1 of the levels SH and SL
To generate a signal ω1 synchronized with.

The signal conversion circuit 200 outputs the input signal e1
A signal S2 obtained by synthesizing a test signal S1 of two kinds of levels SH and SL alternately generated on the time axis is received, and a signal S2 including the two kinds of signals SH and SL is converted into different levels, respectively, and a signal S4 Output as

Specifically, in the inspection periods TC1 and TC2, since the level of the signal S2 is high, the signal S4 having a logical value of 1
Is generated, and a noise confirmation period TN next to the inspection period TC1 is generated.
Since the level of the signal S2 is low at 1, the signal S2 having the logical value 0 is low.
4 is generated.

After time t11 when the input signal e1 contains noise of a predetermined value or more (see FIG. 11B), the inspection period T
The level of the signal S2 becomes high not only in C3 but also in the noise check period TN2. That is, if there is no noise, a noise confirmation period TN in which a signal S4 having a logical value 0 should be generated.
1, a signal S4 having a logical value of 1 is generated. Such a circuit operation can be realized by setting a threshold value in the signal conversion circuit 200 specifically shown in FIGS. 8 and 9, or can be realized by utilizing an amplifying function.

The decision circuit 300 confirms that the signal S4 has the logical value 0 during the noise confirmation period TN (TN1, TN2). When the logic is established, a signal S5 having a logical value of 1 is output, and when the logic is not established, a signal S5 having a logical value of 0 is output.

In the case of the example shown in FIG. 11, the signal S4 has a logical value of 0 during the noise checking period TN1, so that a signal S5 having a logical value of 1 meaning no noise is output (see FIG. 11F).
Is done. On the other hand, in the noise checking period TN2, the signal S4 that should have the logical value 0 is the logical value 1 (see FIG. 11E), so that the signal S5 having the logical value 0 indicating the presence of noise is output ( FIG. 11F). Therefore, the presence or absence of noise can be determined from the signal S5 output from the determination circuit 300.

In the embodiment shown in FIG. 10, an AND element WC1 is provided at the subsequent stage of the decision circuit 300. AND element W
The signal S5 is supplied from the determination circuit 300 to the input terminal B of C1, and the signal S2 is supplied to the input terminal A via the path 130.
Is entered. The AND element WC1 is composed of the signal S2 and the signal S2.
A signal Z, which is a logical product of the signal Z and 5, is output. In the embodiment, this signal Z is the final noise detection signal.

As described above, when the input signal e1 contains noise of a predetermined level or more, the signal S5 becomes a logical value 0 (see FIG. 11F). In the embodiment, the signal S5 is also output when a disconnection fault occurs in the path 110.
The logical value becomes 0. However, the signal S5 due to the disconnection of the path 110
Is not logical 0, the route 11
A disconnection of 0 must be detected separately.

Therefore, in FIG. 10, the logical product element WC
1 is provided to monitor the level of the signal S2. Signal S
AND element WC1 that receives 2 has a lower threshold for the input, and if signal S2 is greater than or equal to the lower threshold,
When the signal S5 has the logical value 1, the signal Z having the logical value 1 is generated. The test signal generation circuit 100 is configured such that the level of the signal S2 when the path 110 is normal substantially depends on the level of the input signal e1, as shown in FIG. At this time, the lower threshold value of the logical product element WC1 is set so that the signal Z has the logical value 1. Here, if a disconnection fault occurs in the path 110, the input signal e1 does not appear in the signal S2, and the level of the signal S2 is determined by the logical product element WC.
When the signal Z becomes equal to or less than the lower limit threshold value of 1, the signal Z becomes a logical value 0 irrespective of the signal S5.

However, in this embodiment, the inspection signal generation circuit 1
00 is configured so that the signal S4 is always at a high level even when the path 110 is disconnected, so that it is not necessary to monitor the signal S2 with the logical product element WC1. Therefore, the signal S5 can be handled as the signal Z without the AND element WC1. In that sense, the path 130 is shown by a dotted line in FIG.

FIG. 12 is an electric circuit diagram showing a specific configuration example of the decision circuit 300, and FIG. 13 is a circuit diagram showing the decision circuit 30 shown in FIG.
6 is a time chart for explaining an operation of a zero. The determination circuit 300 illustrated in FIG. 12 includes the signal S4 and the synchronization signal ω1
, And the signal ω1 is in the noise confirmation period TN (TN1,
TN2), it is confirmed that the level of the signal S4 is equal to or lower than a predetermined value, and the signal S5 of the logical value 1 is generated. The illustrated decision circuit 300 has a level. The comparator 301 and the window. It includes a comparator WC2 and a level conversion circuit 302.

Level. The comparator 301 includes a transistor Q61, base bias resistors R61 and R62, a collector resistor R61, a capacitor C61, and a diode D6.
1 and has a threshold value Vth. The threshold value Vth is given by Vth ≒ (1 + R61 / R62) (Vcc-Vbe). Vbe is a base value when the transistor Q61 is turned on. This is the voltage between the emitters.

Level. The transistor Q61 of the comparator 301 is turned on when the signal S4 supplied to the base circuit is lower than the threshold value Vth. Transistor Q
When 61 is turned on, a high-level (logical value 1) signal S51 substantially equal to the sum of the power supply voltage Vcc and the voltage between the terminals of the capacitor C61 is generated on the cathode side of the diode D61 (FIG. 13B). reference). When the signal S4 is higher than the threshold value Vth, the transistor Q61 is off, and a low-level (logical 0) signal S51 substantially equal to the power supply voltage Vcc is generated on the cathode side of the diode D61 (FIG. 9). 13 (b)). In the illustrated embodiment, in order to implement a fail-safe configuration, the logical value 0 substantially corresponds to the level of the power supply voltage Vcc, and the logical value 1 corresponds to the power supply voltage Vcc.
It is configured to correspond to a higher level. level. The signal S51 output from the comparator 301 is
Window. The signal is transmitted to one input terminal A of the comparator WC2.

The level conversion circuit 302 is provided for converting the signal ω1 supplied from the test signal generation circuit 100 (see FIG. 1) to a level usable in the circuit. If not, it may be omitted. The illustrated level conversion circuit 302 includes transistors Q62 and Q62.
63, resistors R64 to R68, a capacitor C62, a diode D62, and the like. The signal ω1 is shown in FIG.
As shown in (b), the noise check period TN (TN1, T
At the time of N2), it becomes a high level (logical value 1) substantially equal to the power supply voltage Vcc, and becomes a low level (logical value 0) given by the GND potential during the inspection period TC.

In the noise checking period TN (TN1, TN2), when a high-level signal ω1 is supplied to the base circuit of the transistor Q62 composed of the resistors R64 and R65, the transistor Q62 turns on. When the transistor Q62 is turned on, the base circuit of the transistor Q63 composed of the resistors R66 and R67 and the transistor Q62 is driven, and the transistor Q63 is turned on. As a result, a high-level (logic 1) signal S5 higher than the power supply voltage Vcc is applied to the cathode side of the diode D62.
2 is generated.

In the inspection period TC (TC1 to TC3), the signal ω1 is at the low level given by the GND potential (see FIG. 13 (c)).
63 is off, and on the cathode side of the diode D62,
A signal S52 having a logical value 0 substantially equal to the power supply voltage Vcc is generated. The signal S52 has a window. Comparator W
The signal is transmitted to the other input terminal B of C2.

Window. The comparator WC2 outputs a signal of logical value 1 only when both of the signals S51 and S52 input to the input terminals A and B have logical value 1.
When one of the signals S51 and S52 reaches the logical value 0, the window. The output of the comparator WC2 has a logical value 0.

Window. An off-state composed of a diode D63 and a capacitor C63 is provided downstream of the comparator WC2. Delay circuit is connected. This off.
The delay circuit is a window. Even after the output of the comparator WC2 becomes a logical value 0, a predetermined OFF. The signal S5 is provided to maintain the state of the logical value 1 until the delay time has elapsed. That is, the inspection period TC (TC1 to TC3)
In the window. Since the output of the comparator WC2 has the logical value 0, the output of the comparator WC2 is turned off. By setting the delay time longer than the inspection period TC, the signal S5 of the logical value 1 can be continuously generated in a normal state.

The above is the operation when the input signal e1 does not contain noise of a predetermined level or more. Next, the case where the input signal e1 contains noise of a predetermined level or more will be described. For example, if the input signal e1 contains noise of a predetermined level or more in the noise check period TN2, the signal S4 goes high in the noise check period TN2 that should be low. Therefore, level. Signal S51 output from comparator 301
Becomes a low level (logical value 0) as shown by a dotted line in FIG. When the signal S51 goes low, the window. The signal S5 output from the comparator WC2 has the logical value 0.

<Noise Detection Circuit Using Second Judgment Method>
FIG. 14 is a block diagram of the noise detection circuit according to the present invention using the second determination method, and FIG. 15 is a time chart illustrating the operation of the noise detection circuit shown in FIG. In the drawings, the same components as those shown in FIGS. 1 and 10 are denoted by the same reference numerals. 3 to 6 can be used for the test signal generation circuit 100, and the circuits shown in FIGS. 7 to 9 can be used for the signal conversion circuit 200.

This embodiment is characterized in that the signal conversion circuit 200
In the subsequent stage, an alternation detection circuit is provided as the determination circuit 300. The determination circuit 300 configured as an alternation detection circuit checks the level of the signal S4. In particular,
As shown in FIG. 15A, the inspection period TC (TC1 to TC
C3) and the noise confirmation period TN (TN1, TN2), the case where the signal S4 (see FIG. 15 (b)) alternately occurs at a predetermined level is determined as normal (noise level en).
1 is equal to or less than a predetermined value).

When the noise level en1 is equal to or higher than the predetermined value, the noise check period TN (TN1, TN2)
The level of the signal S4 increases, and the inspection period TC (TC1 to TC1) increases.
In TC3) and the noise confirmation period TN (TN1, TN2), the alternating repetition characteristic of the signal S4 is lost. This is considered abnormal. Then, when normal, a signal S5 having a logical value of 1 is generated, and when abnormal, a signal S5 having a logical value of 0 is generated (see FIG. 15C).

In the circuit configuration of FIG. 10, for example, a decrease in the amplification degree of the signal conversion circuit 200 (see FIGS. 7 to 9) is not known. A decrease in the degree of amplification means an increase in the threshold for detecting the presence of noise. According to the embodiment of FIG. 14, such a situation can be avoided.

In the case of the alternation detection method, the presence or absence of noise is detected by the decision circuit 300 configured as an alternation detection circuit by confirming that high and low levels are generated alternately. It is not necessary to provide the signal ω1 as shown at 10.

Even if the level of the signal S4 always falls below a predetermined value due to a decrease in the degree of amplification, the signal S5 becomes a logical value 0.
The threshold value for confirming that signal S4 is equal to or less than a predetermined value and the threshold value for confirming that signal S4 is equal to or greater than a predetermined value may be the same or different. .

Further, an inspection period TC caused by a circuit failure
The decrease in the level of the signal S4 at (TC1 to TC3) is also regarded as abnormal, and the signal S5 having the logical value 0 is generated.

The noise detection circuit shown in FIG. 14 includes an AND element WC1. The logical product element WC1 is a logical product operation element, and generates the signal Z of the logical value 1 at least after confirming that the signal S5 is the logical value 1, that is, the noise level en1 is equal to or less than the predetermined value. The AND element WC1 receives the signal S2 as the other input through the path 130 indicated by the dotted line. The reason for this is to detect a state in which the input signal e1 is not transmitted due to the disconnection of the path 110. When the path 110 is disconnected, the signal Z has a logical value 0. As described above, if the test signal generation circuit 100 can be configured so that the signal S4 always becomes high due to the disconnection of the path 110, the signal S2 does not need to be monitored by the logical product element WC1, and therefore, the logical product The element WC1 can be omitted, and the signal S5 can be handled as the signal Z. In that sense, the path 130 is shown by a dotted line.

Further, AND element WC1 has a lower threshold value. Specifically, the lower threshold value is set so as to include the level of the signal S2 in a normal state and not to include the level of the signal S2 when the path 110 is disconnected.

FIG. 16 is a diagram showing a more specific circuit configuration of the noise detection circuit shown in FIG. In this embodiment, the test signal generating circuit 100 shown in FIG. 3 is used. However, it goes without saying that the test signal generation circuit shown in FIGS. The signal conversion circuit 200 employs the one shown in FIG. The AC amplification circuit 202 included in the signal conversion circuit 200 is the same as that shown in FIG.
9 can be used. Judgment circuit 300
Includes a buffer circuit 310 and a detection circuit 320.

FIG. 17 is a time chart for explaining the operation of the noise detection circuit shown in FIG. Inspection signal S1
Is an amplitude modulation signal of the AC signal ω22 output from the second AC signal source Osc2. The amplitude modulation is executed by a switch SW that is turned on / off by the first AC signal source Osc1. With reference to FIG. 3, as already detailed,
Each time the switch SW is turned ON / OFF, that is, in synchronization with the AC signal ω21 from the first AC signal source Osc1, the inspection signal S1 has two different levels, that is, the low level SL.
And a high level SH occurs (see FIG. 17C).

Then, the inspection signal S1 is superimposed on the input signal e1, and a signal S2 is generated (see FIG. 17E).
The signal S2 is input to the signal conversion circuit 200.

The signal conversion circuit 200 amplifies the signal S2 having the low level SL and the high level SH in the internal AC amplifying circuit 202 while maintaining the level ratio between the two. The amplified signal S3 is input to the next-stage rectifier circuit 203.

Since the rectifier circuit 203 outputs a DC signal having a level proportional to the amplitude of the input signal S3, it has a DC level difference substantially proportional to the level difference between the low level SL and the high level SH of the test signal S1. The DC signal S4 is generated (see FIG. 17 (g)).

The signal S4 is input to the judgment circuit 300. In the embodiment of FIG. 16, the determination circuit 300 includes a rectifier circuit 320 together with the buffer circuit 310. The rectifier circuit 320 outputs a DC signal S5 having substantially the same level as the DC level difference generated in the signal S4 (FIG. 17).
(H)). Therefore, the signal S5 is substantially proportional to the level difference between the low level SL and the high level SH of the inspection signal S1.

When the level of the signal S5 is equal to or higher than the lower threshold value VtLb of the input terminal B of the AND element WC1, the signal S5 is regarded as having the logical value 1. If the level of the signal S2 is within the upper and lower thresholds set at the input terminal A of the AND element WC1, a noise detection signal Z having a logical value of 1 meaning no noise is generated.

Next, in the input signal e1, the noise level en1 became higher than the predetermined level at t11 (FIG. 1).
7 (d)), the signal S2 input to the signal processing determination circuit 120 has a noise level e equal to or higher than a predetermined level.
The signal becomes a signal obtained by superimposing the inspection signal S1 on the input signal e1 including the signal n1 and the noise confirmation period TN which should be low level SL.
2. In TN3, the level rises (FIG. 17 (e)
reference). This signal S2 is amplified by the AC amplifier circuit 202 of the signal conversion circuit 200, and the AC amplifier circuit 202 outputs the amplified signal S3 (see FIG. 17 (f)). The AC amplifier circuit 202 similarly amplifies the frequency other than the frequency of the test signal S1. Therefore, the AC signal ω22 and the noise level en1 are similarly amplified.

The signal S2 is for the high level SH inspection period TC.
The levels at (TC1 to TC4) also increase.
However, the output amplitude of the signal S3 output from the amplifier circuit 20 is limited by the power supply voltage (potential) Vcc, and the high level SH when the noise level en1 is equal to or less than a predetermined value is almost full of the amplitude limit. (See FIG. 17F).

Therefore, the low-level noise checking period TN
2. The rise in the level of TN3 appears as a rise in the level of the signal S3, but the rise in the level during the high-level inspection period TC3 to TC4 does not appear in the signal S3. Therefore, in the signal S4 which is the rectification level of the signal S3, the noise confirmation period T
The level difference generated in each of N2 and TN3 and the inspection periods TC3 and TC4 becomes smaller (see FIG. 17G), and therefore, the level of the signal S5 decreases (see FIG. 17H).

When the level of signal S5 becomes lower than lower limit threshold value VtLb (see FIG. 17 (h)) at input terminal B of AND element WC1, noise detection signal Z becomes logical value 0 and becomes abnormal (no noise exists). ) Is reported.

As another configuration, the signal S4 is input to a comparator having a lower threshold value, and the output thereof is
A configuration for transmitting to 00 is also possible. In this case, when the high level is not equal to the level difference of S4 but is equal to or higher than the threshold value of the comparator and the low level is equal to or lower than the threshold value of the comparator, the level of the level input to the comparator is determined. A logical 1 / O signal synchronized with the level signal is transmitted.

The above configuration is particularly effective when an amplifier is omitted. The same effect as the output amplitude limit by the amplifier can be obtained by using the comparator.

FIG. 18 is a specific circuit diagram of the buffer circuit 310 shown in FIG. The illustrated buffer circuit 310 is a known circuit including a push-pull transistor circuit including a transistor Q71 and a transistor Q72. Since the signal S4 is a signal outside the power supply frame,
In order to shift the operating point, the signal S4 is transmitted via the coupling capacitor C71. Between the supply line of the signal S4 and the supply line of the power supply voltage Vcc,
The resistor R71 is connected, and the capacitor C71 is connected to the bases of the transistors Q71 and Q72 via the resistor R72. The signal S41 output from the emitters of the transistors Q71 and Q72 is output to the detection circuit 32 of the next stage.
0 is supplied.

FIG. 19 shows the judgment circuit 30 shown in FIG.
0 shows another specific circuit diagram of FIG. The illustrated determination circuit 3
00 has a lower threshold circuit 321 having a lower threshold Vth and an upper threshold circuit 322 having an upper threshold VtL.

The lower threshold circuit 321 has a transistor Q81 and a transistor Q82. The base of the transistor Q81 has a Zener diode D81,
A circuit composed of the resistors R81 and R82 is connected. The signal S4 is connected to the cathode of the Zener diode D81.
Is supplied. The anode of the Zener diode D81 is connected to one end of the resistor R81, and the other end of the resistor R81 is connected to the base of the transistor Q81. One end of a resistor R82 is connected to the base of the transistor Q81. The other end of the resistor R82 is grounded.

The collector of the transistor Q81 is connected to a series circuit of resistors R86 and R87. The power supply voltage Vcc is supplied to one end of the resistor series circuit. Resistance R
The connection point between the resistor 86 and the resistor R87 is connected to the base of the transistor Q82. The emitter of transistor Q82 receives supply of power supply voltage Vcc. Transistor Q82
Is connected to one end of a resistor R88, and the other end of the resistor R88 is grounded. Transistor Q82
Is connected to one end of a capacitor C81, and the other end of the capacitor C81 is guided to the input terminal A of the AND element WC3. The other end of the capacitor C81 is connected to the cathode of a diode D82. The anode of diode D82 receives supply of power supply voltage Vcc.

In the lower threshold circuit 321 described above, the lower threshold VtL is determined by the Zener diode D81.
Is the zener voltage of Vz, and a base for turning on the transistor Q81. Assuming that the emitter voltage is Vbe, VtL = Vbe × {(R81 / R82) +1} 10 Vz.

Upper threshold circuit 322 includes a transistor Q83. One end of the resistor R84 and one end of the resistor R85 are connected to the base of the transistor Q83. Resistance R
The other end of the signal 84 is connected to the cathode of a Zener diode D81 provided in the lower threshold circuit 321 and the signal S
4 input is received. The other end of the resistor R85 is grounded. The power supply voltage Vcc is applied to the emitter of the transistor Q83.
Is supplied. One end of each of the resistor R89 and the capacitor C82 is connected to the collector of the transistor Q83. The other end of the resistor R89 is grounded.

In the upper limit threshold circuit 322 described above, the upper limit threshold value VtH is equal to the base value for turning on the transistor Q83. When the emitter voltage is Vbe, VtH = {(R84 / R85) +1} (Vcc−Vb
e) given by

The other end of the capacitor C82 is turned on. The delay circuit 323 is connected. The capacitor C8
The other end of 2 is connected to the cathode side of diode D83. The power supply voltage Vc is connected to the anode of the diode D83.
c is supplied.

ON. The delay circuit 323 has a rectifier circuit at an output end. The output terminal of the rectifier circuit is off. One end of a capacitor C83 constituting a delay circuit is connected. The other end of the capacitor C83 has a power supply voltage Vc
c is supplied. on. The output of the delay circuit 323 is
OFF by the capacitor C83. The signal is supplied to another input terminal B of the AND element WC3 via the delay circuit.

AND element WC3 operates upon receiving supply of power supply voltage Vcc. At the output end of the logical product element WC3,
off. One end of a capacitor C84 constituting a delay circuit is connected. The other end of the capacitor C85 is supplied with the power supply voltage Vcc.

FIG. 20 is a time chart for explaining the operation of determination circuit 300 shown in FIG. Hereinafter, the operation of the determination circuit 300 shown in FIG. 19 will be described with reference to the time chart of FIG.

First, the lower threshold circuit 321 outputs the signal S
4 and the lower threshold VtL, S4 ≧ V
When tL is established, a signal Sb1 of logical value 1 is generated, and after S4 ≧ VtL continues for a predetermined time Tb1,
Even if S4 ≧ VtL, the signal Sb1 has a logical value of 0 (see FIGS. 20B and 20C). Logical value 0 of signal Sb1
Is given by the power supply voltage Vcc, and the logical value 1 is the power supply voltage Vc.
It is given at a voltage value higher than c.

The upper limit threshold circuit 322 generates a signal Sb2 having a logical value of 1 when S4 ≦ VtH with respect to the level of the signal S4 and the upper limit threshold VtH, and S4 ≦ VtH
Is maintained for a predetermined time Tb2, S4 ≦ Vt
Even if it is H, the signal Sb1 has a logical value 0 (FIG. 20)
(B), (d)). Signal Sb2 has a logic value 0 given by power supply voltage Vcc and a logic value 1 given by a voltage value higher than power supply voltage Vcc.

The operation of the lower threshold circuit 321 is specifically as follows. When the level of the signal S4 is higher than the lower threshold value VtL, a base current is supplied to the transistor Q81 via the Zener diode D81 in the input section, and the transistor Q81 is turned on and the transistor Q8 is turned on.
2 is also turned on. When the collector potential of the transistor Q82 is G
When the potential rises from the ND potential to the power supply potential Vcc, the rise is differentiated by the capacitor C81, and the power supply voltage Vcc
A signal Sb1 corresponding to a logic value 1 of a higher level is generated.

When the transistor Q82 continues to be turned on,
The level of the signal Sb1 gradually decreases for a predetermined time Tb1.
, The level of the power supply voltage Vcc corresponding to the logical value 0 is reached. Time Tb1 is equal to the time when signal Sb1 is at power supply voltage V
After rising to a level higher than cc, the logical product element WC
3 corresponds to the time required to reach the power supply voltage Vcc, which is the input lower limit threshold of 3.

The operation of upper threshold circuit 322 is almost the same as that of lower threshold circuit 321. When the signal S4 falls below the upper threshold VtH, the transistor Q83 turns on. The transistor Q83 is turned on, and the transistor Q82 is turned on.
Rises from the GND potential to the power supply potential Vcc when the collector potential of the capacitor C82 rises.
And a logical value 1 higher than the power supply voltage Vcc
Is generated (see FIG. 20D).

Noise level en included in input signal e1
When 1 is equal to or less than a predetermined value, the signal S4 repeats a high-level duration Lb and a low-level duration La in a predetermined cycle (see FIGS. 20A and 20B). Duration La, Lb
Is set to be shorter than the times Tb2 and Tb1.

The signal Sb2 is turned on. The signal is input to the delay circuit 323. on. The delay circuit 323 outputs the signal Sb2 having the logical value 1 to a predetermined ON state. When the delay time Ton or more continues (see FIG. 20D), the signal Sb3 of the logical value 1
Is generated (see FIG. 20E). When the signal Sb2 becomes a logical value 0, the on. The output of the delay circuit 323 has a logical value of 0, but the ON. OFF at the output of delay circuit 323. Since the capacitor C83 constituting the delay circuit is connected, a predetermined OFF. Until the delay time Tof elapses, the signal Sb3 keeps the logical value 1 (FIG. 20).
(F)). Accordingly, there is a period in which the signal Sb1 of the logical value 1 and the signal Sb3 of the logical value 1 are simultaneously generated, and the output signal S5 of the AND element WC3 becomes the logical value 1.

When at least one of the signal Sb1 and the signal Sb3 has a logical value of 0, the signal S5 output from the logical product element WC3 has a logical value of 0, but the signal of the capacitor C84 provided at the output portion of the logical product element WC3. off. Due to the delay action, the signal S5 is set to a predetermined OFF. Delay time Tof
The logical value 1 is maintained until 2 elapses. off. By setting the delay time Tof2, a signal S5 having a logical value of 1 is generated in a normal state.

On. The delay circuit 323 is provided to confirm that the state in which the noise is equal to or less than the predetermined value has continued for a predetermined time or more in the noise checking period TN (TN1, TN2). If you do not need this confirmation,
on. The delay circuit 323 may be omitted.

As shown in FIG. 20B, at t11,
When the noise level en1 increases, the level of the signal S4 input to the determination circuit 300 increases during the duration La that should be low. When the level of the signal S4 becomes larger than the upper threshold value VtH during the continuous time La, the signal Sb2 of the logical value 1 does not occur, and the signal Sb2 supplied to the input terminal B of the logical product element WC3 becomes the logical value 0. Therefore, the signal S5 output from the logical product element WC3 has the logical value O. Thereby, the signal processing determination circuit 120
From the noise detection signal Z having a logical value of 0 indicating the presence of noise.
Is output. When the circuit of FIG. 19 is used, an amplifier circuit and the like included in the signal conversion circuit 200 of FIG. 16 can be omitted.

<Noise Detection Circuit Using Third Judgment Method>
FIG. 21 is a block diagram of a noise detection circuit employing the third determination method, and FIG. 22 is a time chart showing the operation of the noise detection circuit shown in FIG. In FIG.
The same components as those shown in 0, 14, and 16 are denoted by the same reference numerals. The test signal generation circuit 100 can use the circuits shown in FIGS. 3 to 6, and the signal conversion circuit 200 can use the circuits shown in FIGS.
Can be used.

This embodiment is characterized in that the judgment circuit 300
That is, it is configured as a coincidence check circuit. The signal S4 and the signal ω1 are input to the determination circuit 300 including the coincidence check circuit. When the signal ω1 indicates the inspection period TC (TC1 to TC3),
When the signal S4 has a level equal to or higher than a predetermined value and the signal ω1 indicates the noise check period TN (TN1, TN2), it is checked that the signal S4 has a level equal to or lower than the predetermined value. , A signal S5 having a logical value of 1 is generated.
That is, a signal S5 having a logical value of 1 is generated based on the confirmation that the desired state represented by the signal S4 and the state represented by the signal ω1 match.

The state of the confirmation is shown in the time chart of FIG. Noise check period TN (TN1, TN
2), which of the inspection periods TC (TC1 to TC3) is determined by the signal ω1 (FIG. 22C)
reference).

In the noise confirmation period TN (TN1, TN2), it is confirmed that the level of the signal S4 is equal to or less than a predetermined value. In the inspection period TC (TC1 to TC3),
It is confirmed that the level of the signal S4 is equal to or higher than a predetermined value. Based on both confirmations, a signal S5 having a logical value of 1 is generated.

At time t11, when the noise level en1 of the input signal e1 rises (see FIG. 22A) and the level of the signal S4 exceeds a predetermined value, the signal S5 changes to a logical value O (see FIG. 22D). ), The presence of noise is reported.

Further, even if the level of the signal S4 falls below a predetermined value due to a decrease in the amplification degree, the signal S5 becomes a logical value 0. The threshold value for confirming that the signal S4 is equal to or less than a predetermined value and the threshold value for confirming that the signal S4 is equal to or greater than a predetermined value may be the same or different. The basic operation of the test signal generation circuit 100 and the signal conversion circuit 200 is as follows.
As described above.

FIG. 23 shows a decision circuit 300 included in FIG.
FIG. 3 is a block diagram showing a specific configuration of FIG. The illustrated decision circuit 300 has a level. It includes a comparator 330, a level conversion circuit 340, and an exclusive OR circuit 350. level. The same circuit as that shown in FIG. 12 can be used for the comparator 330 and the level conversion circuit 340. Here, a description will be given assuming that they are used.

Level. The comparator 330 outputs the signal S4
Is calculated using a threshold value. When the signal S4 is below the threshold, the level. The output of the comparator 330 is a signal corresponding to a logical value 1 higher than the power supply voltage Vcc. When the signal S4 is equal to or higher than the threshold value, the output is a signal corresponding to a logical value 0 substantially equal to the power supply voltage Vcc. .

On the other hand, the signal ω1 is input to the level conversion circuit 340 via the NOT operation circuit 360. Then, the signal ω1 having the logical value 0 is converted into a signal having a higher level than the power supply voltage Vcc, and the signal ω1 having the logical value 1 is converted into a signal having substantially the same level as the power supply voltage Vcc.

Level. The outputs of the comparator 330 and the level conversion circuit 340 are input to the exclusive OR circuit 350. In the noise check period TN (TN1, TN2), the signal ω1 has a logical value of 1 (see FIG. 22C), so that the level conversion circuit 340 outputs a logical value of 0. If the level of the signal S4 is equal to or lower than a predetermined value, the level. The comparator 330 outputs a logical value “1”.

In the inspection period TC (TC1 to TC3), the signal ω1 has a logical value of 0, so that the level conversion circuit 340 outputs a logical value of 1. If the level of the signal S4 is equal to or higher than a predetermined value, the level. The comparator 330 outputs a logical value O. Therefore, in a normal state, a combination of the logical value (1, 0) or (0, 1) is input to the exclusive OR circuit 350, so that the exclusive OR circuit 350 Generate S5.

During the inspection period TC (TC1 to TC3), the signal S
4 is less than a predetermined value, or the noise confirmation period T
If the level of the signal S4 is greater than or equal to a predetermined value in N (TN1, TN2), the exclusive-OR circuit 350 outputs the logical value (1, 1) to the exclusive-OR circuit 350.
Or (0, 0) is inputted, so that the signal S of the logical value 0
5 is generated.

The negation operation circuit 360 is provided to set a combination of two input signals input to the exclusive OR circuit 350 in a normal state to a logical value (1, 0) or (0, 1). Further, the level conversion circuit 340 is provided to match the level of the logical value 1 or 0 in the coincidence check circuit.
Therefore, if such level adjustment is not necessary, it may be omitted.

The illustrated exclusive OR circuit 350 includes two resistors Rt having the same resistance value and a level. And a comparator 370. One end of each of the two resistors Rt has a level. The other end is connected to the comparator 330 and the level conversion circuit 340, and the other end is connected in common. It is connected to the comparator 370. This exclusive OR circuit 350 is already known, and the level. The lower threshold and the upper threshold can be set by the values of the comparator 370 and the two resistors Rt. Input is a logical value (1, 0)
Or (0, 1), of the two resistors Rt
Only one resistor Rt appears as an input part resistor. This state is set to be regarded as normal. When the input has a combination of logical values (1, 1), the resistance of the input section becomes Rt.
Looks like / 2. This state is set to be abnormal.

The inspection period TC caused by a circuit failure
The decrease in the level of the signal S4 at (TC1 to TC3) is also regarded as abnormal, and the signal S5 having the logical value 0 is generated.

Referring to FIG. 21, signal S2 is supplied to path 13
0 is input to the AND element WC1. This is for detecting disconnection of the path 110. As described above, when the path 110 is disconnected, the signal S
4 so that the test signal generation circuit 10
If 0 can be configured, it is not necessary to monitor the signal S2 with the logical product element WC1, and therefore, the logical product element WC1 is omitted, and
The signal S5 can be handled as the noise detection signal Z.
In that sense, the path 130 is shown by a dotted line.

In the noise detection circuits shown in FIGS. 14 to 20, when the test signal S1 disappears, the level of the signal S4 repeats high and low due to intermittent noise.
As if it were a normal state, the signal S of logical value 1
5 may be generated. To prevent that,
In the noise detection circuits shown in FIGS. 14 to 20, the ON. A delay circuit is provided. In the embodiment shown in FIGS. 21 to 23, such consideration is not necessary.

<Noise Detection Circuit According to Second Aspect> FIG.
4 is a block diagram of the noise detection circuit according to the second embodiment, FIG. 25 is a diagram showing a frequency-amplification characteristic of the AC amplification circuit 202 included in the noise detection circuit shown in FIG. 24, and FIG. 6 is a time chart for explaining the operation of the noise detection circuit according to the first embodiment. In FIG. 24, parts having the same functions as the constituent parts shown in the above-described drawings are denoted by the same reference numerals.

The noise detecting circuit shown in the figure is characterized in that two frequency signals ω22 and ω23 having different frequencies alternately continue on a time axis for a predetermined period of time.
1 is generated, the test signal S1 and the input signal e1 are combined to generate a signal S2, and the presence or absence of noise is detected from the combined signal S2.

In the embodiment shown in FIG. 24, the test signal generation circuit 100 generates two signals ω22 and ω23 having different frequencies by frequency modulation. Then, the two signals ω22 and ω23 having different frequencies are superimposed on the input signal e1 to generate the signal S2. The signal S2 is amplified by the AC amplifier circuit 202 of the signal processing determination circuit 120.
The AC amplification circuit 202 uses the frequency-amplification degree characteristic to convert two signals ω22 and ω23 having different frequencies into
Convert to different levels.

More specifically, test signal generation circuit 100
Are a first AC signal source Osc1 and a second AC signal source Osc1.
sc2, a third AC signal source Osc3, and a switch SW
And The first AC signal source Osc1 supplies a rectangular wave signal ω21 having a frequency fω21 to the switch SW,
The switch SW is turned on / off. Switch SW
The movable contact c is alternately switched between the contact a and the contact b (see FIG. 26C). As a result, the signal ω22 (see FIG. 26A) of the frequency fω22 output from the second AC signal source Osc2 and the third AC signal source Osc2
The signal ω23 (FIG. 26 (b)) of the frequency fω23 output from the sc3 is the frequency fω of the first AC signal source Osc1.
21 undergoes frequency modulation to generate a signal S1 (FIG. 26).
(See (d)).

A second AC signal source Osc2 is connected to the contact a of the switch SW, and a third AC signal source Osc3 is connected to the contact b. The movable contact c has a resistor R
The other end of the resistor R12 is connected to the supply path 110 of the input signal e1 (see FIG. 26E), and further guided to the signal processing determination circuit 120.

Therefore, by the above-described frequency modulation, the second
The signal ω22 of the frequency fω22 output from the AC signal source Osc2 and the signal ω23 of the frequency fω23 output from the third AC signal source Osc3 are superimposed on the input signal e1 via the resistor R12, and the signal S2 Is generated (Fig. 2
6 (f)). The duration of the signals ω22 and ω23 is equal to the signal ω2 output from the first AC signal source Osc1.
It is determined by the cycle of 1, that is, the time during which the switch SW is on at the contact a and the time at which the switch SW is on at the contact b.

Here, the frequency fω22 of the signal ω22
Is set higher than the frequency fω23 of the signal ω23 (fω
22> fω23), and the frequency fω23 of the signal ω23
Is set higher than the frequency fω21 of the signal ω21. That is, fω22>fω23> fω21
It is. If the frequency fω23 of the signal ω23 and the frequency fω21 of the signal ω21 are substantially the same or the former is low, the signal S1 can be fixed at a constant level when the signal ω23 is output. Is almost the same as in the case of a modulation factor of 100%.

The voltage value Vω2 of the signal S2 is equal to the signal ω21,
Assuming that the voltages of ω22 and ω23 are Vω, Vω2 = Vω × R11 / (R11 + R12).

The AC amplification circuit 202 included in the signal conversion circuit 200 is configured so that the amplification degree has a frequency dependency that depends on the frequency of the input signal S2, and the characteristic is utilized as the amplified signal S3. , Two types of alternating signals of different levels are obtained (see FIG. 26 (g)).

FIG. 25 is a diagram showing an example of the frequency-amplification characteristic of the AC amplifier circuit 202. As illustrated, the amplification degree of the AC amplifier circuit 202 increases as the frequency increases in a frequency region lower than the frequency fc.
It saturates at the frequency fc and has a substantially constant amplification factor (G1) in a frequency region higher than the frequency fc. Similar frequency dependence can be realized by a rectifier circuit.

As shown in FIG. 25, the frequency f
ω22 and fω23 are fω2 with respect to the frequency fc.
2>fc> fω23 and the frequency f
Assuming that the gain at ω23 is G2 and the gain at frequency fω22 is G1, G2 <G1.

Therefore, when the signal S2 is a signal of the frequency fω22, the signal S2 output from the AC amplification circuit 202
The level Vω22 of No. 3 is Vω22 、 G1 × Vω × R11 / (R11 + R12), where Vω is the level of the signals ω22 and ω23.

When the signal S2 is a signal of the frequency fω23, the level Vω23 of the signal S3 output from the AC amplifier circuit 202 is as follows: Vω23 ≒ G2 × Vω × R11 / (R11 + R12)

As described above, since G2 <G1,
Vω22> Vω23, and two types of alternating signals S4 of different levels are obtained (see FIG. 26 (h)). This alternating signal S4 is obtained until t11 when there is no noise.

In the judgment circuit 300, the above-described FIGS.
Any of the three determination circuits can be used. However, it is necessary to transmit the signal ω1 in order to use the configurations of FIGS. 10 and 21. Here, the determination circuit 3 by the alternation detection circuit of FIG.
The case where 00 is used will be described. Judgment circuit 300
Is a logical value 1 when the alternation detection signal S4 is input.
Is generated. Window. Comparator WC
1 outputs a signal Z of a logical value 1 without noise, provided that a signal S5 of a logical value 1 is supplied from the determination circuit 300.

Next, in the input signal e1, when the noise level en1 increases at t11, the signal conversion circuit 200
26, the level of the signal S2 input to the AC amplifier circuit 202 is constantly increased (see FIG. 26E).

As described above, in the signal conversion circuit 200, the signal S3 output from the AC amplification circuit 202 is the power supply potential V
Since the signal is limited by cc (see FIG. 26 (g)), the signal S4 output from the signal conversion circuit 200 is always at a high level (see FIG. 26 (h)).

The determination circuit 300 connected to the subsequent stage of the signal conversion circuit 200 determines that the signal S4 has always been at a high level or the level difference has become small, and determines that the signal S4 has an abnormality. Generate S5. Judgment circuit 30
As 0, an alternation detection circuit having the configuration shown in FIGS. 16, 18, and 19 can be used.

Window. The comparator WC1 receives the signal S5 having the logical value 0 from the determination circuit 300,
A signal Z having a logical value 0 is generated and output. As a result, the presence of noise is reported.

The signal conversion circuit 200 has frequency characteristics with respect to the frequency of the input signal and the degree of amplification.
The noise level en1 regarded as abnormal has frequency characteristics.

When the input path 110 of the input signal e1 is disconnected, the signal S2 is almost at the level Vω. Therefore, for example, by setting G2 × Vω ≧ G1 × Vω × R11 / (R11 + R12), the signal S2 due to the disconnection of the path 110 is set.
Is in the same state as the increase in the noise level en1, and an abnormality is detected. The signal S2 may be input to a not-shown logical product element WC1 and monitored.

FIG. 27 shows the signal S2 input to the signal conversion circuit 200 and the signal S2 output from the signal conversion circuit 200.
3 shows another configuration for providing a frequency dependency between the first and third embodiments. The detection circuit 203 includes a first rectifier circuit 210 and a second rectifier circuit 220. In the first rectifier circuit 210,
One end of the capacitor C22 is connected to the output terminal of the AC amplifier circuit 202, and the other end of the capacitor C22 is connected to the anode of the diode D22 and the cathode of the diode D23. A cathode of a diode D22;
A capacitor C2 is connected between the diode D23 and the anode.
23 are connected. A power supply voltage Vcc is supplied to a connection point between the anode of the diode D23 and the capacitor C23.

In the second rectifier circuit 220, the capacitor C
24 is connected to the output terminal of the AC amplifier circuit 202, and the other end of the capacitor C24 is connected to a diode D2.
4 are connected to the cathode of the diode D25. The cathode of the diode D24 and the diode D
A capacitor C25 is connected between the anode of the capacitor C25. The cathode of the diode D24 and the capacitor C
25 is connected to the input terminal of the determination circuit 300.

A connection point between the anode of the diode D25 and the capacitor C25 is connected to a connection point between the cathode of the diode D22 of the first rectifier circuit 210 and the capacitor C23. Therefore, the rectified output obtained by the second rectifier circuit 220 is added to the rectified output Sa of the first rectifier circuit 210.

Further, in this embodiment, the first rectifier circuit 2
The tenth and second rectifier circuits 220 have different frequency dependencies. Such frequency characteristics of the first and second rectifier circuits 210 and 220 correspond to the capacitor C2 that constitutes the rectifier circuit.
It can be obtained by selecting capacitance values of 2 to C25. The first rectifier circuit 210 has at least a frequency f
An AC signal of ω23 or more is rectified to generate a signal Sa having a logical value 1 having a higher level than the power supply potential Vcc.

On the other hand, the second rectifier circuit 220 operates at the frequency f
A signal having a frequency equal to or higher than c is rectified to generate a high-level (logical value 1) signal, and a signal having a frequency lower than the frequency fc is not rectified. In this embodiment, fω22>fc> fω
23, the frequency fω2
The two signal components are rectified by both the first rectifier circuit 210 and the second rectifier circuit 220 and are added.

Next, the determination circuit 300 includes a first threshold circuit 331, a second threshold circuit 332, and an OFF. And a delay circuit 333. The first threshold circuit 331 has an input terminal connected to the output terminal of the signal conversion circuit 200 and an output terminal connected to the window. It is connected to the input terminal A of the comparator WC2. The input terminal of the second threshold circuit 332 is commonly connected to the input terminal of the first threshold circuit 331, and is connected to the output terminal of the signal conversion circuit 200.
off. The delay circuit 333 has an input terminal connected to the output terminal of the second threshold circuit 332 and an output terminal connected to the window.
It is led to the input terminal B of the comparator WC2. Window. The output terminal of the comparator WC2 is turned off. One end of a capacitor C26 constituting a delay circuit is connected. The other end of the capacitor C26 is supplied with the power supply voltage Vcc. The above-described determination circuit 300 may have the same circuit configuration as that shown in FIG.

FIG. 28 shows the signal conversion circuit 20 shown in FIG.
6 is a time chart for explaining the operation of a noise detection circuit using 0 and a determination circuit 300. Next, the operation of the noise detection circuit including the circuit shown in FIG. 27 will be described with reference to FIG.

A signal S2 obtained by superimposing the test signal S1 (see FIG. 28A) and the input signal e1 (see FIG. 28B)
(See FIG. 28C) is amplified by the AC amplifier circuit 202. The signal S3 amplified by the AC amplifier circuit 202 is input to each of the first and second rectifier circuits 210 and 220.

The first rectifier circuit 210 rectifies an AC signal having at least a frequency fω23 or higher to generate a power supply potential Vcc.
The second rectifier circuit 220 rectifies a signal having a frequency equal to or higher than the frequency fc to generate a signal having a higher level (logical value 1). It does not rectify frequency signals lower than the frequency fc.

Therefore, the first and second rectifier circuits 210,
In the signal S3 (see FIG. 28D) input to the signal 220, the component of the frequency fω22 included in the signal S3 is rectified by both the first rectifier circuit 210 and the second rectifier circuit 220, and added. Therefore, the signal S4 output from the first and second rectifier circuits 210 and 220 has a level corresponding to the logical value 2 in the multi-level logic higher than the level corresponding to the logical value 1 described above. (FIG. 28 (f)
reference).

On the other hand, the frequency fω23 contained in the signal S3
Is rectified only by the first rectifier circuit 210 and is not rectified by the second rectifier circuit 220, so that the signal S4 has a level corresponding to the logical value 1 (FIG. 28F).
reference). In this way, it is possible to obtain, as the signal S4, alternating signals of two different levels of the logical value 2 and the logical value 1 (see FIG. 28 (f)).

The signal S4 is input to the judgment circuit 300, and the level is detected by the threshold values VtH and VtL set in the first and second threshold circuits 331 and 332 (see FIG. 28 (f)). 28 (g) is generated by the first threshold circuit 331, and the signal S52 is generated by the second threshold circuit 332. The signal S51 is generated by the first threshold circuit 331. The signal S51 is supplied to the input terminal A of the window comparator WC2.
Signal S52 generated by the threshold circuit 332 of the off-state. A signal S53 (see FIG. 28 (h)) delayed by the time Td1 by the delay circuit 333 becomes a signal S5.
3 is a window. It is supplied to the input terminal B of the comparator WC2.

Noise level en included in input signal e1
When 1 increases at t11 (see FIG. 28 (b)), the levels of the signal S2 and the amplified signal S3 are constantly increased (see FIGS. 28 (c) and 28 (d)). here,
If the frequency of the noise level en1 is the frequency fc (see FIG. 25), the level of the signal S4 always becomes a high level corresponding to the logical value 2 (see FIG. 28 (f)). The determination circuit 300 determines that the level has always been high or the level difference has become small, and determines that the signal S of the logical value 0 is abnormal.
Notify to the outside as 5 and signal Z. Regarding the disconnection of the path 110, the signal S2 may be input to the AND element WC1 (not shown) and monitored.

<Regarding Fail-Safe Configuration of Logical Elements WC1 to WC3> In each of the above-described embodiments, in order to configure the logical product elements WC1 to WC3 in a fail-safe configuration, for example, a fail-safe configuration shown in FIG. Window. A comparator / AND gate may be used. This window. Comparator is USPatent 4,661,880
No., US Patent 5,027,114 and Japanese Patent Publication No.
This is already known in, for example, JP-A-230006. Also,
Regarding the circuit and its operation and fail-safe characteristics,
IEEJ Transactions on Trans.IEE of Japan Vol.109-c, No.9, Se
p-1989 (a method for constructing an interlock system using a fail-safe logic element with window characteristics), and "Application of Window Comparator to Majority".
Operation "Proc.of 19th International Symp.on Mult
It is shown in literatures such as iple-Valued Logic and IEEE Computer Society (May1989).

For example, the window. The comparator includes resistors R91 to R108 and transistors Q91 to Q97 as shown in FIG. 29. Each of the input terminals A and B has upper and lower threshold values, respectively. When a signal having an input level within the threshold range is input, the signal oscillates at a high frequency and an AC output signal is obtained at a terminal U. That is, when the input voltages of the input terminals A and B are V1 and V2 and the power supply voltage is Vcc, (R91 + R92 + R93) Vcc / R93 <Vl <(R96 + R97) Vc
c / R97 (R101 + R102 + R103) Vcc / R103 <V2 <(R106 + R1
07) It oscillates only when the condition of Vcc / R107 is satisfied by each person's signal.

Here, the window. The upper and lower thresholds of the input terminal A of the comparator are set to TA
H and TAL, and the upper and lower thresholds of the input terminal B are TBH and TBL, respectively.
The input signal Va to the input terminal B and the human power levels V1 and V2 of the input signal Vb to the input terminal B cause the window. The comparator performs the following operation.

F = Fa · Fb where Fa = 1 (TAH ≧ V1 ≧ TAL), Fa = 0 (TAH <V1 or V1 <
TAL) Fb = 1 (TBH ≧ V2 ≧ TBL), Fb = 0 (TBH <V2 or V2 <
TBL) where F is the window. AND output of the comparator,
Fa is a logical input signal input to the input terminal A, and Fb is a logical input signal input to the input terminal B. When the upper threshold value of each input terminal is set sufficiently large, this window. The comparator simply has a function as a fail-safe AND operation element.

By providing a rectifier circuit at the output section and inputting an AC signal from the terminal U, the logical product output F is
It is possible to obtain a DC signal whose level when the logical value is 1 is higher than the level when the logical product is 0.

FIG. 30 is a circuit diagram showing the fail safe. level. 2 shows a comparator. This circuit is
Transistors Q301 and Q303 and resistors R301 to R3
08. The input terminal A has a lower threshold value and an upper threshold value, and the respective values are equal to those in FIG. Also, the self-oscillation is performed when the input signal level supplied to the input terminal A is within the upper and lower thresholds, and the oscillation is stopped when the input signal level is outside the thresholds, as in FIG.

<On. Fail-safe configuration of delay circuit> Means for making the delay circuit 323 a fail-safe circuit configuration include International Publication WO94 / 23303 and International Publication W
Nos. 094/23496, JP-B-1-230606, and JP-A-9-162714. A delay circuit can be used.

FIG. 31 shows such a fail-safe ON. A specific configuration example of the delay circuit is shown. ON shown.
The delay circuit includes a PUT oscillation circuit 410, a level conversion circuit 420, a rectifier circuit 430, and a feedback resistor Rf.

The PUT oscillation circuit 410 has a predetermined delay time after the signal is applied to the input terminal Uy.
(Programmable unijunction transistor) to generate an oscillation pulse.

Level conversion circuit 420 converts the output signal of PUT oscillation circuit 410 into a change equal to or lower than power supply potential Vcc and inverts the phase.

Fail safe. Window. The comparator WC has the circuit configuration shown in FIG. 29, and generates an output of logical value 1 when a signal having a level higher than the power supply potential Vcc is input to both of the input terminals A and B. The rectifier circuit 430 rectifies the AC output of the window comparator WC. The feedback resistor Rf returns the output signal of the rectifier circuit 430 to the input terminal B side, and forms a self-holding circuit.

The PUT oscillation circuit 410 includes a PUT, resistors R401 to R404, and a capacitor C401. The level conversion circuit 420 includes resistors R405 to R407.
And a transistor Q401. Further, the capacitor C402 and the diode D401 generate a differential signal of the rising edge of the signal from the level conversion circuit 420, and generate the window. This is for inputting to the input terminal B of the comparator WC.

This ON. The operation of the delay circuit will be briefly described. First, when an input signal having a level higher than the power supply potential Vcc is supplied to the input terminal Uy, this signal is supplied to the window. The signal is inputted to one input terminal A of the comparator WC, and the time constant determined by the low resistance value of the resistor R401 of the PUT oscillation circuit 410 and the capacitance of the capacitor C401, and the voltage dividing ratio of the input voltage of the resistor R402 and the resistor R403. After a determined delay time, the PUT conducts and an oscillation output is generated. This oscillation output is inverted in phase by the transistor Q401 of the level conversion circuit 420. Comparator W
It is input to the other input terminal B of C.

When the differential signal is a window. Comparator WC
Is input to the window. The comparator WC oscillates, and an output signal of the oscillation is rectified by the rectifier circuit 430. The rectified output is fed back to the input terminal B via the feedback resistor Rf. Therefore, even if the differential signal at the rising edge of the phase inversion signal disappears, the input of the input terminal B is held by itself.
As a result, the window. The comparator WC continues to oscillate until the level of the input signal Uy falls below the lower threshold of the input terminal A.

The ON. According to the delay circuit, the PU
In the T oscillation circuit 410, for example, the resistors R401 to R4
03, the disconnection or short-circuit failure of the capacitor C401, the three electrode terminals A (anode terminal), K (cathode terminal) and G of the PUT.
Even if a disconnection of the (gate terminal) or a failure of a short circuit between the electrodes occurs, no oscillation output is generated from the PUT oscillation circuit 410. The resistor R404 determines the pulse width of the oscillation output together with the capacitor C401. If a disconnection failure occurs in the resistor R404, the pulse width of the oscillation output is extended.
This on. The delay time of the delay circuit 300 is slightly extended. There is no problem because the side where the delay time is extended is the safe side.

Further, the fail-safe property of the rectifier circuit 430 is described in detail in, for example, International Publication WO93 / 23772.

By using the above-described fail-safe element, when noise having a level equal to or higher than a predetermined value is input, even if a failure occurs in the circuit, a failure which does not erroneously report that there is no noise can be prevented. A safe noise detection circuit can be realized.

[0208]

As described above, according to the present invention, it is possible to provide a noise detection circuit having no upper limit in principle for a detectable noise frequency. Further, as supported by the embodiment, it is possible to easily realize a fail-safe configuration that does not erroneously report the absence of noise even when the noise is equal to or more than a predetermined value at the time of a circuit failure. A noise detection circuit can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a basic configuration of a noise detection circuit according to the present invention.

FIG. 2 is a time chart for explaining the operation of FIG. 1;

FIG. 3 is a specific circuit diagram of a noise detection circuit according to the present invention.

FIG. 4 is a time chart illustrating an operation of the noise detection circuit illustrated in FIG. 3;

FIG. 5 is a diagram showing another circuit configuration of the test signal generation circuit in the noise detection circuit according to the present invention.

FIG. 6 is a diagram showing still another circuit configuration of the test signal generation circuit in the noise detection circuit according to the present invention.

7 is a diagram showing a specific configuration of a determination circuit of the noise detection circuit shown in FIG.

FIG. 8 is an electric circuit diagram showing a specific circuit example of the amplification used in the signal conversion circuit.

FIG. 9 is a specific electric circuit diagram of an amplifier circuit used in the signal conversion circuit.

FIG. 10 is a block diagram of a noise detection circuit employing a first determination method.

FIG. 11 is a time chart illustrating an operation of the noise detection circuit illustrated in FIG. 10;

FIG. 12 is an electric circuit diagram showing a specific configuration example of a low-level confirmation circuit.

FIG. 13 is a time chart for explaining the operation of the low-level confirmation circuit shown in FIG. 12;

FIG. 14 is a block diagram of a noise detection circuit according to the present invention using a second determination method.

15 is a time chart illustrating an operation of the noise detection circuit illustrated in FIG.

FIG. 16 is an electric circuit diagram showing a more specific circuit configuration of the noise detection circuit shown in FIG.

17 is a time chart illustrating an operation of the noise detection circuit illustrated in FIG.

18 is a specific circuit diagram of the buffer circuit shown in FIG.

19 is a specific electric circuit diagram of the detection circuit shown in FIG.

FIG. 20 is a time chart for explaining the operation of the detection circuit shown in FIG. 19;

FIG. 21 is a block diagram of a noise detection circuit employing a third determination method.

FIG. 22 is a time chart illustrating an operation of the noise detection circuit illustrated in FIG. 21;

FIG. 23 is a block diagram showing a specific configuration of a matching check circuit included in FIG. 22;

FIG. 24 is a block diagram of a noise detection circuit according to a second embodiment.

FIG. 25 is a diagram illustrating an example of a frequency-amplification degree characteristic of the amplifier circuit.

26 is a time chart illustrating the operation of the noise detection circuit shown in FIG.

FIG. 27 is an electric circuit diagram showing another configuration for giving frequency dependency between a signal input to the signal conversion circuit and a signal output from the signal conversion circuit.

FIG. 28 is a time chart illustrating an operation of the noise detection circuit using the signal conversion circuit and the alternating detection circuit illustrated in FIG. 27;

FIG. Window. FIG. 3 is an electric circuit diagram showing a comparator / AND gate.

30 is a diagram showing a fail-safe. level. FIG. 3 is an electric circuit diagram showing a comparator.

FIG. 31 shows fail-safe ON. FIG. 3 is an electric circuit diagram showing a specific configuration example of a delay circuit.

FIG. 32 is a block diagram showing a configuration of a conventional noise detection circuit.

FIG. 33 is a time chart illustrating an operation of the noise detection circuit illustrated in FIG. 32.

FIG. 34 is a time chart for explaining a problem in operation of the noise detection circuit shown in FIG. 32;

[Explanation of symbols]

 Reference Signs List 100 inspection signal generation circuit 120 signal processing determination circuit 200 signal conversion circuit 300 determination circuit

Claims (13)

[Claims] 1. A noise detection circuit for detecting the presence or absence of noise that may be included in an input signal, the test circuit generating a test signal that periodically changes in a predetermined pattern on a time axis, A noise detection circuit that combines a test signal with the input signal, confirms the pattern included in the combined signal, and detects the presence or absence of the noise. 2. A noise detection circuit including a test signal generation circuit and a signal processing determination circuit, wherein the test signal generation circuit periodically changes in a predetermined pattern on a time axis. A signal is generated. The signal processing determination circuit receives a synthesized signal obtained by synthesizing the test signal and the input signal, checks the pattern included in the synthesized signal, and determines whether the noise exists. Noise detection circuit that detects 3. The noise detection circuit according to claim 2, wherein the test signal generation circuit generates a test signal that alternately repeats two periods having different voltage levels. 4. The noise detection circuit according to claim 3, wherein the signal processing determination circuit has a threshold with respect to a voltage level of the composite signal, and the composite with respect to the threshold. A noise detection circuit that detects the presence or absence of noise from the signal voltage level. 5. The noise detection circuit according to claim 3, wherein the signal processing determination circuit detects presence / absence of noise from a difference in voltage amplitude periodically occurring in the composite signal. 6. The noise detection circuit according to claim 2, wherein the test signal generation circuit generates a test signal that alternately repeats two periods having different frequencies. 7. The noise detection circuit according to claim 6, wherein the signal processing determination circuit has a threshold with respect to a frequency of the synthesized signal, and the signal processing determination circuit determines a frequency of the synthesized signal with respect to the threshold. Noise detection circuit that detects the presence of noise from the frequency. 8. The noise detection circuit according to claim 6, wherein the signal processing determination circuit detects presence / absence of noise from a frequency difference periodically occurring in the composite signal. 9. The noise detection circuit according to claim 2, wherein the signal processing determination circuit includes a signal conversion circuit and a determination circuit, wherein the signal conversion circuit includes: At a frequency equal to or lower than a predetermined frequency, the conversion constant has a characteristic of decreasing, and converts the amplitude of the input synthesized signal into a DC signal having a level multiplied by a conversion constant and outputs the DC signal. A noise detection circuit for detecting the presence or absence of noise from the level of the DC signal supplied from the circuit. 10. The noise detection circuit according to claim 9, wherein the determination circuit is supplied with a signal synchronized with the inspection signal from the inspection signal generation circuit, and based on the supplied signal. Noise detection circuit that detects the presence or absence of noise. 11. The noise detection circuit according to claim 9, wherein the signal processing determination circuit includes a period in which the combined signal is equal to or less than a predetermined value, and a period in which the combined signal has a predetermined value. A noise detection circuit for detecting the presence / absence of noise based on the presence / absence of alternate repetition of the above period. 12. The noise detection circuit according to claim 9, wherein the signal processing determination circuit comprises:
A noise detection circuit to which a signal synchronized with the inspection signal is supplied and which detects the presence or absence of noise based on the signal. 13. The noise detection circuit according to claim 9, wherein the determination circuit determines whether or not the input DC signal has a level difference greater than or equal to a predetermined value every predetermined cycle. Noise detection circuit that detects the presence or absence of noise.