JP2001223756A - Delay adjusting circuit, receiver, and communication device system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a delay adjusting circuit which adjusts a delay so that a code error rate becomes minimum. SOLUTION: This system is equipped with a variable delay circuit 2 which delays a 1st input signal 1 corresponding to a delay control circuit 24, a fixed delay circuit 8 which delays a 2nd input signal 7 fixedly, and a delay control circuit 22 which generates a delay control signal 24 according to a signal 23 based upon code error rates of output signals 21, 11 of the variable delay circuit 2 and fixed delay circuit 8 and supplies the signal 24 to the variable delay circuit 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay adjusting circuit for adjusting a relative delay of two streams, a receiver, and a communication system.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram showing a conventional delay amount adjusting circuit disclosed in, for example, Japanese Patent Laid-Open No. 4-47806. In the figure, reference numeral 1 denotes a first input signal, and 2 denotes a first input signal. A variable delay circuit for providing the signal 1 with a delay amount according to the delay amount control signal 15, a first filter circuit for filtering an output signal of the variable delay circuit 2, and a variable filter circuit for filtering the output signal of the first filter circuit 3. First main output signal 5 and first branch output signal 6
1 is a first branch circuit. Further, 7 is a second input signal, 8 is a fixed delay circuit for giving a fixed delay amount to the second input signal 7, 9 is a second filter circuit for filtering the output signal of the fixed delay circuit 8, and 10 is The second branch circuit branches the output signal of the second filter circuit 9 into a second main output signal 11 and a second branch output signal 12. 13 is the first
A phase comparator 14 detects the phase difference between the branch output signal 6 and the second branch output signal 12 of FIG. 1 and integrates the phase difference output from the phase comparator 13 to the variable delay circuit 2 as a delay amount control signal 15. It is an integration circuit to supply.

Next, the operation will be described. The delay amount adjusting circuit shown in FIG. 5 is used in a receiver or a transmitter, etc., and adjusts a relative delay amount of two streams to output a signal with a minimum phase difference. In the figure, a variable delay circuit 2 gives a delay amount according to a delay amount control signal 15 to a first input signal 1 such as one baseband signal, and a first filter circuit 3 outputs an output of the variable delay circuit 2. Filter the signal. The first branch circuit 4 converts the output signal of the first filter circuit 3 into a first main output signal 5 and a first branch output signal 6
Branch to Further, the fixed delay circuit 8 gives a fixed delay amount to the second input signal 7 such as the other baseband signal,
The second filter circuit 9 filters the output signal of the fixed delay circuit 8. The second branch circuit 10 branches the output signal of the second filter circuit 9 into a second main output signal 11 and a second branch output signal 12. Then, the phase comparator 13
The phase difference between the first branch output signal 6 and the second branch output signal 12 is detected, and the integration circuit 14 integrates and smoothes the phase difference output from the phase comparator 13 to obtain a delay control signal 15. It is supplied to the variable delay circuit 2. As a result, in the variable delay circuit 2, the first output signal 5 and the second output signal 1
The delay amount is given to the first input signal 1 so that the phase difference from the first input signal 1 becomes minimum.

[0004]

Since the conventional delay amount adjusting circuit is configured as described above, when this delay amount adjusting circuit is used in, for example, a four-phase phase modulation circuit or the like,
Even if the relative delay amount of the two systems is adjusted and minimized, the deviation of the orthogonality of the modulated signal from 90 degrees is minimized due to the variation in the characteristics of the modulation device connected downstream of the delay amount adjustment circuit. Not always, the best signal is not always transmitted. Similarly, even in the case of using it for a demodulation circuit or the like, even if the relative delay amount of two systems is adjusted and minimized,
There has been a problem that a phase difference occurs due to a variation in characteristics of devices connected to a stage subsequent to the delay amount adjusting circuit, so that the code error rate cannot be said to be minimized.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a delay amount adjusting circuit, a receiver, and a communication system for adjusting a delay amount so as to minimize a bit error rate. Aim.

[0006]

A delay adjusting circuit according to the present invention comprises a variable delay circuit for providing a first input signal with a delay according to a delay control signal, and a constant delay for a second input signal. A fixed delay circuit that provides an amount of delay, a variable delay circuit, and a delay amount control circuit that generates a delay amount control signal in accordance with a signal based on a bit error rate of an output signal of the fixed delay circuit and supplies the delay amount control signal to the variable delay circuit. Things.

The delay amount adjusting circuit according to the present invention includes a variable delay circuit for providing a delay amount according to a delay amount control signal to a first input signal, and a filter circuit for filtering an output signal of the variable delay circuit by a first filter circuit. A first branch circuit that branches into a first main output signal and a first branch output signal; a fixed delay circuit that applies a fixed delay amount to the second input signal; A second branch circuit that filters the signal by the second filter circuit and branches into a second main output signal and a second branch output signal; and a phase difference between the first branch output signal and the second branch output signal. An integration circuit for detecting by the comparator and integrating the phase difference; a signal based on the bit error rate of the first main output signal and the second main output signal; and a delay amount control signal according to the output signal of the integration circuit. Delay amount system to generate and supply to variable delay circuit It is obtained by a circuit.

A receiver according to the present invention detects a bit error rate of an output signal from a delay amount adjusting circuit and supplies a signal based on the code error rate to the delay amount adjusting circuit.

A communication system according to the present invention includes a first communication device including a first transmitter and a first receiver, and a second communication device including a second transmitter and a second receiver. The first transmitter modulates and transmits the output signal from the delay amount adjustment circuit, and the second receiver receives the transmission from the first transmitter and demodulates the received signal. The second transmitter detects a bit error rate and outputs a signal based on the bit error rate. The second transmitter modulates and transmits a signal based on the bit error rate. The transmission from the transmitter is received, and a signal based on the demodulated bit error rate is supplied to the delay adjustment circuit of the first transmitter.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. FIG. 1 is a configuration diagram showing a delay amount adjusting circuit according to a first embodiment of the present invention. In the figure, reference numeral 1 denotes a first input signal, and 2 denotes a first input signal 1 in response to a delay amount control signal 24. A variable delay circuit 21 for giving a delay amount is an output signal of the variable delay circuit 2. Reference numeral 7 denotes a second input signal, reference numeral 8 denotes a fixed delay circuit that applies a fixed delay amount to the second input signal 7, and reference numeral 11 denotes an output signal of the fixed delay circuit 8. Further, reference numeral 22 denotes a delay amount control circuit that generates a delay amount control signal 24 in accordance with a signal 23 based on the bit error rate of the output signals 21 and 11 of the variable delay circuit 2 and the fixed delay circuit 8 and supplies the signal to the variable delay circuit 2 It is.

Next, the operation will be described. The delay amount adjusting circuit shown in FIG. 1 is used for a receiver or a transmitter, and controls the relative phase difference between two series of signals so that the bit error rate is always minimized. In the figure, a variable delay circuit 2 gives a delay amount according to a delay amount control signal 24 to a first input signal 1 such as one baseband signal, and outputs an output signal 21. The fixed delay circuit 8
Gives a constant amount of delay to the second input signal 7 such as the other baseband signal and outputs an output signal 11. And
The delay amount control circuit 22 generates a delay amount control signal 24 in accordance with a signal 23 based on the bit error rate of the output signals 21 and 11 of the variable delay circuit 2 and the fixed delay circuit 8, and supplies the signal to the variable delay circuit 2. As a result, in the variable delay circuit 2, the first
The delay amount is given to the first input signal 1 such that the relative phase difference between the output signal 21 and the second output signal 11 always minimizes the bit error rate. Thus, with the configuration shown in FIG. 1, it is possible to obtain a delay amount adjusting circuit that adjusts the delay amount so that the bit error rate is minimized.

Next, a case where the delay amount adjusting circuit shown in FIG. 1 is applied to a receiver will be described. FIG. 2 is a block diagram showing a receiver according to Embodiment 1 of the present invention. In FIG. 2, reference numeral 31 denotes a demodulation circuit for demodulating a received signal, and 32 denotes a code error which always indicates a relative phase difference between two demodulated signals. The delay amount adjusting circuit shown in FIG.
Reference numerals 3 and 34 denote identification circuits for identifying the signs of the two series of output signals from the delay amount adjustment circuit 32, and reference numeral 35 denotes identification circuits 33 and 34.
A demultiplexing circuit for further demultiplexing the two-sequence output signal from the multiplexing circuit, detects a bit error rate of the output signal demultiplexed by the demultiplexing circuit 35, and converts the signal 23 based on the bit error rate into a delay amount adjusting circuit. 32 is a code error rate detection circuit to be supplied to the MPU 32.

Next, the operation will be described. In FIG. 2, a demodulation circuit 31 demodulates a received signal, and a delay amount adjustment circuit 32 controls so that the relative phase difference between the two demodulated signals is minimized. Identification circuits 33 and 34 identify codes according to a comparison between the two series of output signals and the threshold value,
The demultiplexing circuit 35 further demultiplexes the two series of output signals. Then, the bit error rate detection circuit 36 detects the bit error rate of the demultiplexed output signal, and supplies the signal 23 based on the bit error rate to the delay adjustment circuit 32.
As a result, in the variable delay circuit 2 of the delay amount adjustment circuit 32,
The amount of delay is given to the relative phase difference between the two demodulated signals so that the bit error rate is always minimized. in this way,
With the configuration shown in FIG. 2, it is possible to obtain a receiver to which a delay amount adjustment circuit that adjusts the delay amount so as to minimize the bit error rate is applied.

Next, a case where the delay amount adjusting circuit shown in FIG. 1 is applied to a transmitter will be described. FIG. 3 is a configuration diagram showing a communication system according to Embodiment 1 of the present invention. In the drawing, reference numeral 41 denotes a first communication device, 42 denotes a second communication device,
In the first communication device 41, 43 is a first transmitter, 44
Is a first receiver, 45 is a second receiver, and 46 is a second transmitter. Also, the first and second transmitters 43, 46
, 51 is a multiplexing circuit for multiplexing a plurality of series of data and a signal based on a bit error rate, and 52 is controlling the relative phase difference between the multiplexed two series of signals so that the bit error rate is always minimized. The delay amount adjusting circuit 53 shown in FIG.
Is a modulation circuit for modulating and transmitting two series of output signals from the delay adjustment circuit 52. Further, in the first and second receivers 44 and 45, reference numeral 31 denotes a demodulation circuit for demodulating a received signal; 35, a demultiplexing circuit for further demultiplexing a two-series output signal from the demodulation circuit 31; The circuit 35 detects the bit error rate of the output signal demultiplexed by the circuit 35 and multiplexes the signal based on the bit error rate into the multiplexing circuit 51.
Is a circuit for detecting a bit error rate. 54 is a transmission wave transmitted from the first transmitter 43, 55 is the second transmitter 4
6 is a transmission wave transmitted from the transmission wave No. 6.

Next, the operation will be described. FIG.
Is applied to the first transmitter 43 and the second transmitter 46, and the respective bit error rates are detected by the first and second receivers 44 and 45. Then, by feeding back the signals based on the bit error rates to the first and second transmitters 43 and 46, a delay amount is given so that the bit error rate is minimized. First
The delay amount adjusting circuit 52 applied to the transmitter 43 of FIG.
Since the adjustment operation with the delay adjustment circuit 52 applied to the transmitter 46 is the same, only the adjustment operation of the delay adjustment circuit 52 applied to the first transmitter 43 will be described. In the first transmitter 43, the multiplexing circuit 51 multiplexes a plurality of streams of data, and the delay amount adjustment circuit 52 controls the relative phase difference between the multiplexed two streams of signals to be minimized. The modulation circuit 53 modulates the two series of output signals from the delay amount adjustment circuit 52 and transmits a transmission wave 54. In the second receiver 45, the demodulation circuit 31
Receives the transmission wave 54, demodulates the received signal, and the demultiplexing circuit 35 further demultiplexes the two-series output signal from the demodulation circuit 31. The bit error rate detection circuit 36 detects the bit error rate of the output signal demultiplexed by the demultiplexing circuit 35 and outputs a signal based on the bit error rate. Further, in the second transmitter 46, the multiplexing circuit 51 multiplexes a plurality of streams of data and a signal based on the bit error rate, and the modulation circuit 53 outputs the delay amount adjustment circuit 5
The transmission signal 55 is transmitted by modulating two series of output signals from the transmission signal 55. Further, in the first receiver 44, the demodulation circuit 31 receives the transmission wave 55, demodulates the received signal,
The demultiplexing circuit 35 further demultiplexes the two-sequence output signal from the demodulation circuit 31 and supplies a signal based on the code error rate to the delay adjustment circuit 52. As a result, in the variable delay circuit 2 of the delay adjustment circuit 52 of the first transmitter 43, the relative phase difference between the multiplexed two series signals is given a delay amount such that the code error rate is always minimized. . Note that the delay adjustment circuit 52 of the second transmitter 46
The delay amount is adjusted by a signal based on the bit error rate. As described above, with the configuration shown in FIG. 3, it is possible to obtain a transmitter to which the delay amount adjusting circuit for adjusting the delay amount so as to minimize the bit error rate is applied.

As described above, according to the first embodiment, with the configuration shown in FIG. 1, it is possible to obtain a delay amount adjusting circuit for adjusting the delay amount so as to minimize the bit error rate. According to the configuration shown in FIG. 2, it is possible to obtain a receiver to which a delay amount adjusting circuit for adjusting the delay amount so as to minimize the bit error rate is obtained. With the configuration shown in FIG. Thus, it is possible to obtain a transmitter to which a delay amount adjusting circuit for adjusting the delay amount is applied.

Embodiment 2 FIG. FIG. 4 is a block diagram showing a delay amount adjusting circuit according to a second embodiment of the present invention. In the figure, reference numeral 1 denotes a first input signal, and 2 denotes a first input signal 1 in response to a delay amount control signal 65. A variable delay circuit for providing an amount of delay, 3 is a first filter circuit for filtering an output signal of the variable delay circuit 2, and 4 is a first main output signal 61 and a first main output signal 61 for filtering the output signal of the first filter circuit 3. This is a first branch circuit that branches to a branch output signal 62. Further, 7 is a second input signal, 8 is a fixed delay circuit for giving a fixed delay amount to the second input signal 7, 9 is a second filter circuit for filtering the output signal of the fixed delay circuit 8, and 10 is This is a second branch circuit that branches the output signal of the second filter circuit 9 into an output signal (second main output signal) 11 and a second branch output signal 12. Further, 13 is a phase comparator for detecting a phase difference between the first branch output signal 62 and the second branch output signal 12, and 14 is an integration circuit for integrating the phase difference output from the phase comparator 13. Further, 63 is the first and second main output signals 6
A signal 64 based on the bit error rates of 1, 11 and an integrating circuit 1
4 to generate a delay amount control signal 65 in accordance with the output signal of
This is a delay amount control circuit supplied to the variable delay circuit 2.

Next, the operation will be described. The delay amount adjustment circuit shown in FIG. 4 is used in a receiver or a transmitter, and controls the relative phase difference between two series of signals so that the bit error rate is always minimized. In the figure, a variable delay circuit 2 gives a delay amount according to a delay amount control signal 65 to a first input signal 1 such as one baseband signal, and a first filter circuit 3 outputs an output of the variable delay circuit 2. Filter the signal. The first branch circuit 4 branches the output signal of the first filter circuit 3 into a first main output signal 61 and a first branch output signal 62. The fixed delay circuit 8
Gives a fixed amount of delay to the second input signal 7 such as the other baseband signal, and the second filter circuit 9 filters the output signal of the fixed delay circuit 8. The second branch circuit 10 includes:
The output signal of the second filter circuit 9 is converted to the second main output signal 1
It branches to the first and second branch output signals 12. further,
The phase comparator 13 outputs the first branch output signal 62 and the second
The phase difference of the branch output signal 12 of the
Integrates and smoothes the phase difference output from the phase comparator 13. The delay amount control circuit 63 determines a delay amount according to a value obtained by appropriately weighting the signal 64 based on the bit error rate of the first and second main output signals 61 and 11 and the output signal of the integration circuit 14. A control signal 65 is generated and supplied to the variable delay circuit 2. As a result, in the variable delay circuit 2, the delay amount of the first input signal 1 is set so that the relative phase difference between the first main output signal 61 and the second main output signal 11 is always minimized. Given.

Here, the phase difference is detected by the phase comparator 13 by comparing the first and second branch output signals 62,
A response speed several to several tens of times as long as 12 periods can be obtained. On the other hand, the detection of the signal 64 based on the bit error rate of the first and second main output signals 61 and 11 is, for example, 1 / 1,000,000
In order to detect the error rate, it takes 1,000,000 times the period of the first and second main output signals 61 and 11, so that the response becomes slower as the code error rate decreases. Therefore, in the delay amount control circuit 63, the integration circuit 14
And the first and second main output signals 61 and 11
By appropriately weighting the signal based on the two methods, that is, the signal 64 based on the code error rate, and generating the delay control signal 65 according to the value, it is possible to control the delay amount of only the signal based on the code error rate. Compared with this, the responsiveness can be improved and the bit error rate can be minimized quickly.

The delay adjustment circuit shown in the second embodiment may be applied to the configuration of the receiver shown in FIG. 2 and the configuration of the communication system shown in FIG. As compared with the first embodiment, it is possible to obtain a receiver and a transmitter that can quickly minimize the bit error rate with good responsiveness.

As described above, according to the second embodiment, the output signal of the integrating circuit 14 and the signal 64 based on the bit error rate of the first and second main output signals 61 and 11 are used.
By appropriately weighting the signal according to the two methods and generating the delay amount control signal 65 according to the value, the responsiveness and the bit error rate can be improved quickly compared to the delay amount control of only the signal based on the bit error rate. Can be obtained to adjust the delay amount so as to minimize the delay time.

[0022]

As described above, according to the present invention, the first
A variable delay circuit for providing a delay amount according to a delay amount control signal to an input signal of the variable delay circuit, a fixed delay circuit for providing a constant delay amount to the second input signal, and a code error in output signals of the variable delay circuit and the fixed delay circuit. And a delay amount control circuit that generates a delay amount control signal in accordance with the signal based on the rate and supplies the delay amount control signal to the variable delay circuit, so that the delay amount is adjusted so that the bit error rate is minimized. The effect that the adjustment circuit can be obtained is obtained.

According to the present invention, the variable delay circuit for providing the first input signal with a delay amount according to the delay control signal, and the output signal of the variable delay circuit are filtered by the first filter circuit, and the first A first branch circuit for branching into a main output signal and a first branch output signal, a fixed delay circuit for providing a fixed amount of delay to a second input signal, and a second filter circuit for converting an output signal of the fixed delay circuit into a second filter circuit And a second branch circuit that branches into a second main output signal and a second branch output signal, and detects a phase difference between the first branch output signal and the second branch output signal by a phase comparator. An integration circuit that integrates the phase difference; a signal based on the bit error rate of the first main output signal and the second main output signal; and a delay amount control signal generated in accordance with the output signal of the integration circuit, and a variable delay. And a delay amount control circuit for supplying to the circuit. With such a configuration, the delay amount control signal is generated according to two signals, that is, a signal based on the bit error rate of the first main output signal and the second main output signal and an output signal of the integration circuit. Therefore, compared to the control of the delay amount of only the signal based on the bit error rate, the responsiveness is improved,
The effect of obtaining a delay amount adjusting circuit for adjusting the delay amount so that the bit error rate is minimized quickly is obtained.

According to the present invention, the bit error rate of the output signal from the delay amount adjusting circuit is detected and a signal based on the code error rate is supplied to the delay amount adjusting circuit. The effect of obtaining a receiver to which a delay amount adjusting circuit that adjusts the delay amount so as to minimize is obtained.

According to the present invention, the first communication device including the first transmitter and the first receiver and the second communication device including the second transmitter and the second receiver are provided. , The first transmitter modulates and transmits the output signal from the delay adjustment circuit, and the second receiver receives the transmission from the first transmitter, and performs a bit error rate of the demodulated received signal. And outputs a signal based on the bit error rate, the second transmitter modulates and transmits a signal based on the bit error rate, and the first receiver transmits the signal from the second transmitter. Since the transmission is received and a signal based on the demodulated code error rate is supplied to the delay amount adjustment circuit of the first transmitter, the delay amount adjustment for adjusting the delay amount so as to minimize the code error rate is performed. The effect that a transmitter to which the circuit is applied can be obtained is obtained.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a delay amount adjusting circuit according to a first embodiment of the present invention;

FIG. 2 is a configuration diagram showing a receiver according to Embodiment 1 of the present invention.

FIG. 3 is a configuration diagram showing a communication system according to the first embodiment of the present invention.

FIG. 4 is a configuration diagram illustrating a delay amount adjustment circuit according to a second embodiment of the present invention;

FIG. 5 is a configuration diagram illustrating a conventional delay amount adjustment circuit.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 first input signal, 2 variable delay circuit, 3 first filter circuit, 4 first branch circuit, 7 second input signal, 8 fixed delay circuit, 9 second filter circuit, 10
Second branch circuit, 11 output signal (second main output signal), 12 second branch output signal, 13 phase comparator,
14 integration circuit, 21 output signal, 22, 63 delay amount control circuit, 23, 64 signal based on code error rate, 2
4,65 delay amount control signal, 31 demodulation circuit, 32,5
2 delay amount adjustment circuit, 33, 34 identification circuit, 35 demultiplexing circuit, 36 code error rate detection circuit, 41 first communication device, 42 second communication device, 43 first transmitter, 4
4 First receiver, 45 Second receiver, 46 Second transmitter, 51 Multiplexer, 52 Delay adjustment circuit, 5
3 modulation circuits, 54, 55 transmission waves, 61 first main output signal, 62 first branch output signal.

Claims (4)

[Claims] A variable delay circuit for providing a delay amount according to a delay amount control signal to a first input signal; a fixed delay circuit for providing a constant delay amount to a second input signal; A delay amount adjustment circuit comprising: a delay amount control circuit that generates a delay amount control signal in accordance with a signal based on a bit error rate of an output signal of a fixed delay circuit and supplies the delay amount control signal to the variable delay circuit. 2. A variable delay circuit for providing a delay amount according to a delay amount control signal to a first input signal, a first filter circuit for filtering an output signal of the variable delay circuit, and the first filter. The output signal of the circuit is divided into a first main output signal and a first main output signal.
A first branch circuit for branching into a branched output signal, a fixed delay circuit for providing a fixed delay amount to the second input signal, a second filter circuit for filtering an output signal of the fixed delay circuit, A second branch circuit that branches the output signal of the second filter circuit into a second main output signal and a second branch output signal, and detects a phase difference between the first branch output signal and the second branch output signal Comparator, an integration circuit for integrating the phase difference output from the phase comparator, a signal based on the bit error rate of the first main output signal and the second main output signal, and an output signal of the integration circuit And a delay amount control circuit that generates a delay amount control signal in accordance with the control signal and supplies the delay amount control signal to the variable delay circuit. 3. The delay amount adjusting circuit according to claim 1, wherein a signal error rate of an output signal from the delay amount adjusting circuit is detected, and a signal based on the code error rate is supplied to the delay amount adjusting circuit. Receiver. 4. A first communication device comprising a first transmitter and a first receiver, and a second communication device comprising a second transmitter and a second receiver. The transmitter of claim 1 modulates the output signal from the delay amount adjusting circuit according to claim 1 or 2 and transmits the modulated signal.
Receiving the transmission from the transmitter, detects the bit error rate of the demodulated received signal, and outputs a signal based on the bit error rate. The second transmitter modulates the signal based on the bit error rate. The first receiver receives the transmission from the second transmitter and supplies a signal based on the demodulated code error rate to the delay adjustment circuit of the first transmitter. A communication system characterized by the following.