JP2001222865A - Digital signal reproducing device and reproducing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the number of times of access to a temporary storage means when reproducing a disk having large capacity at high speed. SOLUTION: Data obtained by demodulating data read out from a disk is not recorded once in a storage means, but recorded in a temporary storage means after error correction in a row direction is performed. Next, error correction in a column direction is performed for data recorded in the temporary storage means, scramble processing is performed at the same time when data of which the error is already corrected and which is recorded in the temporary storage means is outputted. Thereby, the access to the temporary storage means is constituted of three times of access of write-in processing of row direction data, error correction processing in a column direction, and output processing in a row direction by processing simultaneously conforming to features of data operation, thereby, accessing times to the temporary storage means can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reproducing apparatus for an optical disk on which a digital signal is recorded.

[0002]

2. Description of the Related Art As a typical digital signal reproducing apparatus,
CD (Compact Disc) and DVD are mentioned. When a digital signal is reproduced, data read from a disk is demodulated by a demodulation unit, further subjected to error correction by an error correction unit, and output. An example of access to the temporary storage means when playing a DVD is described in Japanese Patent Application No. 9-6 / 1990.
As seen in No. 5900, reproduced input data is recorded in temporary storage after demodulation processing, error correction is performed by error correction means, and error-corrected data is temporarily stored. Output from the output means in response to an external request. In the error correction, data recorded in the temporary storage unit is once read, an error position and error correction data are calculated, and an error portion of the data in the temporary storage unit is overwritten with correct data. In the DVD format, a block product code is used to improve the correction capability.
They are arranged in a dimension, and the encoding process is performed in each of the row direction (PI) and the column direction (PO). Therefore, error correction processing is performed in both the row direction and the column direction of data in block units. In addition, DVD data avoids fixed data patterns that can adversely affect disc playback,
Scramble processing is performed, and it is necessary to scramble (descramble) when outputting data. The descrambling process for this is performed simultaneously with the data output to the host.

At the time of data reproduction, the temporary storage means is used for error correction and output buffers as described above. The output buffer is used as an interface buffer when outputting to an external host (for example, a personal computer) for storing data to be output in order to transfer a large amount of data in a short time. When the two uses described above are performed by two temporary storage units, the error correction process and the output process to the outside can be performed independently.
The error correction processing can be performed on the data that has been demodulated and recorded in the temporary storage means. The error-corrected data is stored in a temporary storage unit (output buffer) different from the one for error correction by utilizing the time during which the temporary storage unit is not accessed in writing after demodulation processing or error correction processing. Can be stored. Further, the error-corrected data stored in the output buffer can be output in response to a request from the host. Therefore, when two temporary storage units are used, data can be output to the host without being affected by access to the temporary storage unit due to error correction. However, when the two uses are performed by one temporary storage unit, it is necessary to control the system so that each process can be performed within the required time.

[0004]

As described above, when reproducing a digital signal, data processing at the time of error correction processing and output processing is performed via temporary storage means. Therefore, the number of accesses to the temporary storage unit increases. Furthermore, the time for accessing the temporary storage means is limited for reproducing within a certain fixed time, and the time for accessing the temporary storage means is further reduced for high-speed processing. Therefore, when reproducing a large-capacity disk such as a DVD at a high speed, it is necessary to reduce the number of accesses to the temporary storage means.

[0005] Further, when the use for error correction and output buffer is performed by one temporary storage means, the time required for the output processing to the external host and the error correction processing is taken into consideration, and the slot of the temporary storage means is limited. In addition to performing the processing within the time, a system configuration for increasing the occupancy of the temporary storage means is required.

As described above, an object of the present invention is to reduce the number of accesses to the temporary storage means in a system in which one use is made for error correction and for use as an output buffer using one temporary storage means.

[0007]

According to the present invention, in a disk reproducing apparatus, demodulation processing of data is performed in the order read from the disk, and h (h: natural number) is used in the same order of the data subjected to the demodulation processing. ) Error correction in the PI direction is performed on the data divided in byte units, and the data after the PI error correction is recorded in the temporary storage means without temporarily recording the demodulated data. Reduce access times.

The selection of access to the temporary storage means is determined by the priority of each means. The priority of the error correction means having the largest number of accesses is set to the lowest, and the idle time of the demodulation and output processing is set. By performing error correction, the burst transfer capability at the time of output to an external host is kept high.

[0009]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a digital signal reproducing apparatus according to a first embodiment of the present invention. In this embodiment, a case where data in accordance with the format shown in FIGS. 2 and 3 is input will be described as an example. FIG. 2 shows one data sector structure. The input data is divided into units of 2048 bytes, 6 bytes of ID 201 having information such as the sector number are added before the main data, and then the data is divided into units of 172 bytes and one row (1 row) Thus, one data sector is composed of 12 rows. 202 is a control information part (RSV) 6 bytes, 203 is main data 2048 bytes, and 204 is an error detection code (EDC) 4 bytes. FIG. 3 shows a 1-ECC block data structure. PI is a row-direction error correction code 302, and PO is a column-direction error correction code 3.
03. The 16 consecutive data sectors 301 are arranged in order to form one ECC block.

In FIG. 1, reference numeral 101 denotes an optical disk; 102, an optical pickup for reproducing data from the optical disk 101; and 103, a spindle motor for rotating the disk. Also,
A servo 104 controls the optical pickup 102 and the like.
A read channel 105 performs waveform equalization processing, binarization, and synchronous clock generation of an analog reproduction signal read from the disk 101. 109 is a RAM control means for controlling access to the RAM from each means, and 110 is a RAM for temporarily storing data. 113 is an external host (for example, a personal computer),
A microcomputer 114 controls the system. Also, 120
Is a writing means for performing demodulation and error correction in the PI direction and recording it in the RAM 110, 121 is an error correction means in the PO direction for data in the RAM 110, and 122 is scrambled for error-corrected data. Output means for outputting.

Hereinafter, the operation of the digital signal reproducing apparatus shown in FIG. 1 will be described.

The disk 101 rotated by the motor 103
In response, data is read out by the pickup 102,
The signal is converted into a digital signal in the read channel 105. The digital signal read from the disk 101 is subjected to arithmetic processing in the row direction by the writing means 120. First, demodulation is performed according to the modulation rule, error correction is performed on data in the same direction (PI direction) as the order in which demodulation processing is performed, and the data is recorded in the RAM 110. Next, the column direction error correction means 121 performs error correction on the data stored in the RAM 110 in the column direction (PO direction). At this time, RAM
An error in the data read from 110 overwrites the error position of the data on RAM 110. In addition, host 113
In response to the request, the output-corrected data is scrambled by the output means 212 and then output. Each RAM 110
The access to the RAM is controlled by the RAM control unit 109, and the access control and the management of the address in the RAM 110 are performed so that each process can perform the process within a desired time.

As described above, by performing the processing simultaneously according to the characteristics of the data in the calculation direction, the RAM 110 can be constituted by three accesses of writing data in the row direction, correcting errors in the column direction, and outputting data in the row direction. Can reduce the number of accesses to.

Next, a detailed configuration will be described with reference to FIG.

In FIG. 11, reference numeral 106 denotes a demodulating means for demodulating the read data, 107 denotes an error correcting means for correcting errors in the PI direction, and 108 denotes an error correcting means for correcting errors in the PO direction. Also,
111 is a descrambler for scrambling the error-corrected data to be output, and 112 is an ATAPI (= host interface) for performing output processing in response to a request from an external host. Others are equivalent to those seen in FIG.

Hereinafter, the operation of the digital signal reproducing apparatus shown in FIG. 11 will be described.

The demodulation means 106 demodulates the digital signal read from the disk 101 in accordance with the modulation rule. However, at this time, the demodulated data is not directly transferred to the RAM 110 but is transferred to the PI direction error correction means 107. Therefore, error correction is performed on data in the same row direction (PI direction) as the order in which demodulation processing is performed. At this time, corrected data is generated on the RAM 2 115 dedicated to PI error correction, and then RA
The data is written to the RAM 110 via the M control means 109. The PI error correction RAM 115 has a size capable of temporarily storing data in row units to be demodulated within the PI error correction processing time. Next, error correction is performed by the PO error correction means 108 in the column direction (PO direction) of the data stored in the RAM 110. At this time, an error in the data read from the RAM 110 overwrites an error position of the data on the RAM 110. Further, it outputs error-corrected data in response to a request from the host 113. Output processing is performed by ATAPI 112. However, since the data to be input to the ATAPI 112 needs to be data after descrambling, the RAM 110
The read data (data after error correction) is descrambled by descrambling means 111 and transferred. Conventionally, demodulated data is stored in RAM 110
The data is read out once and calculated after
The error portion on the RAM 110 was overwritten with correct data by the PI error correction data.

However, in the present invention, by providing a dedicated RAM2 115 for error correction in the PI direction, the PI2 of the demodulated data is provided.
After error-corrected data is generated, it is written to the RAM 110.

The data after the demodulation processing is temporarily stored in the RAM 110
Therefore, access to the RAM 110 when reading data in the PI direction and writing correction data is deleted. In the data having the block structure shown in FIG. 3, the reading of the row direction data of 182 bytes × 208 rows and the writing of error correction of up to 5 bytes × 208 rows can be deleted. Therefore, access to the RAM 110 can be reduced. Also, the descrambling means is RAM 110 and ATAPI 112
, The error-corrected data is not returned to the RAM 110 after the descrambling process, but is output as it is, so that the number of accesses to the RAM 110 can be reduced. To realize high-speed reproduction, a high-speed RAM can be used or the data bus width of the RAM can be increased, but the circuit scale increases. However, according to the configuration of the present invention, the R of the capacity capable of performing the error correction in the ECC block row direction is obtained.
By simply adding the AM 115, high-speed reproduction can be realized without increasing the data bus width, and a significant increase in circuit size can be suppressed.

In the RAM control means 109 of FIGS. 1 and 11, the control of the RAM access of each channel is executed based on the priority. Maximum DMA in one ECC block from each means (Dir
ectMemory Access) Since the number of requests is fixed, DMA
Channels for which requests are periodically generated are placed at a higher priority, and the priority is fixed. In this method, no waste occurs in the RAM access, so that the efficiency of use of the RAM bus can be increased and a high transfer rate can be secured for the data output having the lower priority. The priority order is determined in consideration of the DMA margin time for each channel and the DMA occupancy. In order to complete the decoding process such as demodulation and error correction within a certain processing time, and to read the decoded data upon request from the host side, the priority is signal processing. Must be performed in the order in which they are performed. However, in the digital signal reproducing apparatus of the present invention, unlike the above, the order of writing after demodulation and PI error correction> ATAPI output (descrambling)> PO error correction. RAM 110 for data read from optical disk
Since it is impossible to stop the writing process to the RAM 110, the demodulation and the writing of the error-corrected data in the PI direction to the RAM 110 need to be the highest priority. Further, since the RAM 110 of the digital signal reproducing apparatus of the present invention also serves as an error correction buffer and an output buffer, access requests for the error correction processing and the output processing frequently occur. To complete the PO error correction process in a fixed time,
Since the error correction process occupies the RAM 110, almost no access is allocated to the output process during that time, and large-capacity continuous transfer cannot be performed at the request of the host. Therefore, in order to prevent the output processing by the ATAPI 112 from being greatly delayed, the order of access at the time of output is set higher than the PO error correction access that requires the longest time. This makes it possible to respond to a large-capacity continuous transfer request from the host. Conversely, a waiting time for the RAM access of the PO error correction means having the lowest priority occurs, and it cannot be completed within a fixed time. However, the error correction processing is changed by changing the processing time according to the input. In addition, the present invention is not limited to the above embodiment, and can be implemented with various modifications. For example, the priority order is the order in which signal processing is performed, that is, writing after demodulation and PI error correction> PO error correction> ATAPI output (descrambling), and the priority order of PO error correction and output is reversed at a certain fixed cycle. This can be similarly configured. Since the output processing can interrupt the PO error correction processing at a certain fixed cycle, large-capacity continuous transfer can be performed by setting a cycle capable of processing the amount of data required by the host within the required time.

FIG. 4 is a timing chart of the operation processing block. The processing operation in each means is performed in units of one ECC block, and the processing is performed on the block in which the previous processing has been completed in units of one ECC block. FIG. 4A shows a sequential operation. In the sequential operation, data read from a disk is continuously processed and output as it is. Some numbers (n: natural numbers) in FIG. 4 are stored in the RAM 110.
ECC block number. As can be seen from the figure, after the demodulation / PI corrected data write processing is performed in units of one block, PO error correction is performed, and data in units of one block after error correction is output. Similarly, processing is continuously performed in block units. Control of blocks in RAM
This is performed as shown in FIG. 804 is the RAM address, 80
5 is an ECC block. FIG. 8A is a flowchart of the block control, and FIG. 8B is an address map of the RAM, and an output process will be described as an example. In this case, the output processing block number is “A” 806, and the processing block number of the PO error correction that is the previous processing is “B” 807. The PO error correction block number (B = n) and the output block number (A = n) are compared to determine whether they are the same (801), and if they are the same, the previous processing (in this example, the PO error correction processing) is performed. Since n-block processing is in progress, access to this block in output processing is prohibited.
However, when the processing of one block is completed, the block number is set to 1
By incrementing (808, B = n + 1), the block number of the PO error correction block number (B = n + 1) does not match the block number of the output block number (A = n), and RAM access for output processing is permitted. , Start the process. Similarly for other processing blocks,
The ECC block access on the RAM is controlled by comparing with the block number of the previous processing. With this control, access is performed in units of blocks in the RAM, and access for one block of each process can be guaranteed within the time of reproduction from the disk.

FIG. 4B shows the cache hit operation. The cache hit operation is a process for previously input data, in which data stored in the RAM 110 is first read and output, and subsequently, data read from the disk is continuously output, and time This is an operation of continuously outputting a large amount of data without interruption.

Therefore, the output processing block includes a demodulation / PI
Different from the block number “n” at which the writing process of the corrected data starts, another block number (in this case, 3
Processing is started from "n-3" before the block. Since the data stored in the RAM 110 is error-corrected data, it can be continuously output up to the processing block “n” before the PO correction. After the end of the continuous output, as in the sequential operation of FIG. 4A, the following processing is performed on one block for which the previous processing has been completed according to the control of FIG. In this way, data processing can be performed without interruption, and AT
By setting the priority of API output higher than that of PO error correction, output processing that satisfies the request from the host can be performed without being affected by the error correction processing time. Also, in the case where the priority is the order of the write processing after demodulation / PI correction, the PO correction, and the ATAPI output, there is a system in which each processing guarantees access for one block within the time played from the disk. If the process performs a plurality of block processes within the above-mentioned time, continuous processing cannot be performed. However, when the ATAPI output according to the present invention has a higher priority than the PO correction, a plurality of block processes of each process can be performed.

FIG. 5 is a detailed view of the descrambling means 111 in FIG. 501 is a descrambling operation means,
Reference numeral 502 denotes a selector for switching data, and reference numeral 503 denotes a control signal from the microcomputer. Reference numeral 504 denotes input data, 505 denotes output data, and 506 denotes data after descrambling processing.
At the request of the host 113, the data to be output-processed via the ATAPI 112 is processed by the descrambling means 111. The control signal 403 of the microcomputer is applied to the data 504 read from the RAM 110 and the data 506 scrambled by the descrambling operation means 501.
Data is switched by the selector 502 according to the
05). By turning on / off the descrambling process, it is possible to output both data as input and data obtained by scrambling the input data.

Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 6 shows, in addition to the digital signal reproducing apparatus of FIG. 11, a CD signal processing means 601 and a CD-ROM for reproducing CD data.
ROMDEC 602 is added. When the read data format in the optical disc is the CD format, the read input data is transferred to the CD signal processing means 601 instead of the demodulation means 106. Therefore, demodulation and error correction of CD data are performed. Next, CD-ROMDEC 60
The data is sent to an ECC (Layered ECC) via the RAM 110 to increase the reliability of the CD-ROM data.
P and Q error correction and CD data descrambling are performed.
As a result, the CD data that has been scrambled and error corrected is stored in the RAM 110, and the A
Output via TAPI 112. At this time, the data is output through the descrambling means 111. Since the descrambling means 111 can switch the data output as shown in FIG. 5, the data is read from the RAM 110 which does not perform the processing for scrambling the main data. By selecting the data as it is output, data in CD format can be output. The microcomputer control signal 503 is generated according to the data recorded on the disc, and the descrambling is turned on / off.
By turning off, the ATAPI 112 can be shared and data in a different format can be output. In addition, in the CD format, in addition to main data, identification information such as a sector number is scrambled, which is different from the DVD format in which the identification information is not scrambled. Therefore, according to whether or not the identification information section is scrambled, the descrambling is turned on / off.
By turning it off, data output in a different format becomes possible.

Next, a third embodiment of the present invention will be described with reference to FIG. FIG. 7 shows a configuration in which a microcomputer DMA control means 701 is added to the digital signal reproducing apparatus shown in FIG.
The microcomputer DMA is operated by the microcomputer control signal 114 in a method of directly accessing the RAM 110 from the microcomputer. This can be used, for example, when storing in a memory a list having information on defective sectors found at the time of formatting a disk used for DVD-RAM reproduction. From the microcomputer, via the microcomputer DMA control means 701, the RAM 11
Data is written to 0. Therefore, the data is output via ATAPI at the request of the external host. At that time, the microcomputer DMA
Since the data recorded directly in the RAM 110 is unscrambled data, the selector 502 shown in FIG.
To select and output data that does not scramble. By generating the microcomputer control signal 503 according to the data written in the RAM 110 and turning on / off the descrambling, the microcomputer control signal 503 can be output regardless of the format of the data stored in the RAM 110.

As described above, by using the descrambler 111 capable of switching the output of the present invention, it is possible to output according to the format of the data stored in the RAM 110. After descrambling the scrambled data, the RAM 11
Since it does not return to 0, access to the RAM 110 can be reduced.

A fourth embodiment of the present invention will be described with reference to FIG. FIG. 10 shows a digital signal reproducing apparatus shown in FIG. 11 in which a PI and PO direction error correction means 1001 is used instead of the PO direction error correction means. Once the data is read from the RAM 110 where the PI error corrected data is stored,
The PI / PO error correction means 1001 once performs error correction in the PO direction. However, at low speeds, error correction is repeatedly performed on the data in the PI direction and the PO direction. Then the ATAP
Output to the host via I112. Thereby, the reliability of the output data can be improved. However, at the time of high-speed playback, it is possible to respond by outputting data after the first PO error correction without repeating the correction under the control of the microcomputer.

Next, a fifth embodiment of the present invention will be described with reference to FIG. FIG. 9 is an address map of a RAM that can be used in the digital signal reproducing device of the above embodiment. 9
01 is the entire address area of the RAM, and 902 is one ECC block. When the RAM of the present invention is described using a DRAM as an example, the DRAM is m
It has a two-dimensional array address area of (m: natural number) rows n (n: natural numbers) columns, and as a characteristic of the DRAM, data in the row direction can be read continuously in bursts. Cannot be read at high speed. Therefore, in one ECC block 902 composed of 182 bytes × 208 lines, one line = 182 bytes is divided into 64 bytes, 64 bytes, and 54 bytes and stored in separate lines on the RAM. Therefore, one line
= 1024 bytes of DRAM, 16 lines of ECC blocks are stored in RAM1
It can be stored on a row, and the data of one ECC block is RA
M Can be stored in the area of 39 rows. Therefore, data for 16 rows of ECC blocks allocated to one row on the RAM can be read at high speed, and the number of times (time) required for reading in the error correction in the column direction can be reduced.

Further, since the number of PO sequences to be simultaneously operated can be increased, unnecessary access to the RAM for reading an area where no operation is performed can be eliminated, and the number of accesses to the RAM can be reduced.

[0032]

As described above, after the input data read from the optical disk is subjected to the demodulation processing, the error correction in the row direction is performed once, and then recorded in the temporary storage means. afterwards,
Error correction in the column direction is performed, and descramble processing is performed on the error-corrected data recorded in the temporary storage means simultaneously with output. Therefore, by performing the processing at the same time according to the characteristics of the data operation, the access to the temporary storage means is constituted by the three accesses of the write processing of the row direction data, the error correction processing in the column direction, and the output processing in the row direction. Access can be reduced.

Further, by using the descrambling means 111 for turning on / off the descrambling at the time of output, it is possible to output according to the characteristics of the data stored in the temporary storage means, and to temporarily store the scrambled data. Since the data is not returned to the storage means, the number of accesses to the temporary storage means can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a digital signal reproducing apparatus according to a first embodiment of the present invention.

FIG. 2 is a diagram showing the structure of one data sector.

FIG. 3 is a 1ECC block structure diagram.

FIG. 4 is a timing chart of a block process.

FIG. 5 is a detailed view of a descrambling means.

FIG. 6 is a diagram showing a digital signal reproducing apparatus according to a second embodiment of the present invention.

FIG. 7 is a diagram showing a digital signal reproducing apparatus according to a third embodiment of the present invention.

FIG. 8 is an ECC block control operation diagram.

FIG. 9 is a RAM address map.

FIG. 10 is a diagram showing a digital signal reproducing device according to a fourth embodiment of the present invention.

FIG. 11 is a detailed view of a digital signal reproducing apparatus according to the first embodiment of the present invention.

[Explanation of symbols]

101 optical disk, 102 pickup, 103 spindle motor, 104 servo, 105 read channel, 106
Demodulation means, 107: PI direction error correction means, 108: PO direction error correction means, 109: RAM control means, 110: RAM, 111: descrambling means, 112: ATAPI, 113: host, 120: writing means, 121 ... Column direction error correction means, 122 ... output means, 20
1 ... ID, 202 ... RSV, 203 ... Main data, 204 ... EDC, 301
... 1 data sector, 302 ... PI, 303 ... PO, 501 ... descramble calculation means, 502 ... selector, 503 ... microcomputer control signal, 504 ... input data, 505 ... output data, 506 ... descrambled data, 601 ... CD Signal processing means, 602 ... CD-R
OMDEC, 701: microcomputer DMA control means, 804: RAM address, 805: 1 ECC block, 806: processing block number, 807
... The processing block number of the previous processing, 901 ... RAM address area, 902-1 ECC block, 1001 ... PI / PO error correction means.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hiroshi Nagai 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside Digital Media Development Division, Hitachi, Ltd. (72) Inventor Taku Hoshizawa 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Address F-term in Hitachi Digital Media Development Division (Reference) 5D044 BC02 CC04 DE03 DE68 DE81 DE91 FG10

Claims (16)

[Claims] 1. A sector is formed by adding ancillary data in units of h (h: natural number) bytes, scrambled in sector units, and divided into rows in i (i: natural number) byte units.
j (j: natural number) rows are collected to form an i × j matrix, a first error correction code is added in column units, and a second
A digital signal reproducing apparatus that forms block data by adding an error correction code of the above and reproduces a medium on which data is modulated and recorded, demodulating the recording data for each row according to a modulation rule, Means for correcting the error by the correction code and then writing to the temporary storage means, storage means for temporarily storing data,
Means for reading the error-corrected data by the second correction code in the temporary storage means, performing a correction operation in accordance with the first correction code, replacing the error data with the corrected data, and correcting the error-corrected data in the temporary storage means. Digital signal reproducing apparatus comprising output means for scrambling and outputting the data of FIG. 2. The writing means includes means for modulating recording data in accordance with a modulation rule, and means for correcting an error using a second correction code, wherein the means for correcting an error using the second error correction code includes a demodulation means. A second temporary storage unit for temporarily storing the processed data, wherein the second temporary storage unit performs an error correction process on one row of the block data according to a second correction code. 2. The digital signal reproducing apparatus according to claim 1, wherein the digital signal reproducing apparatus has a capacity equal to the amount of data to be demodulated in a required processing time t (t: natural number) in units of rows. 3. A sector is formed by adding data to the data in units of h (h: natural number) bytes, scrambled in sector units, and block data is formed by adding an error correction code to the data. A digital signal reproducing apparatus for reproducing a medium on which modulated data is recorded, a means for demodulating the recording data, a means for correcting an error by an error correction code, and a temporary storing means for temporarily storing data. A digital signal reproducing apparatus comprising output means for controlling data output to a bus to which a plurality of input / output devices can be connected, wherein descrambling for scrambling the data between the temporary storage means and the output means A digital signal reproducing apparatus characterized by comprising means. 4. The descrambling means according to claim 3,
A digital signal playback device that performs descramble arithmetic processing only when outputting to the bus. 5. A digital signal reproducing apparatus comprising means for descrambling output data read from a medium according to claim 3 and recorded in a temporary storage means, wherein the descrambling means performs a descrambling process. A digital signal reproducing apparatus comprising: a scramble calculation means; and a selector for switching between input data and output data of the descrambling calculation means. 6. A descrambling means comprising a descrambling operation means and a data switching selector according to claim 5, wherein said data switching selector switches according to the type of recording medium. 7. A descrambling means comprising a descrambling operation means and a data switching selector according to claim 6, wherein the data recorded on the recording medium is an identification code converted into data in units of h (h: natural number) bytes. , A data switching selector is switched according to whether the identification code is scrambled or not. 8. A plurality of blocks (h: natural number) which are added with first and second error correction codes to byte data to form block data, and access a temporary storage means of a means for temporarily storing the block data. A component for writing error-corrected data to the temporary storage means according to a second correction code, and a first correction code for the data recorded in the temporary storage means. And a means for outputting data from said temporary storage means, on which error-corrected data is recorded, to a bus to which a plurality of input / output devices can be connected. In a digital signal reproducing apparatus having control means for controlling access, said control means controls each access in a priority order, and performs access when writing data to said temporary storage means. As the top priority, the priority of access of the error correction processing using the first correction code recorded in the temporary storage means,
A digital signal reproducing apparatus characterized in that the order is lower than the order of access at the time of data output. 9. The digital signal reproducing apparatus according to claim 8, wherein an access at the time of writing data to said temporary storage means is set to the highest priority, and a first correction code of data recorded in said temporary storage means. A digital signal reproducing apparatus characterized in that the priority of access at the time of error correction processing is higher than the priority of access at the time of data output, and the priority of access is reversed at a fixed period. 10. The digital signal reproducing apparatus according to claim 9, wherein the predetermined period is an interval in which a time for processing a required data amount can be within a required time according to a request from a bus. 11. A means for writing block data read from a medium into a temporary storage means, a means for correcting an error in the temporarily stored block data, and a means for outputting the error-corrected data to an external device. Control means for controlling access to the temporary storage means, the temporary storage means temporarily stores a plurality of block data read from the medium, and the control means stores one block of data in the medium. In a digital signal reproducing apparatus in which access to data of one block of each of writing, error correction and output within a time t (t: natural number) read out is guaranteed, the temporary storage means is provided when data output to an external device is started. If there are multiple blocks of error-corrected data stored, 1
Block writing time ≤ t, correction processing time> t, time t
If the number of block data to be output within 1 block, and no error-corrected data is stored in the temporary storage means, the writing time of one block ≦ t, the correction processing time <t,
A digital signal reproducing method, wherein the number of blocks output within a time t is one block. 12. A digital signal reproducing apparatus for reproducing data to which the first and second error correcting codes are added according to claim 1 and 2, means for correcting an error by a second correcting code, and In a digital signal reproducing apparatus including a temporary storage unit in which error-corrected data by the second correction code is recorded, the digital signal reproduction device includes both error correction units by the first and second correction codes. The means for correcting the error by the correction code not only performs the error correction according to the first correction code on the data corrected by the second correction code recorded in the temporary storage means, but also performs the first or second correction again. No. 2
A digital signal reproducing apparatus and a reproducing method, wherein error correction can be performed in accordance with the correction code of (1), and the number of repetitions of the error correction is switched according to the reproduction rate. 13. A digital signal reproducing apparatus comprising a temporary storage unit in which block data having a matrix structure according to claim 1 is recorded, wherein each row of the recording block is divided into m (m: natural number) byte units. The temporary storage means are arranged in different rows, and the data in the column direction of the recording block is stored in one row of the temporary storage means by n.
(N: natural number) A digital signal reproduction device characterized by being arranged. 14. A digital signal reproducing apparatus comprising a temporary storage unit in which block data having a matrix structure according to claim 13 is recorded, wherein said block data is divided in units of h (h: natural number) bytes. And i (i: natural number) in the row direction and j in the column direction
An (i: j) matrix is composed of (j: natural number) cells, and the arrangement of rows and columns of the matrix structure is switched to j × i
A digital signal reproducing device arranged in a temporary storage means in a matrix. 15. A digital signal reproducing apparatus according to claim 14, wherein the cell has a unit size in which k (k: natural number) cells can be arranged in one row of a temporary storage means capable of high-speed reading in a row direction. . 16. A sector is formed by adding an error correction code and an identification code to data of h (h: natural number) bytes, scrambling is performed in sector units, a synchronization signal is added, and another error correction code is added. Are added to form block data, and further, a synchronization signal is added to the medium 1 which is modulated and recorded, and an identification code is added to data of h (h: natural number) bytes to form a sector. A digital signal reproducing apparatus for scrambling only main data in units, adding an error correction code to form block data, adding a synchronization signal, and reading data from a medium 2 which is modulated and recorded. , Demodulation, error correction,
Medium 1 signal processing means for performing descrambling processing, and medium 2
A medium 2 signal processing means for performing demodulation and error correction on the
Temporary storage means for temporarily storing data processed by each of the signal processing means, descrambling means for scrambling data according to the scrambling rule of the medium 2,
In a digital signal reproducing apparatus having output means for controlling output to the bus, the type of the medium is determined, the input to the medium 1 signal processing means and the input to the medium 2 signal processing means are switched, and read from the medium 1. The data is input to the medium 1 signal processing unit, and demodulated, error corrected, and descrambled according to the characteristics of the data of the medium 1 in the signal processing unit and recorded in the temporary storage unit, and recorded in the temporary storage unit. The descrambled data is output as it is, and the data read from the medium 2 is input to the medium 2 signal processing means, and the medium 2 signal processing means performs demodulation and error correction according to the characteristics of the data of the medium 2. A digital signal reproducing apparatus for outputting the error-corrected data recorded in the temporary storage means after performing descrambling processing by the descrambling means. And playback method.