JP2001222408A - Processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a processor equipped with a function for performing an exclusive arithmetic instruction for accelerating metric calculation in viterbi decoding processing. SOLUTION: A subtracter 116 for scaling metric and an adder 117 for calculating a scaling value and latches 109 and 110 for holding two data to be inputted to an arithmetic unit 108 for performing an MAX instruction are added to the arithmetic unit 108. The inputs of the two latches 109 and 110 and the subtracter 116 and the adder 17 are connected through as selector 113, and the selector 113 is controlled according to the arithmetic result of the MAX instruction. Thus, it is possible to process the calculation of a scaling value following metric calculation with scaling, and to realize the high speed and more efficient arithmetic operation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a portable telephone terminal such as a digital cellular phone, and more particularly to an operation instruction of a low power consumption programmable processor required for realizing the terminal with low power consumption.

[0002]

2. Description of the Related Art In a radio communication system, a portable terminal performs demodulation and equalization processing such as receiving a modulated wave transmitted from a base station and reproducing a modulated signal. In wireless communication, a bit error occurs in received data due to the influence of noise on a transmission path. Therefore, as demodulation and equalization processing,
A maximum likelihood estimation method (Viterbi decoding) for estimating transmission data from a received wave is usually used. In particular, a programmable digital signal processor (hereinafter abbreviated as DSP) used in a portable terminal is required to process Viterbi decoding at high speed. Specifically, metric calculation is processed at high speed. Is to realize the operation instruction. Thus, the metric calculation process will be described with a specific example. For details of Viterbi decoding, for example,
"Mobile Communications" (Ohm, 1998, 269-2
82).

FIG. 2 shows a trellis diagram of four states as an example. In general, the number of states is 2 ⁿ (2 n
In the following, a case where n = 2, that is, the number of states is 4, will be described.

In order to estimate a reception sequence, it is necessary to calculate a metric for each state at each time. Here, the metric of the state (0,0) at time T-1 is Pt
Assuming that the metric of -1 (0, 0) and the state (0, 1) is Pt-1 (0, 1), and the branch metrics are b0 and b1 as shown in FIG. The metric P (0,0) in the state (0,0) is represented by Expression (1).

Pt (0,0) = MAX {Pt-1 (0,0) + b0, Pt-1 (0,1) + b1} (1) Here, MAX means two values in {}. It means to compare and take the larger value. Hereinafter, Kt0
(0,0) = Pt-1 (0,0) + b0 and Kt0 (0,1) = Pt-1 (0,1) + b1.

Normally, equation (1) is called metric calculation. Since the metric is the cumulative value of the branch metric values, it can be seen that the metric increases as the time advances. Therefore, when performing the metric calculation of the above equation (1), it is necessary to perform scaling so that the metric value does not overflow. The scaling value St-1 is represented by the following equation.

St-1 = (Pt-1 (0,0) + Pt-1 (0,1) + Pt-1 (1,0) + Pt-1 (1,1)) / 4 (2) That is, St- 1 is the average of all the metrics at time T-1, and the metric calculation with scaling can be expressed by the following equation (3).

Pt (0,0) = MAX ｛Kt (0,0), Kt (0,1)｝ − St−1 (3) That is, in the metric calculation with scaling, in addition to the MAX operation, ( It is necessary to perform a process of subtracting a scaling value from a metric value as in Expression (3) and a process of calculating a scaling value as in Expression (2).

In summary, the metric P at time T
In the metric calculation with scaling for calculating t (0,0), inputs are metric candidates Kt (0,0), Kt (0,1) and S
t-1, and the outputs are the metrics Pt (0,0) and St of each state. Other metrics Pt (0,
Similar calculations are performed for 1), Pt (1,0), and Pt (1,1).

The metric calculation of the above formulas (2) and (3) can be realized by using a comparison operation instruction or the like provided in the microprocessor. As an example of more efficient execution, signal processing is executed at high speed. A digital signal processor (DSP), which is a processor, has a comparison / selection instruction for comparing the magnitude of data and selecting a larger value. The register storing the data to be compared is, for example,
The first register and the second register are used, and the operation result is the second register.
Specifically, this MAX instruction first executes an operation of subtracting the value of the second register from the value of the first register. When the operation result is positive, Performs an operation of newly storing the value of the first register in the second register, and not updating the value of the second register when the operation result is negative.

Conventionally, to calculate the value of the metric Pt in the equation (3), first, a metric candidate Kt (0,0) is stored in a first register, and Kt (0,1) is stored in a second register. Stored in
Perform the above MAX instruction. Next, a process of subtracting the scaling value St-1 from the maximum value held in the second register is performed. For example, the scaling value St-1
Is stored in the third register, and the metric Pt (i, j) subjected to the scaling process is stored in the fourth register.

Next, the value of the metric stored in the fourth register is added to the fifth register in order to calculate the scaling value St of the equation (2). Note that the scaling values of the fifth register and the third register need to keep their values until the metric calculation in all states is completed, and the value of the metric held in the fourth register is Since it is used for the metric calculation at the time T + 1, it needs to be stored in the memory. That is, the MAX instruction is executed for calculating the metric, the subtraction instruction is executed for scaling, and the addition instruction is executed for calculating the scaling value. Each instruction is executed in one cycle. As it is performed, the metric calculation with scaling takes a minimum of three cycles per state.

As described above, the minimum number of registers used for metric calculation with scaling is 5, but the number of registers that can be used for metric calculation is actually smaller than 5, that is, in an actual program, the metric Pt There is a problem that the calculation and the calculation of the scaling value St cannot be performed simultaneously. Specifically, in an actual program, metrics of all states at the time T are calculated, and these values are used for the metric calculation at the time T + 1, so that the metrics of all the states are stored in the memory.

When calculating the scaling value St, the metric value stored in the memory is used as the metric value used for calculating the scaling value St. Therefore, the metric value is transferred from the memory to the register, and the average of all the metrics is calculated. As described above, if the number of registers that can be used for calculation is small, there is a problem in that processing for data transfer instructions is unnecessarily performed.

[0015]

SUMMARY OF THE INVENTION The present invention has been made in view of such a problem, and a processor is provided with a function of executing a dedicated operation instruction for eliminating the redundancy of the operation as described above. It is another object of the present invention to provide a processor that improves the efficiency of metric calculation with scaling.

[0016]

For example, when the number of states is 4, the scaling value S calculated at time T is calculated.
t is St = (Pt (0,0) + Pt (0,1) + Pt (1,0) + Pt (1,1)) / 4 (4) Further, St = (MAX ｛Kt0 (0, 0), Kt0 (0,1) ＋ + MAX ｛Kt1 (0,0), Kt1 (0,1)｝ + MAX ｛Kt0 (1,0), Kt0 (1,1)｝ + MAX ｛Kt1 (1 , 0), Kt1 (1,1)｝) / 4-St-1 (5). The terms other than St-1 in the equation (5) are the output of the MAX instruction, and coincide with the input of the scaling calculation in the equation (3).

Focusing on this point, a calculator for executing the MAX instruction includes a subtractor for scaling the metric,
An adder for calculating a scaling value and a latch for holding two data input to an arithmetic unit for executing a MAX instruction are added. The inputs of the two latches and the subtractor and the adder are connected via a selector, and the selector is controlled by the sign information of the operation result of the MAX instruction.

A dedicated register is connected to the subtracter, and an output of the dedicated register is connected to an input of the subtractor. The output of the subtractor is connected to the input of a general-purpose register so that the value of the metric after scaling is held in the register.

The adder for calculating the scaling value is connected to another dedicated register. The output of the dedicated register is connected to the input of the adder, and the output of the adder is held in the dedicated register.

According to a specific configuration of the present invention, first and second latches for holding first and second data output from the first register, respectively, and first and second latches are provided. An arithmetic and logic unit having data as input, a first or second
A data generation circuit that generates data related to a metric with scaling by using an output of the latch as an input,
The data generation circuit includes a second register for holding third data, a third register for holding fourth data, a first or second data, and a third data. And a adder for calculating a scaling value by adding the first or second data to the fourth data. provide.

Further, according to the present invention, in the above configuration, an output of the first latch or the second latch is connected to an input of the data generation circuit;
Is connected to the input of the subtractor, the output of the third register is connected to the input of the adder,
The output of the subtracter is connected to the input of the first register, and the output of the adder is connected to the input of the third register.

Further, according to the above configuration of the present invention,
The arithmetic and logic unit calculates the second data from the first data.
If the sign information of the operation result executed by the arithmetic and logic unit is positive,
The output of the first latch is connected to the input of the data generation circuit, and if the sign information of the operation result executed by the arithmetic and logic unit is negative, the output of the second latch is output to the data generation circuit. The subtractor and the adder are connected to an input of a circuit, and are configured to execute an operation at the same time.

[0023]

Next, an embodiment of the present invention will be described with reference to FIG.

FIG. 1 is a block diagram showing an embodiment of a processor having a dedicated operation instruction for executing a metric calculation with scaling according to the present invention. Processor 10
0 indicates a program memory 101 in which instructions for performing processing are stored, a data memory 102 in which data necessary for performing operations are stored, and an arithmetic processing circuit 118
Are connected by a data bus 103 and an address bus 104.

The arithmetic processing circuit 118 reads an instruction stored at an address designated by the program counter 105 from the program memory 101, decodes the instruction and sends a signal to the control circuit 106. ALU 108 for performing arithmetic and logical operations, latches 109 and 110 for storing two inputs of the ALU 108, a plurality of general-purpose registers 111 for storing data transferred from the data memory 102, and a dedicated operation for performing metric calculation with scaling Circuit 112
And selectors 113, 114, 115 and 121. The dedicated operation circuit 112 includes an adder 117, a subtractor 116, and dedicated registers 119 and 120.

The general-purpose register 111 includes a data bus 103
And stores the data transferred from the data memory 102. The data held in the general-purpose register 111 is output to the data bus 103 and stored in the data memory 102.

ALU 108 has two inputs, which are connected to the output of general purpose register 111. Also, A
The LU 108 outputs data of the operation result and code information a of the operation result. The operation result data output from the ALU is output to the general-purpose register 111. Code information a is
Output to selector 113.

The latches 109 and 110 hold the input data of the ALU 108. The output of the latch is input to the dedicated arithmetic circuit 112 via the selector 113. The selector 113 connects the output of the latch 109 or 110 with the input of the subtractor 116 and the adder 117 according to the control signal a. Specifically, when the control signal a is 0,
The latch 109 is connected, and when the control signal a is 1, the latch 110 is connected.

The dedicated registers 119 and 120 are connected to the data bus 103 and store the data transferred from the data memory 102. Also, the dedicated register 111
Is output to the data bus 103 and stored in the data memory 102.

The subtractor 116 has two inputs, one of which is connected to the output of the dedicated register 119, and the other of which is connected to the selector 113. ALU1
If the sign information of the operation result in 08 is 1, the data stored in the latch 109 and the dedicated register 119 is output to the subtractor 116, and the operation is executed. Also, A
When the sign information of the operation result in the LU 108 is 0, the data stored in the latch 110 and the dedicated register 119 is output to the subtractor 116, and the operation is executed.

The adder 117 has two inputs, one of which is connected to the output of the dedicated register 120, and the other of which is connected to the selector 113. ALU1
When the sign information of the operation result in 08 is 1, the data stored in the latch 109 and the dedicated register 120 is output to the adder 117, and the operation is executed. Also, A
When the sign information of the operation result in the LU 108 is 0, the data stored in the latch 110 and the dedicated register 120 is output to the adder 117, and the operation is executed.

Next, the operation of the operation instruction for performing the metric calculation with scaling will be described. For example, the operation will be described with this operation instruction as SMAX R0, R1.
Here, R0 and R1 are designated source operands of the general-purpose register 110. First, in the instruction fetch, the code circuit 107 decodes the SMAX instruction, and the control circuit 106 having received the decoding result outputs the control signal c to the selector 11.
5 and sends the control signal f to the ALU 108.

The selector 115 connects the outputs of the general purpose registers R0 and R1 to the input of the ALU 108. The data stored in general-purpose register R0 is latch 1
09, and the data stored in the general-purpose register R1 is stored in the latch 110. The ALU 108 subtracts the data in the general-purpose register R1 from the data in the general-purpose register R0, and outputs the sign information a resulting from the subtraction to the selector 121.

When the code information a is 0, the selector 121 outputs the output of the latch 109 to the subtractor 116 and the adder 117.
Connect to the input of. When the code information a is 1, the selector 121 connects the output of the latch 110 to the inputs of the subtractor 116 and the adder 117.

The subtractor 116 converts the data held in the latch 109 or 110 into the special register 11.
9 is subtracted, and the output of the subtractor 116 is stored in the general-purpose register R1.

The adder 117 is provided between the data held in the latch 109 or the latch 110 and the dedicated register 120.
And the output of the adder 117 is stored in the dedicated register 120.

The ALU 108 compares the values of the general-purpose registers R0 and R1 with each other.
7 is determined. The subtractor 116 and the adder 117 that have received the input data execute the operation at the same time, and the operation result is held in the general-purpose register R1 and the dedicated register 120. The ALU 108 includes a subtractor 116 and an adder 117
It is possible to perform another operation at the same time as the operation of (A) is performed. Further, the operation result of the ALU 108, the operation result of the subtractor 116, and the operation result of the adder 117 Is transferred to the register.

FIG. 3 shows a processing flow of metric calculation with scaling when the number of states is four. Processes 302, 303, and 304 are performed for each state, and are repeated four times because the number of states is 4 in this example. Steps 301, 305, and 306 are executed only once at time T. Hereinafter, the processing of the metric calculation with scaling at the time T will be described.

A process 301 is an initialization process, in which St is set to 0.
Set to. St is data stored in the dedicated register 120 of FIG. State-Count is a counter, and is data stored in the general-purpose register R2.

Next, a process 302 is a process for calculating a metric in the state (0, 0). First, the branch metric
b0 and b1 are calculated, and two metric candidates Kt0 (0,0) = Pt−
1 (0,0) + b0 and Kt0 (0,1) = Pt-1 (0,1) + b1 are calculated.

Next, the metric candidate Kt0 (0,0) is stored in the general-purpose register R0.
1) is stored in the general-purpose register R1, and the SMAX instruction is executed. For example, assuming that Kt0 (0,1)> Kt1 (0,1), the ALU 108 sends the control signal a = 0 to the selector 113.
Is output. The data stored in the latch 109, that is, Kt0 (0,1), is input to the subtractor 116 and the adder 117, and executes an operation.

The ALU 108 performs the operation of the process 303 at the same time as the operation of the subtractor 116 and the adder 117.

The above processes 302 and 303 are repeatedly executed four times. As a result, the metric values Pt (0,0), Pt (0,1), Pt (1,0), Pt (1) of all the states at the time T are obtained.
(1, 1) and a scaling value St are calculated. However, the metric values of all states are stored in the memory, and the scaling value St is stored in the dedicated register 120.

The process 305 is a process for calculating a scaling value. The data held in the dedicated register 120 is expressed as MAX ｛Kt0 (0,0), Kt0 (0,1)｝ + MAX ｛Kt1 (0,
0), Kt1 (0,1) ＋ + MAX ｛Kt0 (1,0), Kt0 (1,1)｝
+ MAX {Kt1 (1,0), Kt1 (1,1)}. First, the dedicated register 120 and the dedicated register 11
9 is transferred to the general-purpose registers R4 and R5. Next, the ALU 108
4 is shifted by two bits to the right.

Next, the ALU 108 stores the data of R4 and R5.
Is subtracted with the data of (1) and the operation result is stored in R4.
Here, since the data of R4 is the scaling value St + 1 at the time T + 1, the data of R4 is stored in the dedicated register 119.
And the calculation of the metric with scaling at the time T ends.

As described above, the arithmetic instruction of the present invention is configured so that the arithmetic operation is first performed by the ALU 108 and then the dedicated arithmetic unit 112 is operated. And the processing is performed in two cycles, so that the efficiency of the operation is higher than in the past. Further, the ALU 108 can execute another operation instruction at the same time as the operation of the dedicated operation unit 112. The dedicated arithmetic circuit mainly includes a subtractor, an adder, and a register, so that the scale of a newly added circuit is small.

[0047]

According to the present invention, the calculation of the scaling value can be processed following the calculation of the metric with scaling, and a high-speed and high-efficiency processor can be realized. In particular, the present invention is effective in a DSP used in a cellular phone terminal such as a digital cellular phone.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an embodiment of a processor having a dedicated operation instruction according to the present invention.

FIG. 2 is a trellis diagram in the case of an example having four states

FIG. 3 is a diagram showing a processing flow of metric calculation with scaling in the case of an example having four states.

[Explanation of symbols]

100: Processor, 101: Program memory, 102: Data memory, 103: Data bus, 104: Address bus,
105 ... program counter, 106 ... control circuit, 107 ... instruction fetch decode circuit, 108 ... ALU, 109 ... latch, 110 ... latch, 111 ... general purpose register, 112 ... dedicated arithmetic circuit, 113 ... selector, 114 ... selector, 115 ... Selector, 116 ... subtractor, 117 ... adder, 118 ... arithmetic processing circuit, 119 ... dedicated register, 120 ... dedicated register, 121 ...
selector.

Claims (5)

[Claims] A first register for holding first and second data output from a first register, respectively;
, An arithmetic and logic unit that receives the first and second data as inputs, and a data generation circuit that receives, as an input, the output of the first or second latch and generates data related to a metric with scaling. And the data generation circuit has a second register for holding third data consisting of a plurality of bits, and a third register for holding fourth data consisting of a plurality of bits. , The first
Alternatively, a subtractor for scaling a metric by subtracting the second data and the third data, and calculating a scaling value by adding the first or second data to the fourth data A processor comprising: 2. An output of the first latch or the second latch is connected to an input of the data generation circuit, and
The output of the second register is connected to the input of the subtractor, the output of the third register is connected to the input of the adder, and the output of the subtractor is connected to the input of the first register. 2. The processor according to claim 1, wherein an output of said adder is connected to an input of said third register. 3. The arithmetic and logic unit executes a subtraction operation of subtracting the second data from the first data, and when the sign information of the operation result executed by the arithmetic and logic unit is positive. The output of the first latch is connected to the input of the data generation circuit, and if the sign information of the operation result executed by the arithmetic and logic unit is negative, the output of the second latch is 2. The processor according to claim 1, wherein the processor is connected to an input of the data generation circuit, and the subtractor and the adder are configured to execute an operation at the same time. 4. An arithmetic unit for executing a MAX instruction of a metric operation, a subtractor for scaling a metric,
An adder for calculating a scaling value; and latch means for holding two data input to the arithmetic unit. The latch means is connected to the inputs of the subtractor and the adder via a selector. A processor characterized in that the selector is controlled by code information of a calculation result of the MAX instruction. 5. A digital signal processor for performing demodulation and equalization processing using a maximum likelihood estimation method for estimating transmitted data from received data.
In the signal processor, a dedicated operation circuit for performing a metric operation with scaling is provided, and the dedicated operation circuit has a subtractor for scaling the metric and an adder for calculating a scaling value. , Wherein the subtractor and the adder are configured to execute an operation in parallel.