JP2001218173A - Circuit and method for converting sampling frequency - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a sampling frequency converting circuit by a simple circuit configuration. SOLUTION: The circuit is provided with a count part 1 for permitting a number as a count maximum value, which is obtained by dividing a pixel number S2 in a horizontal effective video period in the case of sampling by the second sampling frequency (or a pixel number H2 in a horizontal scanning period) by the common divisor of the pixel number S2 (or H2) and of a pixel number in a horizontal effective video period (or horizontal scanning period) in the case of sampling by the first sampling frequency, and for repeatedly performing counting to the count maximum value, with a decoding signal generating part 4 for generating a decoding signal (e) corresponding to the count value (d) by the count part 1 and a digital filter part 2 which is provided with a plurality of digital filters to process a digital picture data signal (b) which is sampled by the first sampling frequency by the digital filter selected in accordance with the decoding signal (e) and to convert the digital picture data signal (b) into a digital picture data signal (g) which is sampled by the second sampling frequency.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sampling frequency conversion circuit for converting digital image data sampled at a first sampling frequency to digital image data sampled at a second sampling frequency. The present invention relates to a generalized frequency conversion method.

[0002]

2. Description of the Related Art When digital signal processing becomes widespread, it may be necessary to connect systems having different sampling frequencies. The principle method is to return to an analog signal once and resample at a new frequency.However, there are problems such as noise mixing in the analog section and accumulation of quantization noise. There is a demand for the development of a technology for converting the digitized frequency.

[0003] At present, digital equipment for studios has a composite system of color composite signals in many cases, analog equipment is mainstream, and it is mixed with digital system. In the composite method, the sampling frequency is the color subcarrier frequency of 3.
14.3 [MHz], which is four times 58 [MHz], is often used.

On the other hand, when shooting with a video camera,
This is a component signal that is divided into a color signal and a luminance signal. Video recording is also better when recorded with components. In addition, satellite and cable digital broadcasting and DV
When digitizing a video signal from a D player or the like, the amount of data becomes enormous, so MPEG that compresses the transmission band
A scheme has been introduced. To standardize the format of the component signal and the digital signal in these digital video devices, a sampling frequency of 13.5 [MH]
z] is adopted.

Therefore, a technique for connecting systems having different sampling frequencies is required in order to handle the digitized video signal not only in video recording but also in broadcasting station equipment as standard.

FIG. 14 is a diagram showing a conventional sampling frequency conversion circuit, for example, a sampling frequency conversion circuit disclosed in Japanese Patent Application Laid-Open No. H11-27096. In FIG. 14, 14 is a counter, 15 is a polynomial interpolation operation unit, 16 is a linear interpolation operation unit A, 17 is a linear interpolation operation unit B, 18 is a delay unit, 19 is a buffer unit, and t, u, and v are transmission sides, respectively. , A horizontal signal, a luminance signal input, and a color signal input, w represents a control signal, and x and y represent a luminance signal output and a color signal output, respectively.

Next, the operation of the conventional sampling frequency conversion circuit will be described. The luminance signal input u and the chrominance signal input v of the digital image data sampled at the first sampling frequency are input to the polynomial interpolation operation unit 15 and the delay unit 18. The polynomial interpolation calculator 15 approximates the first and second sampling frequencies with a simple integer ratio. From this integer ratio the first
A polynomial interpolation operation is performed on the interpolated value at the midpoint of the sampling point at the sampling frequency of. From the signal having this value and the original signal from the delay unit 18, the linear interpolation calculation unit A16 performs a linear interpolation calculation on the interpolation value of the sampling point close to the second sampling frequency.
A signal having this value is written to the buffer unit 19.
The read control unit in the buffer unit 19 reads the signal of the interpolated value of the sampling point close to the second sampling frequency in synchronization with the second sampling frequency while the writing is not being performed. . As described above, digital image data sampled at the first sampling frequency is converted into digital image data sampled at the second sampling frequency.

[0008]

The conventional sampling frequency conversion circuit is configured as described above. To convert digital image data from a first sampling frequency to a second sampling frequency, By dividing the input signal into a plurality of stages based on a simple integer ratio of two sampling frequencies and performing multipoint interpolation, an interpolation value of a point closest to the sampling point of the frequency after conversion is obtained. The sampling frequency is read out in synchronization with the sampling frequency to realize conversion of the sampling frequency. As described above, in the conventional sampling frequency conversion circuit, since the input signal is divided into a plurality of stages and multipoint interpolation is performed, there is a problem that the filter configuration in the interpolation calculation becomes complicated.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems.
Is to realize, with a simple circuit configuration, a sampling frequency conversion circuit that converts digital image data sampled at the second sampling frequency into digital image data sampled at the second sampling frequency.

A second object of the present invention is to provide a pixel arrangement of digital image data sampled at a second sampling frequency with respect to a pixel arrangement of digital image data sampled at a first sampling frequency. An object of the present invention is to provide a sampling frequency conversion circuit capable of correcting an appropriate arrangement when a start position is shifted.

A third object of the present invention is to convert digital image data sampled at a first sampling frequency into digital image data sampled at a second sampling frequency, Is to obtain a sampling frequency conversion method for converting digital image data sampled at a sampling frequency of? Into digital image data sampled at an original first sampling frequency.

[0012]

According to a first aspect of the present invention, there is provided a sampling frequency conversion circuit for sampling a first digital image data sampled at a first sampling frequency at a second sampling frequency. A sampling frequency conversion circuit for converting the image data into the second digital image data, the number of pixels in a horizontal effective video period when sampling is performed at the first sampling frequency, and sampling at the second sampling frequency. The maximum count is a value obtained by dividing the number of pixels S2 by a common divisor with the number of pixels S2 in the horizontal effective video period in the case where the horizontal scanning is performed, or the horizontal scanning in the case where the sampling is performed at the first sampling frequency. A count maximum value is obtained by dividing the number of pixels H2 by a common divisor of the number of pixels in the period and the number of pixels H2 in the horizontal scanning period when sampling is performed at the second sampling frequency. A mosquito that counts repeatedly And cement means, for each operation clock,
Means for generating a first control signal for designating processing by a digital filter in accordance with the count value of the counting means; and a plurality of digital filters which are selected in accordance with the first control signal. A conversion unit configured to convert the first digital image data into the second digital image data by processing the first digital image data with a filter.

The sampling frequency conversion circuit according to claim 2 of the present invention monitors the pixel arrangement of the second digital image data with respect to the pixel arrangement of the first digital image data, and monitors the pixel arrangement of the second digital image data. If the start position is shifted, the unit is further provided with a means for correcting to an appropriate pixel arrangement.

According to a third aspect of the present invention, there is provided the sampling frequency conversion method, wherein the first digital image data sampled at the first sampling frequency is converted to the second digital image data sampled at the second sampling frequency. A sample that converts the digital image data into digital image data and converts the second digital image data or the signal-processed second digital image data into digital image data sampled at the original first sampling frequency [A] In the first sampling frequency conversion circuit, the number of pixels in a horizontal effective video period when sampling is performed at the first sampling frequency and the second sampling The number of pixels S2 in the horizontal effective video period when sampled by frequency
The maximum count is a number obtained by dividing the number of pixels S2 by a common divisor of the following, or the number of pixels in the horizontal scanning period when sampling is performed at the first sampling frequency and the second sampling frequency A step of counting the number obtained by dividing the number of pixels H2 by a common divisor with the number of pixels H2 in the horizontal scanning period in the case of sampling as the maximum count value, and repeatedly counting up to the maximum count value; [B] In the sampling frequency conversion circuit, one of the plurality of digital filters is selected according to the count value in step [A], and the first digital image data is processed by the selected digital filter. Converting digital image data into the second digital image data;
[C] In the second sampling frequency conversion circuit, the number of pixels in the horizontal effective video period when sampling at the second sampling frequency and the horizontal count when sampling at the first sampling frequency are performed. The number obtained by dividing the number of pixels S1 by a common divisor with the number of pixels S1 in the effective video period is the maximum count value, or
The number of pixels is a common divisor of the number of pixels in the horizontal scanning period when sampled at the second sampling frequency and the number of pixels H1 in the horizontal scan period when sampled at the first sampling frequency. A step of repeatedly counting the number obtained by dividing H1 to the maximum count value, and [D]
In the second sampling frequency conversion circuit, one of a plurality of digital filters is selected according to the count value in step [C], and the second digital filter generated in step [B] by the selected digital filter is selected. Converting the second digital image data into digital image data sampled at a first sampling frequency by processing the digital image data.

In the sampling frequency conversion method according to a fourth aspect of the present invention, the first sampling frequency conversion circuit and the second sampling frequency conversion circuit are operated with the same operation clock, and the step [B] is performed. ] And [C], a core block designed to perform signal processing on digital image data sampled at a second sampling frequency is operated by the operation clock, and signal processing timing of the core block is performed. Is controlled by a control signal generated in the first sampling frequency conversion circuit, whereby the second digital image data generated in step [B] is signal-processed in the core block.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 FIG. 1 is a block diagram of a sampling frequency conversion circuit according to a first embodiment of the present invention. In FIG. 1, 1 is a counter, 2 is a digital filter, 3 is a decoder, 4 is an enable signal generator, a is an effective video period signal, and b is digital image data sampled at a first sampling frequency. Digital signal,
c is an operation clock, d is a count value, e is a decode signal, f is an enable signal, and g is a digital signal of digital image data equivalent to digital image data sampled at the second sampling frequency.

The counter unit 1 has a number of pixels in a horizontal effective image period when sampling at a first sampling frequency and a number of pixels H2 in a horizontal effective image period when sampling at a second sampling frequency. The number obtained by dividing the number of pixels H2 by the common divisor is set as the maximum count value, the count is repeated up to the maximum count value, and the count value d is output.

The digital filter section 2 has a plurality of digital filters, processes the digital image data signal b with a digital filter selected according to the decode signal e, and takes in the obtained pixel data according to the enable signal f. The digital image data signal b sampled at the first sampling frequency is converted into a digital image data signal g sampled at the second sampling frequency.

The decode section 3 generates a decode signal e for designating a process by a digital filter (for selecting one from the plurality of digital filters) according to the count value d for each clock. Further, the enable signal generator 4 generates an enable signal f for taking in the pixel data of the digital image data signal g in accordance with the count value d every clock.

Next, regarding the operation of the sampling frequency conversion circuit of FIG. 1, the digital image data signal b sampled at the sampling frequency of 13.5 [MHz] is converted to the sampling frequency of 14.3 [MHz].
Digital image data signal g sampled at 3 [MHz]
A description will be given of an example of conversion to.

The number of pixels in one horizontal effective video period is 720 (13.5 [MHz]) and 768 (14.3 [MH]).
z]), and the ratio of the number of pixels is 15:16.
The signal supplied from the digital equipment on the transmission side to the sampling frequency conversion circuit of FIG. 1 includes an effective video period signal a having a high level within the horizontal effective video period and a low level outside the horizontal effective video period, and a sampling frequency. It is a digital image data signal b of 13.5 [MHz] and a clock c which is a reference of the operation of the sampling frequency conversion circuit of FIG. The period of one pixel data of the digital image data signal b corresponds to two clock periods of the clock c.

At the same time when the effective video period signal a switches from low level to high level, the first pixel data of the digital image data signal b having a sampling frequency of 13.5 [MHz] synchronized with the clock c is sampled as shown in FIG. It is supplied to a frequency conversion circuit. Thereafter, pixel data of the digital image data signal b is sequentially supplied every two clocks of the clock c.

The counter section 1 receives the effective video period signal a
At the same time as the high level, and starts counting for each pixel data of the digital image data b. The greatest common divisor of the number of pixels 720 (13.5 [MHz]) and 768 (14.3 [MHz]) is 48, and the value obtained by dividing the number of pixels 768 by the greatest common divisor 48 is 16
Becomes Here, the counter unit 1 sets the maximum count value to 16. Therefore, the count value d starts from 1 and
.. Are incremented to 2, 3,... That is, the counter unit 1 is 1 to 16
The count value d is output for each pixel data. The counting operation from 1 to 16 is repeated 48 times, which is the greatest common divisor, in one horizontal effective video period.

The decoding unit 3 controls the digital filter unit 2 so as to select one from a plurality of digital filters of the digital filter unit 2 based on the effective video period signal a and the count value d every clock. To generate a decode signal e. At the same time, the enable signal generation unit 4 generates an enable signal f for capturing data obtained by the filtering process in the digital filter unit 2 based on the effective video period signal a and the count value d every clock. .

The digital filter section 2 selects one of a plurality of digital filters for each clock in accordance with the decode signal e generated in accordance with the count value d, and sets the sampling frequency 13.
The digital image data signal b of 5 [MHz] is filtered. In this filtering process, digital image data having a sampling frequency of 14.3 [MHz] is calculated from digital image data having a sampling frequency of 13.5 [MHz]. At the same time, the pixel data calculated every clock by the above-described filtering process is fetched according to the enable signal f, and the sampling frequency is 14.3 [MH].
z] is generated. Thus, the period of the pixel data forming the digital image data signal g is two clock periods or one clock period. The digital image data signal g has a sampling frequency of 14.
This is a digital image data signal arranged so that pixel data sampled at 3 [MHz] is synchronized with the clock c.
Accordingly, pixel data sampled at the sampling frequency of 14.3 [MHz] that constitutes the digital image data signal g is not arranged at the sampling position of the sampling frequency of 14.3 [MHz]. Therefore, strictly speaking, the sampling frequency 14.
This is a digital image data signal equivalent to a digital image data signal sampled at 3 [MHz].

As described above, the digital filter unit 2 converts the digital image data signal b having a sampling frequency of 13.5 [MHz] into a digital image data signal g having a sampling frequency of 14.3 [MHz]. This sampling frequency 14.3
The digital image data signal g of [MHz] is output from the sampling frequency conversion circuit of FIG. 1 together with the enable signal f.

When the counter 1 counts the last pixel data in one horizontal effective image period, the effective image period signal a switches from high level to low level in the next clock. This low level effective video period signal a
In response, the operation of the counter unit 1 stops. As a result, the operation of the sampling frequency conversion in the horizontal scanning period is stopped, and the signal waits for the next horizontal scanning period. Thereafter, sampling frequency conversion can be performed by repeating the above operation.

FIG. 2 is a diagram for explaining the filtering process according to the first embodiment of the present invention, and has a sampling frequency of 13.5.
FIG. 4 is a diagram illustrating a relationship between sampling positions of pixel data of digital image data of [MHz] and 14.3 [MHz].
In FIG. 2, the upper data A (open circles) is 13.5 [M
Hz], and the lower B data (black circle) indicates the sampling position of 14.3 [MHz] pixel data. The number of pixels in one horizontal effective video period is 720 (13.5 [MHz]) and 768 (14.3 [MH]
z]), and the ratio of the number of pixels is 15:16.
A0 and B0, which are the first pixels in the effective video period, have the same arrangement. In the period from A0 to A14 of the pixel of 13.5 [MHz], 16 pixels of 14.3 [MHz] correspond to B0 to B15, and the pixels of A15 and B16 are arranged in the same manner again. Assuming that the periods of A0 to A14 and B0 to B15 are one unit, the subsequent periods are repeated.

Next, the digital image data (A data) having a sampling frequency of 13.5 [MHz] is converted to a sampling frequency of 14.3 [MHz].
The filtering process for converting the data to 3 [MHz] (B data) will be described. The digital image data in one unit period includes 15 pieces of A data and 16 pieces of B data. In order to create 16 B data, 16 A data to be referred to are required.

First, in the first unit, the first A
A process of setting 0 to B0 of the same arrangement is performed, and A0 is held. This A0 is used when obtaining the next B1. B1 is obtained by operation from A0 and A1 of two adjacent pixels, and A1 is obtained.
Hold. Thereafter, the same processing is performed, and B data is sequentially obtained from two adjacent A data. Thus, the filtering process in one unit is two taps. Then, B15, which is the last data of the first unit, is obtained by calculation from A14 of the last data in the first unit and A15 of the first data of the second unit. As described above, B0 to B15 of the first unit are obtained.

Next, the second unit is subjected to the same filtering processing as that of the first unit to obtain B1.
7 to B31 are sequentially obtained. For the third and subsequent units, the same filtering process as the first unit is repeated. Thus, the sampling frequency 1
It is possible to convert 3.5 [MHz] digital image data (A data) into sampling frequency 14.3 [MHz] digital image data (B data). Note that the last pixels of the effective video period are A719 and B767, and A720 outside the effective video period is used as reference data for obtaining B767.

Next, digital image data having a sampling frequency of 13.5 [MHz] is converted to a sampling frequency of 14.3 [MHz].
The operation in the above-described filtering process for converting into digital image data will be described. FIG. 3 is a diagram in which a part of FIG. 2 is enlarged and a distance scale is added, and the sampling frequency is 14.3 [MHz] from the digital image data of the sampling frequency of 13.5 [MHz] in the first embodiment. FIG. 4 is a diagram for explaining an operation of a filtering process for obtaining digital image data. The scale shown in FIG. 3 has a sampling frequency of 13.5.
Each pixel of digital image data of [MHz] is divided into 16 parts.

The B data having a sampling frequency of 14.3 [MHz] corresponds to the sampling frequency 1 located before and after the B data.
It is determined by two adjacent A data of 3.5 [MHz] and the distance of the B data from the A data. If the weight of the A data sampled at the same position as the B data is set to 16/16, when the A data is sampled at a position left and right by one division from the B data, the weight of the A data is weighted. Is 15/16, and when the A data is sampled at a position separated from the B data by two scales to the left and right, the weight of the A data is 14/16.

From the above, since the first pixels A0 and B0 in the first unit are arranged in the same manner, the arithmetic expression for calculating B0 is B0 = (16/16) A0. Next, the weighting of A0 to B1 is 1/16
Since the weight of A1 with respect to B1 is 15/16, the arithmetic expression for calculating B1 is B1 = (1/16) A0 + (15/16) A1. Next, the weighting of A1 to B2 is 2/16
Since the weight of A2 with respect to B2 is 14/16, the arithmetic expression for calculating B2 is B2 = (2/16) A1 + (14/16) A2. Next, the weight of A2 on B3 is 3/16
Since the weight of A3 with respect to B3 is 13/16, the arithmetic expression for calculating B3 is B3 = (3/16) A2 + (13/16) A3.

[0035]

[Table 1] Table 1 shows an arithmetic expression of the filtering process according to the first embodiment of the present invention. That is, Table 1 shows the sampling frequency 13.
This is an arithmetic expression for obtaining digital image data (B data) having a sampling frequency of 14.3 [MHz] from digital image data (A data) of 5 [MHz]. Note that the calculation formulas for calculating B17 and subsequent steps are the same as the calculation formulas for B1 to B16.

FIG. 4 is an operation timing chart of the sampling frequency conversion circuit of FIG. In FIG. 4, (A) is 27 [MHz] which is a reference of the sampling frequency conversion circuit of FIG.
Clock c, (B) are digital image data signals b, with a sampling frequency of 13.5 [MHz] synchronized with clock c.
(C) is a digital image data signal (signal generated inside the digital filter unit 2) obtained by delaying the digital image data signal b by two clocks, (D) is a count value d by the counter unit 1, and (E) is a decode. The decoded signal e by the unit 3 and (F) are the calculation results by the digital filter unit 2, the (G) is the enable signal f by the enable signal generating unit 4, and the (H) is the sampling frequency 1 synchronized with the clock c.
This is a digital image data signal g of 4.3 [MHz].

In one unit, as shown in FIG. 2, 16 B data having a sampling frequency of 14.3 [MHz] are processed with respect to 15 A data having a sampling frequency of 13.5 [MHz]. There is a need. Thus, B in one unit
Since the data is one pixel larger than the A data, it is necessary to process two pieces of pixel data B during a period corresponding to a sampling frequency of 13.5 [MHz]. Therefore, as shown in FIG. 4, the frequency of the clock c which is the reference of the sampling frequency conversion circuit of FIG. 1 is 13.5 [M] which is the first sampling frequency.
Hz] or more.

The count value d of the counter unit 1 is 1 during two clock periods when A0 of the digital image data signal b is input, and is 2, 3 every two clock periods when A1, A2,. ,... 15 and the first one of two clock periods in which A15 is input
It is incremented to 16 in the clock period, reset to 1 in one clock period thereafter, and becomes 2 in two clock periods when A16 is input.

The decoding signal e by the decoding unit 3 is 1
Generated according to the count value d for each clock, and when the above-mentioned counter value d is 1, 2,.
F1,... F15. Values F0 to F1 of decode signal e
5 respectively correspond to the arithmetic expressions in Table 1, and the digital filter unit 2 selects one of the arithmetic expressions in Table 1 according to the value of the decode signal e. For example, the decoded signal e =
At the time of F1, B1 = (1/16) A0 + (15/16) A1 is selected from the arithmetic expression of Table 1.

The enable signal f generated by the enable signal generator 4 is generated in accordance with the count value d every clock, and becomes high when the count value d is incremented and reset, and the count value d is incremented or decremented. This signal is a low level when not reset.

In order to obtain digital image data having a sampling frequency of 14.3 [MHz], a sampling frequency of 1
Two adjacent pixels of 3.5 [MHz] digital image data are required. For this reason, the digital filter unit 2
The digital image data signal b is generated by delaying the digital image data signal b by two clock periods, and two adjacent pixels of the digital image data signal b are obtained at the same time. Then, the calculation result of FIG. 4 (F) is obtained for each clock by a filtering process using a calculation formula selected according to the value of the decode signal e.

At the same time, the digital filter unit 2 arranges the data of the result of the above operation according to the enable signal f. That is, the above calculation result is taken in according to the enable signal f. Although the above operation result is obtained every clock, the digital image data signal b of the sampling frequency of 13.5 [MHz] used for the operation is one pixel for every two clocks, so the above operation result is B0, B0 , B1, B1, B
2, B2,..., And the same two data are continuously obtained. However, necessary data is B0, B1, B2,..., And one of the same two data is unnecessary. Therefore, the enable signal f is a signal that alternates between a high level and a low level every other clock, and this enable signal f
For example, only when is at a high level, a digital image data signal g having a width of 2 clocks can be obtained by taking in the operation result. However, continuous pixel data of B15 and B16 is
Since the width is one clock, the enable signal f is at a high level during this period. Thereby, B15
And B16 continuous pixel data,
Sampling frequency 14.3 [MHz] synchronized with clock c
Can be obtained.

As described above, according to the first embodiment, the number obtained by dividing H2 by the common divisor of the number of pixels at the first sampling frequency and the number of pixels H2 at the second sampling frequency is set as the maximum count value. , The digital image data signal b sampled at the first sampling frequency by the digital filter corresponding to this count value, and sampled at the second sampling frequency. With the configuration for generating the digital image data signal g, a sampling frequency conversion circuit having a simple circuit configuration can be realized.

Further, since the configuration is such that the enable signal f corresponding to the pixel arrangement of the digital image data signal g synchronized with the clock c is output, a digital image data signal designed to process digital image data signals having different sampling frequencies is provided. Connecting the device to the output stage of the first sampling frequency conversion circuit having the above configuration, operating the digital device with the clock c,
Furthermore, it is possible to connect the second sampling frequency conversion circuit having the above configuration to the output stage of the digital device, thereby configuring a sampling frequency conversion system that operates with one type of clock c.

In the first embodiment, the first
Is the common divisor of the number of pixels in the horizontal effective video period when sampled at the sampling frequency and the number of pixels H2 in the horizontal effective video period when sampled at the second sampling frequency. Is the maximum count value, but the number of pixels in the horizontal scanning period when sampling at the first sampling frequency and the pixel in the horizontal scanning period when sampling at the second sampling frequency The number obtained by dividing the number of pixels S2 by a common divisor with the number S2 may be used as the maximum count value. The common divisor is not necessarily the greatest common divisor, but may be any suitable common divisor. However, by using the greatest common divisor, the number of digital filters can be minimized, and the circuit configuration can be simplified.

Embodiment 2 FIG. 5 is a block diagram showing a sampling frequency conversion circuit according to the second embodiment of the present invention. In FIG. 5, the same parts or corresponding parts as in FIG. 1 are denoted by the same reference numerals as in FIG. The sampling frequency conversion circuit of FIG. 5 has a configuration in which the pixel arrangement correction unit 5 is provided in the sampling frequency conversion circuit of the first embodiment (see FIG. 1).

The pixel arrangement correction unit 5 corrects the pixel arrangement of the digital image data signal g sampled at the second sampling frequency with respect to the pixel arrangement of the digital image data signal b sampled at the first sampling frequency. When the start position of the digital image data signal g is shifted, the pixel arrangement of the digital image data signal g is corrected to an appropriate arrangement, and the timing of the enable signal f is corrected. As described above, the sampling frequency conversion circuit according to the second embodiment includes a unit that corrects an appropriate pixel arrangement when the start position of digital image data sampled at the second sampling frequency is shifted. It is characterized by the following.

When the start position of the digital image data sampled at the second sampling frequency is not shifted, the pixel arrangement correction section 5 described above outputs the digital image data signal g input from the digital filter section 2. The enable signal f input from the enable signal generator 4 is output as it is as a digital image data signal h sampled at the second sampling frequency and an enable signal i. When the start positions of the digital image data sampled at the second sampling frequency are shifted, the corrected digital image data and the enable signal are replaced with the digital image data signal h and the enable signal i, respectively.
Output as The above digital image data signal h is
As with the digital image data signal g, the sampling frequency 1
The pixel data sampled at 4.3 [MHz] is clock c.
Is a digital image data signal arranged in synchronization with the digital image data.

FIG. 6 is a block diagram of the pixel arrangement correction unit 5 in FIG. In FIG. 6, the same or corresponding parts as those in FIG. 5 are denoted by the same reference numerals as in FIG. In FIG. 6, 6 is a pixel arrangement monitoring unit, 7 is a correction filter unit, 8 is a selector unit, 9 is a delay unit, 10 is a selector unit, j is a shift width signal, k is a shift detection signal, and m is a timing-corrected enable. The signal l is a digital signal of digital image data whose pixel arrangement has been corrected.

The pixel arrangement monitoring unit 6 monitors the pixel arrangement of the digital image data g sampled at the second sampling frequency with respect to the pixel arrangement of the digital image data b sampled at the first sampling frequency. I do. Further, when the start position of the digital image data g is shifted, the shift width is detected. Then, a shift width signal j for correcting the pixel arrangement to an appropriate one and a shift detection signal k for notifying the shift are output.

Next, the correction filter unit 7 corrects the digital image data g sampled at the second sampling frequency into an appropriate pixel arrangement based on the shift width signal j, and outputs it as digital image data t. I do. Next, the selector 8 selects either the digital image data 1 corrected to have an appropriate pixel arrangement by the correction filter 7 or the uncorrected digital image data g according to the shift detection signal k. Selects the corrected digital image data 1 and, if there is no shift, selects the uncorrected digital image data g), and samples the selected digital image data at the second sampling frequency. The digital image data is output as digital image data h which is equivalent to the digital image data and is synchronized with the clock c.

The corrected digital signal 1 is delayed in timing by the processing of the correction filter unit 7 with respect to the enable signal f. For this reason, the delay unit 9 adjusts the phase of the enable signal f and generates the enable signal m whose timing matches the corrected digital signal l.

Next, in the selector 10, the enable signal m whose timing has been corrected by the delay unit 9
And any one of the enable signals f whose timing has not been corrected is selected according to the shift detection signal k (if there is a shift, the corrected enable signal m is selected. If there is no shift, the enable signal m is corrected. Not enable signal f
Is selected), and the device that receives the digital image data signal h outputs the selected enable signal as an enable signal i for capturing the digital image data signal h.

As described above, according to the second embodiment, the pixel arrangement of the digital image data g is monitored, and the pixel arrangement correction unit 5 for correcting the pixel arrangement to an appropriate pixel arrangement is provided. Sampled digital image data signal b
When the start position of the pixel arrangement of the digital image data signal g sampled at the second sampling frequency is shifted with respect to the pixel arrangement of, the pixel arrangement of the digital image data g is corrected to an appropriate position. can do.

Embodiment 3 FIG. 7 is a block diagram of a sampling frequency conversion system according to Embodiment 3 of the present invention. In FIG. 7, the same parts or corresponding parts as in FIG. 5 are denoted by the same reference numerals as in FIG. In FIG.
11 is a sampling frequency conversion circuit A, 12 is a core block,
Reference numeral 13 denotes a sampling frequency conversion circuit B.

The sampling frequency conversion system shown in FIG.
Is converted into a digital image data signal h sampled at a second sampling frequency, the digital image data signal h is subjected to signal processing, and the signal processing is performed. Digital image data signal n
Is converted to digital image data o sampled at the original first sampling frequency.

In the sampling frequency conversion system shown in FIG. 7, the sampling frequency conversion circuit A11, the core block 12,
The effective video period signal a and the clock c are input to the sampling frequency conversion circuit B13. Therefore, the sampling frequency conversion circuit A11, the core block 12,
The sampling frequency conversion circuit B13 operates using the clock c as a basic operation clock.

The sampling frequency conversion circuit A11 converts the digital image data signal b sampled at the first sampling frequency into a digital image data signal h sampled at the second sampling frequency. The image data signal h is output to the core block 12, and the generated enable signal i is sent to the core block 12 and the sampling frequency conversion circuit B13. The digital image data signal h is a digital signal in which pixel data sampled at the second sampling frequency is arranged in synchronization with a clock c (more precisely, an enable signal i).

The core block 12 is a signal processing block designed to process digital image data sampled at the second sampling frequency. In the sampling frequency conversion system of FIG. 7, the enable signal i is input to the core block 12, and all flip-flop circuits in the core block 12 are operated according to the enable signal i. Thereby, the core block 12 can capture the pixel data of the digital image data signal h according to the enable signal i. The core block 12 processes the digital image data signal h to generate a digital image data signal n.
And sends the digital image data signal n to the sampling frequency conversion circuit B13. The digital image data signal n is, like the digital image data signal h, the second digital image data signal n.
The pixel data sampled at the sampling frequency of
This is a digital signal arranged so as to synchronize with.

The sampling frequency conversion circuit B13 outputs the digital image data signal n processed by the core block 12.
Is converted to a digital image data signal o sampled at the original first sampling frequency.

Hereinafter, in the sampling frequency conversion system shown in FIG. 7, the digital image data signal b having a sampling frequency of 13.5 [MHz] is converted into a digital image data signal h having a sampling frequency of 14.3 [MHz]. The digital image data signal h is subjected to signal processing, and the signal-processed digital image data n having a sampling frequency of 14.3 [MHz] is converted into a digital image data signal o having an original sampling frequency of 13.5 [MHz]. An example of conversion will be described. That is, a sampling frequency conversion system in which the first sampling frequency is 13.5 [MHz] and the first sampling frequency is 14.3 [MHz] will be described. In this sampling frequency conversion system, the block configuration of the sampling frequency conversion circuit A11 is the same as that of the second embodiment (FIG. 5).
Is the same as

FIG. 8 shows the sampling frequency conversion circuit B13 of FIG.
FIG. 2 is a block diagram of the configuration. 8, 21 is a counter unit, 22 is a digital filter unit, 23 is a decoding unit,
24 is an enable signal generation unit, 25 is a pixel arrangement correction unit,
26 is a delay unit, a1 is an effective video period signal obtained by delaying the effective video period signal a by the delay unit 26, i1 is an enable signal obtained by delaying the enable signal i by the delay unit 26, and q is generated by the enable signal generation unit 24. The generated enable signal, r is a decoded signal generated by the decoding unit 23, and s is a digital signal of digital image data generated by the digital filter unit 22 and sampled at the first sampling frequency.

The sampling frequency 14.3 [MHz] inputted from the core block 12 to the sampling frequency conversion circuit B13.
The digital image data signal n becomes a signal whose timing is delayed with respect to the effective video period signal a and the enable signal i by the signal processing in the core block 12. Therefore, the delay unit 26 adjusts (delays) the effective video period signal a and the enable signal i, and generates an effective video period signal a1 and an enable signal i1 that are in timing with the digital image data signal n.

The counter section 21 has a sampling frequency of 14.3.
The greatest common divisor of the number of pixels 768 in one horizontal effective video period when sampling at [MHz] and the number 720 of pixels in one horizontal effective video period when sampling at a sampling frequency of 13.5 [MHz] At 48, 15 which is the number obtained by dividing the number of pixels 720 is set as the maximum count value, 1 to 15 are repeatedly counted, and the count value p is output.

The digital filter section 22 has a plurality of digital filters, and the input sampling frequency 14.3.
The pixel data of the digital image data signal n of [MHz] is fetched according to the enable signal i1, and the decoded signal r
The digital image data signal n is processed by a digital filter selected according to the above, the obtained pixel data is fetched according to the enable signal q, and a digital image data signal composed of the fetched pixel data is generated. The digital image data signal n sampled at 0.3 [MHz] is sampled at a sampling frequency of 13.5 [MHz].
Is converted into a digital image data signal s sampled by.

The decode unit 23 generates a decode signal r for designating a process by a digital filter (for selecting one from the plurality of digital filters) in accordance with the count value p for each clock. Also,
The enable signal generator 24 generates an enable signal q for designating the pixel arrangement of the digital image data signal s at each clock.

The pixel arrangement correcting section 25 is provided in the second embodiment.
In the pixel arrangement correction unit 5 (see FIGS. 5 and 6),
This is a configuration excluding the delay unit 9 and the selector unit 10. The pixel arrangement correction unit 25 calculates the pixel arrangement of the digital image data s sampled at the first sampling frequency with respect to the pixel arrangement of the digital image data n equivalent to that sampled at the second sampling frequency. Monitoring is performed, and when the start position of the digital image data s is shifted, the pixel arrangement of the digital image data s is corrected to an appropriate arrangement.

Next, the digital image data signal b having a sampling frequency of 13.5 [MHz] is converted to a sampling frequency of 14.3 [M].
[Hz], and a digital image data signal o having an original sampling frequency of 13.5 [MHz].

FIG. 9 is a diagram for explaining the filtering process in sampling frequency conversion circuits A and B according to the third embodiment of the present invention, where sampling frequencies 13.5 [MHz] and 1
FIG. 4 is a diagram illustrating a relationship between sampling positions of pixel data of digital image data of 4.3 [MHz]. In FIG. 9, the upper data A and the lower C data (open circles) are 13.5 [MH].
z] indicates the sampling position of the pixel data, and the middle B data (black circles) indicates the sampling position of the pixel data of 14.3 [MHz]. The filtering process for converting A data to B data is performed by a sampling frequency conversion circuit A11, and the filtering process for converting B data to C data is performed by a sampling frequency conversion circuit B13.

In FIG. 9, the number of pixels in the effective video period is seven.
68 (14.3 [MHz]) and 720 (13.5
[MHz]), and the ratio of the number of pixels is 16:15. The first pixels B0 and C0 in the effective video period have the same arrangement. B0 to B1 of 14.3 [MHz] pixel
5, the 13.5 [MHz] pixel has C
Fifteen from 0 to C14 correspond, and B16 and C15 are again in the same arrangement. This B0 to B15 and C0
Assuming that the period from to C14 is one unit, the subsequent units are repeated. The last pixels of the effective video period are B767 and C719. Sampling frequency 13.
The filtering process for converting the digital image data (A data) of 5 [MHz] to the sampling frequency 14.3 [MHz] (B data) is the same as the process described in the first embodiment.

Next, the filtering process for converting digital image data (B data) having a sampling frequency of 14.3 [MHz] to the original sampling frequency of 13.5 [MHz] (C data) will be described. The digital image data in the period of one unit includes 16 B data and 1 C data.
There are five. B to refer to to make 15 C data
The data is 16 in the same unit.

First, in the first unit, the first B
A filtering process is performed in which 0 is set to C0 of the same arrangement. Next, C1 is calculated from B1 and B2 of two adjacent pixels.
Ask for. The subsequent processing is the same, except that two adjacent B
C data is sequentially obtained from the data. Thus, the filtering process in one unit is two taps. Then, C14, which is the final data of the first unit, is obtained by calculation from B14 and B15 in the first unit. Thus, C0 to C14 of the first unit are obtained.

For the second and subsequent units, the same filtering processing as that of the first unit is repeated. Thus, the sampling frequency 14.3 [MH]
z] can be converted to digital image data (C data) having the original sampling frequency of 13.5 [MHz].

Next, the digital image data having a sampling frequency of 14.3 [MHz] is converted to the original sampling frequency of 13.5 [M].
[Hz] will be described below. In FIG. 3, the interval between pixels of the B data of the sampling frequency 14.3 [MHz] is 15
If the B data is weighted based on the 15 divided distances, C data of the original sampling frequency of 13.5 [MHz] can be calculated from two adjacent B data. However, if hardware is configured in accordance with the weighting by 15 divisions, it becomes complicated. Therefore, the B data is weighted based on the approximated 16 division distances.

First, the first pixel B0 in the first unit
Since C0 and C0 are arranged in the same manner, the arithmetic expression for obtaining C0 is C0 = (16/16) B0. Next, the weight of B1 with respect to C1 is 1/16
Since the weight of B2 with respect to C1 is 15/16, the arithmetic expression for calculating C1 is C1 = (1/16) B2 + (15/16) B1. Next, the weight of B2 with respect to C2 is 2/16
Since the weight of B3 with respect to C2 is 14/16, the arithmetic expression for calculating C2 is C2 = (2/16) B3 + (14/16) B2. In this way, the arithmetic expression for obtaining the C data is obtained by moving the distance between the adjacent B data and the C data by 1/16 right and left. C3 and thereafter can also be obtained by an arithmetic expression according to the same rule. And 2
Since the first B16 and C15 in the second unit have the same arrangement again, the arithmetic expression for calculating C15 is C15 = (16/16) B16.

[0076]

[Table 2] Table 2 shows an arithmetic expression of the filtering process according to the third embodiment of the present invention. That is, Table 2 shows that sampling frequency 1
An arithmetic expression for obtaining digital image data (B data) at a sampling frequency of 14.3 [MHz] from digital image data (A data) at 3.5 [MHz];
This is an arithmetic expression for obtaining digital image data (C data) having an original sampling frequency of 13.5 [MHz] from digital image data (B data) of 3 [MHz]. Note that B17
The calculation formulas for obtaining the following are the same repetitions as the calculation formulas from B1 to B16, and the calculation formulas for obtaining the calculation after C16 are similar to the calculation formulas for C1 to C15. In addition, in an arithmetic expression for obtaining C data at a sampling frequency of 13.5 [MHz] from B data at a sampling frequency of 14.3 [MHz], a portion that does not apply to the weighting of the distance by 16 divisions occurs. Think and process.

FIG. 10 is an operation timing chart of the sampling frequency conversion circuit B13 of FIG. 8 in the third embodiment. 10A shows a sampling frequency conversion circuit B.
A clock c of 27 [MHz], which is an operation reference clock of 13, an enable signal i input from the sampling frequency conversion circuit A11, and (C) an input of the enable signal i from the sampling frequency conversion circuit A11 to the core block 12. , A digital image data signal h having a sampling frequency of 14.3 [MHz] synchronized with the clock c, (D) is an enable signal i1 by the delay unit 26, and (E) is input from the core block 12 and is synchronized with the clock c. Sampling frequency 14.3 [MH
z], the digital image data signal n, (F) is a digital image data signal (signal generated inside the digital filter unit 22) obtained by delaying the digital image data signal n by one clock, and (G) is the counter unit 21. Count value p,
(H) is a decoded signal r by the decoding unit 23, (I)
Is an operation result by the digital filter unit 22, (J) is an enable signal q by the enable signal generation unit 24,
(K) is a sampling frequency 13.5 synchronized with the clock c.
[MHz] digital image data signal o.

The count value p of the counter section 21 is 1 in four clock periods when B0 and B1 of the digital image data signal n are input, and becomes 2 every two clock periods in which B2, B3,. , 3,... 14, incremented to 15 in one clock period in which B15 is input, reset to 1 in three clock periods in which B16 and B17 are input, and reset to two in two clock periods in which B18 is input. Incremented.
As described above, the counting operation of 1 to 15 is repeated, but the period of the count value p = 1 is 4 clock periods only in the first unit of the effective video period, and 3 clock periods in the second and subsequent units. .

The decoding signal r by the decoding unit 23 is
Generated according to the count value p for each clock, and when the above-mentioned counter value p is 1, 2,.
0, F1,... F14. Decode signal r value F0
F14 respectively corresponds to the arithmetic expressions for calculating C0 to C14 in Table 2 (the arithmetic expression for C15 in Table 2 is the same as the arithmetic expression for C0), and the digital filter unit 22 outputs the value of the decode signal r. , One of the arithmetic expressions in Table 2 is selected. For example, when the decode signal r = F2, Table 2
C2 = (2/16) B3 + (14/16) B2

The enable signal q by the enable signal generator 24 is generated every clock, and becomes low level during two clock periods when B0 of the digital image data signal n is input, and is set to low level during two clock periods when B1 is input. Becomes high level during the first one clock period of
This signal repeats a low level and a high level every one clock period.

In the core block 12, the digital image data signal g is processed with an enable signal i. The digital image data signal n output from the core block 12 is a digital image data signal having a sampling frequency of 14.3 [MHz] synchronized with the clock c, like the digital image data signal g. However, the timing of the digital image data signal n is delayed by one clock period from the digital image data signal g due to signal processing in the core block 12. For this reason, the digital filter unit 22 of the sampling frequency conversion circuit B13 cannot capture the digital image data signal n with the enable signal i. Therefore, the delay unit 26 of the sampling frequency conversion circuit B13 generates an enable signal i1 obtained by delaying the enable signal i by one clock period, and inputs the enable signal i1 to the digital filter unit 22. Thus, the digital filter unit 22 can capture the input digital image data signal n according to the enable signal i1.

An operation for obtaining digital image data of the original sampling frequency of 13.5 [MHz] requires two adjacent pixels in digital image data of the sampling frequency of 14.3 [MHz]. For this reason, the digital filter unit 22 generates the digital image data signal of FIG. 10F in which the digital image data signal n is delayed by one clock period, and two adjacent pixels of the digital image data signal n are obtained at the same time. I am trying to be. Then, the calculation result of FIG. 10I is obtained for each clock by the filtering process using the calculation formula selected according to the value of the decode signal r.

At the same time, the digital filter section 22 takes in the above operation result according to the enable signal r. Thus, a digital image data signal s having a sampling frequency of 13.5 [MHz] can be obtained. The pixel arrangement of the digital image data signal s is corrected as necessary in the pixel arrangement correction unit 25, and the original sampling frequency 13.
It is output from the sampling frequency conversion circuit B13 as a digital image data signal o of 5 [MHz].

As described above, according to the third embodiment, the digital image data signal b sampled at the first sampling frequency
Is converted to a digital image data signal h sampled at the second sampling frequency, and a digital image data signal n (digital image data signal sampled at the second sampling frequency) that has been subjected to signal processing is also converted. And a sampling frequency conversion system that converts the digital image data signal o into a digital image data signal sampled at the first sampling frequency.

The first sampling frequency conversion circuit A11
By operating the core block 12 and the sampling frequency conversion circuit B13 with the same clock c and controlling the signal processing timing of the core block 12 by the enable signal i, the configuration of the sampling frequency conversion system can be further simplified. it can.

In the third embodiment, the core block 12 is configured as a one-stage flip-flop circuit for simplicity of description, but is provided between the sampling frequency conversion circuits A and B. The core block is designed to process digital image data sampled at the second sampling frequency, and is configured by a circuit operable according to a clock c and an enable signal i. I just need.

Embodiment 4 In the fourth embodiment, digital image data having a sampling frequency of 27 [MHz] is converted into digital image data having a sampling frequency of 14.3 [MHz], and digital image data having a sampling frequency of 14.3 [MHz] is converted. Will be described below. A sampling frequency conversion system for converting the digital image data having a sampling frequency of 14.3 [MHz] into digital image data having an original sampling frequency of 27 [MHz] will be described.

When digital image data sampled at a sampling frequency of 27 [MHz] is transmitted as it is, the amount of data handled becomes enormous, and the configuration of the digital filter becomes very complicated. For this reason, for a portion that becomes large or complicated during transmission, the sampling frequency is 1
Using a core block designed to process digital image data of 4.3 [MHz], digital image data of a sampling frequency of 27 [MHz] is converted to digital data of a sampling frequency of 14.3 [MHz] on the transmission side. 13. Convert the image data into image data and store the sampling frequency in the core block.
3 [MHz] digital image data is transmitted, and the sampling frequency 14.3 subjected to signal processing in the core block
In some cases, it may be more convenient to convert the digital image data of [MHz] into digital image data of a sampling frequency of 27 [MHz] on the receiving side.

The configuration of the sampling frequency conversion system of the fourth embodiment is the same as that of the sampling frequency conversion system of the third embodiment (see FIG. 7). However, a part of the internal configuration of the sampling frequency conversion circuit B is different from the sampling frequency conversion circuit B of the third embodiment (see FIG. 8).

FIG. 11 shows a sampling frequency conversion circuit B13 in the sampling frequency conversion system according to the fourth embodiment of the present invention.
FIG. 2 is a block diagram of the configuration. In FIG. 11, FIG.
The same or corresponding parts are denoted by the same reference numerals.
The sampling frequency conversion circuit B shown in FIG. 11 is different from the sampling frequency conversion circuit B shown in FIG. 8 in that the digital filter unit 22 is replaced by a digital filter unit 32 and the enable signal generation unit 24 is omitted. In FIG. 11, digital signals s and o are digital image data signals sampled at a sampling frequency of 27 [MHz].

The digital filter section 32 has a plurality of digital filters, and the input sampling frequency 14.3.
The pixel data of the digital image data signal n of [MHz] is fetched according to the enable signal i1, and the decoded signal r
The digital image data signal n is processed by a digital filter selected according to the above, and a digital image data signal composed of the obtained pixel data is generated, whereby the digital sampled at a sampling frequency of 14.3 [MHz] is obtained. The image data signal n is converted into a digital image data signal s sampled at a sampling frequency of 27 [MHz].

Next, in the sampling frequency conversion circuit A, a digital image data signal b having a sampling frequency of 27 [MHz]
Is converted into a digital image data signal h having a sampling frequency of 14.3 [MHz], and the digital image data signal n having a sampling frequency of 14.3 [MHz] processed in the core block is converted into a sampling frequency of FIG. A description will be given of a filtering process for converting the digital image data signal o into the original sampling frequency 27 [MHz] in the conversion circuit B.

FIG. 12 is a diagram for explaining the filtering process in sampling frequency conversion circuits A and B according to the fourth embodiment of the present invention, in which sampling frequencies 27 [MHz] and 1 [MHz] are used.
FIG. 4 is a diagram illustrating a relationship between sampling positions of pixel data of digital image data of 4.3 [MHz]. In FIG. 12, the upper D data and the lower E data (open circles) are 27 [MH].
z] indicates the sampling position of the pixel data, and the middle B data (black circles) indicates the sampling position of the pixel data of 14.3 [MHz]. When the first sampling frequency is 13.5 [MHz] as in the third embodiment, the number of effective pixels is 720
On the other hand, when the first sampling frequency is 27 [MHz] as in the fourth embodiment, the number of pixels referred to is doubled, and the number of effective pixels is 1440. The filtering process for converting D data to B data is performed by the sampling frequency conversion circuit A (see FIG. 5), and the filtering process for converting B data to E data is performed by the sampling frequency conversion circuit B in FIG. .

Next, digital image data (D data) having a sampling frequency of 27 [MHz] and a sampling frequency of 14.3 are used.
The sampling position of digital image data (B data) of [MHz] will be described. The first pixels D0 and B0 in the effective video period have the same arrangement. In 15 periods of D0 to D14 of the pixel of 27 [MHz], 14.3 [MH]
8] correspond to eight pixels B0 to B7, and D15 and B7
8 is again in the same arrangement. Assuming that the periods of D0 to D14 and B0 to B7 are one unit, the subsequent periods are repeated. The last pixels of the effective video period are D1439 and B767.

Next, the digital image data (B data) of the sampling frequency 14.3 [MHz] and the sampling frequency 27
The sampling position of [MHz] (E data) will be described. The first pixels B0 and E0 in the effective video period have the same arrangement. Within eight periods of B0 to B7 of the 14.3 [MHz] pixel, the 27 [MHz] pixel has E0 to E1.
4 correspond to 15 pieces, and B8 and E15 are again arranged in the same manner. Assuming that the periods from B0 to B7 and E0 to E14 are one unit, the subsequent periods are repeated. The last pixel of the effective video period is B767
And E1439, and B768 is reference data for obtaining E1439.

First, digital image data (D data) having a sampling frequency of 27 [MHz] is converted to a sampling frequency of 14.3.
The filtering process for converting into [MHz] digital image data (B data) will be described. In the first unit, a filtering process is performed in which the first D0 is set to B0 having the same arrangement. Next, D1 and D2 of two adjacent pixels
To calculate B1 from the calculation. Thereafter, the same processing is performed, and B data is sequentially obtained from two adjacent D data. Thus, the filtering process in one unit is two taps. Then, D1 in the first unit
B7, which is the final data of the first unit, is obtained from 3 and D14 by calculation. Thus, B0 to B7 of the first unit are obtained. For the second and subsequent units, the same filtering process as in the first unit is repeated. Thus, the sampling frequency 27
[MHz] digital image data (D data) can be converted to sampling frequency 14.3 [MHz] digital image data (B data).

Next, a filtering process for converting digital image data (B data) having a sampling frequency of 14.3 [MHz] into original digital image data (E data) having a sampling frequency of 27 [MHz] will be described. . In the first unit, the first B0 is subjected to a filtering process of setting the same B0 to E0, and B0 is held. Next, E1 is obtained by computation from the stored B0 and B1, B1 is retained, and B0 is discarded. Next, E2 is obtained by calculation from the held B1 and B2, and B2 is held while B1 is held. Next, E3 is obtained from the stored B1 and the stored B2 by calculation, B1 is discarded, and B2 is stored. Thereafter, by the same processing, the B data from the two adjacent D data
Obtain data sequentially. Thus, the filtering process in one unit is two taps. Then, E14, which is the final data of the first unit, is calculated from B7 in the first unit and B8 in the second unit. Thus, the first unit E0 to E
14 is obtained. For the second and subsequent units, the same filtering process as in the first unit is repeated. Thus, the sampling frequency 14.3 [MH]
z] can be converted to digital image data (D data) having the original sampling frequency of 27 [MHz]. The last pixels in the effective video period are B767 and E1439, and B768 is E
It is used as reference data for obtaining 1439.

Next, digital image data (D data) having a sampling frequency of 27 [MHz] is converted to a sampling frequency of 14.3.
The calculation in the above-described filtering process for converting into digital image data (B data) of [MHz] will be described.
The number of pixels of the digital image data having a sampling frequency of 27 [MHz] is twice the number of pixels of the digital image data having a sampling frequency of 13.5 [MHz]. If twice the number of pixels exist at equal intervals in the effective video period, the sampling frequency is 1
The distance between the pixels of the digital image data of the sampling frequency 27 [MHz] with respect to the distance between the pixels of the 3.5 [MHz] digital image data is half. In the first embodiment, the sampling frequency is 13.5 [MH] as shown in FIG.
z], the sampling frequency is 14.3 [MHz] by weighting the distance obtained by dividing each pixel of the digital image data into 16 parts.
Of digital image data. In the fourth embodiment, each pixel of the digital image data of the sampling frequency of 13.5 [MHz] is divided into eight, and the weight of the distance by the eight divisions is used to convert the digital image data of the sampling frequency of 27 [MHz]. Calculate.

The B data having a sampling frequency of 14.3 [MHz] includes sampling frequencies 27 before and after the B data.
It is obtained from two adjacent D data of [MHz] and the distance of the B data from these D data. Weighting of E data sampled at the same position as B data is 1
6/16, when the D data is sampled at a position one scale left and right from the B data, this D data
Data weighting is 7/8, and D data is B
When the data is sampled at a position two scales apart from the data to the left and right, the weight of the D data is 6/8. Here, the scale is obtained by dividing the distance between adjacent D data into eight.

From the above, since the first pixel D0 and B0 in the first unit are arranged at the same position, the arithmetic expression for calculating B0 is B0 = (8/8) D0. Next, since the weighting of D1 for B1 is 1/8 and the weighting of D2 for B1 is 7/8,
The arithmetic expression for obtaining 1 is: B1 = (1/8) D1 + (7/8) D2. Next, since the weight of D3 for B2 is 2/8 and the weight of D4 for B2 is 6/8,
The arithmetic expression for obtaining 2 is: B2 = (2/8) D3 + (6/8) D4. In this way, the arithmetic expression for obtaining the B data is obtained by moving the distance between the adjacent D data and the B data left and right by 1/8. B3 and thereafter can also be obtained by calculation according to the same rule. Then, since the first D15 and B8 in the second unit have the same arrangement again, the arithmetic expression for calculating B8 is B8 = (8/8) D15.

Next, in the above filtering process, digital image data (B data) having a sampling frequency of 14.3 [MHz] is converted into digital image data (E data) having a sampling frequency of 27 [MHz]. The operation will be described. The distance between each pixel of the digital image data of the sampling frequency 14.3 [MHz] is approximated to 16 as in FIG. The E data having a sampling frequency of 27 [MHz] corresponds to a sampling frequency of 14.3 [M] positioned before and after the E data.
[Hz], and the distance of the E data from these two pieces of B data. The weight of E data sampled at the same position as B data is 16 /
If the B data is sampled at a position left and right by one division from the E data, the weight of the B data is 15/16, and the B data is
When the data is sampled at a position separated from the data by two scales to the left and right, the weight of the B data is 14/16. Here, the scale is obtained by dividing the distance between adjacent B data into 16 divisions.

From the above, since the first pixel B0 and E0 in the first unit are arranged at the same position, the equation for calculating E0 is E0 = (16/16) B0. Next, the weighting of B0 for E1 is 7/16
Since the weight of B1 with respect to E1 is 9/16, the arithmetic expression for calculating E1 is: E1 = (7/16) B0 + (9/16) B1. Next, the weight of B1 for E2 is 15/1
6, and the weighting of B2 with respect to E2 is 1/16, so the equation for calculating E2 is: E2 = (15/16) B1 + (1/16) B2. Next, the weight of B1 for E3 is 6/16
Since the weight of B2 with respect to E2 is 10/16, the arithmetic expression for calculating E3 is E3 = (6/16) B1 + (10/16) B2. After E3, it can be obtained by calculation according to the same rule. Then, since the first B8 and E15 in the second unit have the same arrangement again, the arithmetic expression for obtaining E15 is E15 = (16/16) B8.

[0103]

[Table 3] Table 3 shows an arithmetic expression of the filtering process according to the fourth embodiment of the present invention. That is, Table 3 shows that the sampling frequency 27
From digital image data (D data) of [MHz], digital image data (B of sampling frequency 14.3 [MHz]
Data) and a sampling frequency of 14.3 [M
Hz] of digital image data (B data) to obtain digital image data (E data) of the original sampling frequency of 27 [MHz]. Note that the calculation formula for calculating B9 and thereafter is the same repetition as the calculation formula for B1 to B8, and the calculation formula for obtaining E16 and after is the same repetition as the calculation formula for E1 to E16.

FIG. 13 is an operation timing chart of sampling frequency conversion circuits A and B according to the fourth embodiment. In FIG. 13, (A) shows a sampling frequency conversion circuit A
A clock c of 27 [MHz] serving as an operation reference clock of the sampling frequency converter B, (B) is a digital image data signal b of a sampling frequency 27 [MHz] inputted to the sampling frequency conversion circuit A, and (C) is a digital image signal. A digital image data signal obtained by delaying the data signal b by one clock (a signal generated inside the digital filter unit of the sampling frequency conversion circuit A);
(D) is a calculation result by the digital filter unit of the sampling frequency conversion circuit A, (E) is an enable signal i by the enable signal generation unit of the sampling frequency conversion circuit A, and (F) is an output from the sampling frequency conversion circuit A. Sampling frequency 1
4.3 [MHz] digital image data signal h, (G)
Is an enable signal i1 obtained by delaying the enable signal i by one clock (a signal generated by the delay unit 9 of the sampling frequency conversion circuit B), and (H) is a sampling frequency input from the core block to the sampling frequency conversion circuit B 14.3 [M
Hz] (the digital filter unit 32 of the sampling frequency conversion circuit B outputs the enable signal i1
Digital image data signal captured according to
Is a digital image data signal (a signal generated inside the digital filter unit 32) obtained by delaying the digital image data signal n by one clock, and (J) is the original sampling frequency 27.
[MHz] digital image data signal o (digital image data signal output from the sampling frequency conversion circuit B).

The counter section of the sampling frequency conversion circuit A is
13. The number of pixels 1440 in one horizontal effective video period and the sampling frequency when sampling is performed at the sampling frequency 27 [MHz].
The greatest common divisor 96 with the number of pixels 768 in one horizontal effective video period when sampling is performed at 3 [MHz] is 96.
8 which is the number obtained by dividing 8 is the maximum count value, and 1 to 8
Is counted repeatedly. The counter unit 21 of the sampling frequency conversion circuit B has a sampling frequency of 14.3 [M
Hz], and the number of pixels 768 in one horizontal effective video period when sampled at a sampling frequency of 27 [MHz], and the number of pixels 1440 in one horizontal effective video period when sampled at a sampling frequency of 27 [MHz]. 15 which is the number obtained by dividing the number of pixels 1440
Is the maximum count, and counting from 1 to 15 is repeated.

In order to obtain a digital image data signal h having a sampling frequency of 14.3 [MHz], two adjacent pixels in the digital image data signal b having a sampling frequency of 27 [MHz] are required. For this reason, the digital filter unit of the sampling frequency conversion circuit A generates the digital image data signal of FIG. 13C in which the digital image data signal b is delayed by one clock period, and outputs the two adjacent digital image data signals b. Pixels are obtained at the same time. Then, the digital image data signal b and the digital image data signal delayed by one clock are filtered by an arithmetic expression selected according to the count value to obtain the operation result of FIG. 13D. However, the pixel data constituting the digital image data signal h having a sampling frequency of 14.3 [MHz] is obtained every other clock, and the last pixel data in a certain unit and the first pixel data in the next unit ( For example, B7 and B8) are obtained continuously. Therefore, 1 where there are 15 D data
By taking in eight B data from the above operation result in accordance with the enable signal i during the unit period, FIG.
A digital image data signal h having a sampling frequency of 14.3 [MHz] in (F) can be obtained.

From core block to sampling frequency conversion circuit B
Is delayed by one clock period from the digital image data signal h due to signal processing in the core block. Therefore, the digital filter unit 32 of the sampling frequency conversion circuit B
Cannot capture the digital image data signal n with the enable signal i. Therefore, the delay unit 26 of the sampling frequency conversion circuit B generates an enable signal i1 that is obtained by delaying the enable signal i by one clock period, and inputs the enable signal i1 to the digital filter unit 32. Accordingly, the digital filter unit 32 converts the input digital image data signal n into the enable signal i.
1 can be captured.

The calculation for obtaining the digital image data having the original sampling frequency of 27 [MHz] includes the sampling frequency of 1 [MHz].
Two adjacent pixels in 4.3 [MHz] digital image data are required. For this reason, the digital filter unit 32 generates the digital image data signal of FIG. 13 (I) in which the digital image data signal n is delayed by one clock period, and two adjacent pixels of the digital image data signal n are obtained at the same time. I am trying to be. Then, a digital image data signal o having a sampling frequency of 27 [MHz] in FIG. 13 (J) is obtained for each clock by a filtering process using an arithmetic expression selected according to the value of the decode signal r.

As described above, according to the fourth embodiment, the digital image data signal b sampled at the first sampling frequency 27 [MHz] is converted to the second sampling frequency 14.3 [MH].
z] is converted into a digital image data signal h sampled by z], and further processed into a digital image data signal n
A sampling frequency conversion system for converting a (digital image data signal sampled at a first sampling frequency) into a digital image data signal o sampled at an original first sampling frequency is described in the above embodiment. It can be realized with a simple circuit configuration as in the third embodiment. Further, the digital filter section 32 has a plurality of digital filters and is switched by a decode signal, or has a single digital filter, and is a circuit that performs a plurality of stages of filtering processing in which the coefficient is switched by the decode signal. You may.

[0110]

As described above, according to the sampling frequency conversion circuit of the first aspect of the present invention, the number of pixels at the first sampling frequency and the number of pixels S2 ( Or a value obtained by dividing S2 (or H2) by a common divisor of H2) as a count maximum value, repeatedly counting up to the count maximum value, and processing the first digital image data with a digital filter corresponding to the count value. By
There is an effect that a sampling frequency conversion circuit having a simple circuit configuration that does not include a circuit that performs a plurality of stages of filtering processing can be realized.

According to the sampling frequency conversion circuit of the second aspect of the present invention, the means for monitoring the pixel arrangement of the second digital image data and correcting the pixel arrangement to an appropriate pixel arrangement is provided. Correcting the pixel arrangement of the second digital image data to an appropriate position even when the pixel arrangement of the first digital image data is displaced from the pixel arrangement of the second digital image data signal. There is an effect that can be.

According to the sampling frequency conversion method of the present invention, the first digital image data is converted to the second digital image data.
, And a sampling frequency conversion system that converts the second digital image data into digital image data sampled at the original first sampling frequency can be realized with a simple circuit configuration. This has the effect.

According to the sampling frequency conversion method of the present invention, the first sampling frequency conversion circuit, the core block, and the second sampling frequency conversion circuit are operated by the same operation clock. By controlling the signal processing timing of the core block by the control signal generated in the first sampling frequency conversion circuit, there is an effect that the configuration of the sampling frequency conversion system can be further simplified.

[Brief description of the drawings]

FIG. 1 is a block diagram of a sampling frequency conversion circuit according to a first embodiment of the present invention.

FIG. 2 shows sampling frequencies of 13.5 [MHz] and 1
FIG. 4 is a diagram illustrating a relationship between sampling positions of pixel data of digital image data of 4.3 [MHz].

FIG. 3 is a diagram in which a part of FIG. 2 is enlarged and a distance scale is added.

FIG. 4 is an operation timing chart of the sampling frequency conversion circuit of FIG. 1;

FIG. 5 is a block diagram illustrating a sampling frequency conversion circuit according to a second embodiment of the present invention;

FIG. 6 is a block diagram of a pixel arrangement correction unit in FIG. 5;

FIG. 7 is a block diagram of a sampling frequency conversion system according to a third embodiment of the present invention.

FIG. 8 is a block diagram of a sampling frequency conversion circuit B according to Embodiment 3 of the present invention.

FIG. 9 is a diagram illustrating a relationship between a sampling frequency and a pixel arrangement according to the third embodiment of the present invention.

FIG. 10 is an operation timing chart of the sampling frequency conversion circuit B of FIG. 8 according to the third embodiment of the present invention.

FIG. 11 is a block diagram of a sampling frequency conversion circuit B according to a fourth embodiment of the present invention.

FIG. 12 is a diagram illustrating a relationship between a sampling frequency and a pixel arrangement according to the fourth embodiment of the present invention.

FIG. 13 is a diagram showing operation timing according to the fourth embodiment of the present invention.

FIG. 14 is a block diagram showing a conventional sampling frequency conversion circuit.

[Explanation of symbols]

1, 21 counter section, 2, 22, 32 digital filter section, 3, 23 decoding section, 4, 24 enable signal generation section, 5, 25 pixel arrangement correction section, 6
Pixel arrangement monitoring unit, 7 correction filter unit, 8 selector unit, 9, 26 delay unit, 10 selector unit,
11 sampling frequency conversion circuit A, 12 core block, 13 sampling frequency conversion circuit B, a, a1 effective video period signal, b, s, o digital image data signal sampled at the first sampling frequency, c Clock, d, p count value, e, r decode signal,
f, i, i1, m, q enable signals, g, h,
l, n A digital signal sampled at the second sampling frequency, a j-shift width signal, and a k-shift detection signal.

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Yoshiaki Mimura 2-3-2 Marunouchi, Chiyoda-ku, Tokyo F-term in Mitsubishi Electric Corporation (reference) 5C059 KK15 LB15 SS01 UA02 5C063 AC01 BA08 BA20

Claims (4)

[Claims] A first sampling frequency sampled at a first sampling frequency;
In the sampling frequency conversion circuit for converting the digital image data of the above to the second digital image data sampled at the second sampling frequency, wherein the horizontal effective video period in the case of sampling at the first sampling frequency The number obtained by dividing the number of pixels S2 by a common divisor of the number of pixels S2 and the number S2 of pixels in the horizontal effective video period when sampling is performed at the second sampling frequency is set as a count maximum value, or The number of pixels H2 is divided by the common divisor of the number of pixels in the horizontal scanning period when sampling is performed at the sampling frequency of the second sampling frequency and the number of pixels H2 in the horizontal scanning period when sampling is performed at the second sampling frequency. The maximum value of the count is used as the maximum count value. Counting means that repeatedly counts up to the above maximum value, and processing by a digital filter is specified for each operation clock according to the count value of the above counting means. Means for generating a first control signal for processing the first digital image data with a digital filter selected in accordance with the first control signal. A conversion means for converting the first digital image data into the second digital image data. 2. A pixel arrangement of the second digital image data with respect to a pixel arrangement of the first digital image data, and when a start position of the second digital image data is shifted, an appropriate pixel arrangement is provided. 2. The sampling frequency conversion circuit according to claim 1, further comprising means for correcting the sampling frequency. 3. A first sampling frequency sampled at a first sampling frequency.
Is converted to second digital image data sampled at a second sampling frequency, and the second digital image data or the second
In the sampling frequency conversion method of converting the digital image data of (a) into digital image data sampled at the original first sampling frequency, [A] in the first first sampling frequency conversion circuit, The number of pixels is a common divisor of the number of pixels in the horizontal effective image period when sampling at the sampling frequency of 1 and the number S2 of pixels in the horizontal effective image period when sampling at the second sampling frequency. The number obtained by dividing S2 is taken as the maximum count value, or the number of pixels in the horizontal scanning period when sampling at the first sampling frequency and the horizontal scanning when sampling at the second sampling frequency A step of counting the number of pixels obtained by dividing the number of pixels H2 by a common divisor with the number of pixels H2 of the period as a maximum count value and repeatedly counting up to the maximum count value; [B] in the first sampling frequency conversion circuit, By selecting one from a plurality of digital filters in accordance with the count value in step [A] and processing the first digital image data with the selected digital filter, the first digital image data is converted to the second digital filter. Converting into digital image data; [C] in a second sampling frequency conversion circuit, the number of pixels in a horizontal effective video period when sampling at the second sampling frequency and the first sampling The maximum count value is obtained by dividing the number of pixels S1 by a common divisor with the number of pixels S1 in the horizontal effective video period in the case of sampling at the frequency, or when sampling at the second sampling frequency. The maximum count value is obtained by dividing the number of pixels H1 by a common divisor of the number of pixels in the horizontal scanning period of the horizontal scanning period and the number of pixels H1 in the horizontal scanning period when sampling is performed at the first sampling frequency. A step of counts repeated until the maximum count value,
[D] In the second sampling frequency conversion circuit, one of a plurality of digital filters is selected according to the count value in step [C], and the digital filter generated in step [B] by the selected digital filter. Second
By processing the digital image data of
Converting the digital image data into digital image data sampled at a first sampling frequency. 4. The method according to claim 1, wherein the first sampling frequency conversion circuit and the second sampling frequency conversion circuit are operated by the same operation clock, and the second sampling is performed between the steps [B] and [C]. A core block designed to process digital image data sampled at a sampling frequency is operated by the operation clock, and a signal processing timing of the core block is generated by the first sampling frequency conversion circuit. 4. The sampling frequency conversion method according to claim 3, further comprising a step of performing signal processing on said second digital image data generated in said step [B] in said core block by controlling with a control signal. .