JP2846427B2 - PAL signal / CIF signal conversion circuit - Google Patents

Description

Detailed Description of the Invention [Table of Contents] Overview Industrial application field Conventional technology (Fig. 9) Problems to be solved by the invention Means for solving the problems [Fig. 1 (a), (b) Operation [FIGS. 1 (a) and (b)] Example Description of the first embodiment (FIGS. 2 to 6) Description of the second embodiment (FIGS. 7 and 8) Effect of the Invention [Overview] TV It is used in a system that exchanges image signals using a conference device or videophone, etc. For circuits that convert between CIF signals / PAL signals, the cycle of the delay number and the weight distribution of interpolation coefficients can be easily performed.
The purpose is to enable the conversion of PAL / CIF signals by a simple configuration and control. The pre-stage memory performs periodic variable delay on the PAL signal, and the post-stage memory performs fixed delay on the output signal from the pre-stage memory. A frame interpolation processing circuit that performs temporal frame interpolation on a PAL signal and an output signal from each memory to output a signal of a temporary frame frequency, and disables a frame synchronization signal of the temporary frame frequency once for a required number of frames. And a time correction circuit for outputting the output signal from the frame interpolation processing circuit by using the frame synchronization signal from the time correction circuit for one frame for a required number of frames.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit used in a system for exchanging image signals using a video conference device, a video phone, or the like, and particularly to a required PAL frame frequency (for example, 25 Hz).
Is converted to a CIF signal having a higher CIF frame frequency (for example, 29.97 Hz) than the PAL frame frequency, or a PA for converting the CIF signal to a PAL signal.
The present invention relates to an L signal / CIF signal conversion circuit.

The National Television Committee (NTSC; National Television)
System Commitee) developed the NTSC system as a color television system compatible with the black and white television system, and the PAL (Phase Alternation by Line) system, which improved the disadvantage that the NTSC system is susceptible to hue distortion during transmission. is there.

By the way, about the standardized video codec, CCITT
However, when implementing such a globally standardized video codec, the difference in the above-mentioned television system in each country becomes a problem.

Therefore, in order to be able to take out a video even between different television systems, a signal of a target system is obtained after the signal is once converted into a CIF (Common Intermediate Format) signal which is a common intermediate data format. The present invention particularly relates to such a conversion method between a CIF signal and a PAL signal.

[Prior Art] Fig. 9 shows an image taken with a PAL television camera in NTSC.
FIG. 9 is a block diagram for viewing on a monitor of the PAL system. In FIG.
PAL / CIF signal conversion circuit that converts signals to CIF signals
102 is a codec, 103 is a transmission line, 104 is a decoder, 105 is a CIF signal / NTSC for converting a CIF signal to an NTSC signal.
A signal conversion circuit 106 is an NTSC monitor.

With such a configuration, the video captured by the PAL television camera 100 is subjected to A / D conversion, and is then temporarily converted from a PAL signal to a CIF signal by a PAL signal / CIF signal conversion circuit 101. After being coded by the codec 102, passed through the transmission path 103, and decoded by the decoder 104, the CIF signal / NTS
The C signal conversion circuit 105 converts the CIF signal into an NTSC signal, and further performs D / A conversion and displays the converted signal on a monitor 106.

By the way, generally, the frame frequency of a PAL signal is 25 Hz.
And the frame frequency of the CIF signal is almost 30 Hz (strictly, about 2
9.97 Hz), and the CIF signal requires six frames for five PAL signal frames. Therefore, conventionally, PA
When converting the L signal to a CIF signal, one out of every five frames is superimposed on the same frame, or by interpolating two appropriate frames every five and adding one frame, The frame frequency is converted from 25Hz to 30Hz.

[Problems to be Solved by the Invention] However, as described above, when the PAL signal / CIF signal conversion is performed only by the superposition of frames, in the case of a moving image, the motion necessarily appears to have discontinuity. There are issues.

Also, when performing interpolation processing, the frame frequency of the CIF signal is actually about 29.97 Hz, and the frame frequency 2
Strictly speaking, the start position of the frame coincides only once every 40.04 seconds with a 5 Hz PAL signal, so it is difficult to distribute the weight of the interpolation coefficient in order to perform the PAL signal / CIF signal conversion strictly by interpolation processing. It is.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and can easily perform a period of a delay number and weight distribution of an interpolation coefficient, and can surely convert a PAL signal / CIF signal by a simple configuration and control. The purpose of the present invention is to provide an improved circuit.

[Means for Solving the Problems] FIG. 1A is a principle block diagram according to the first invention of the present invention, in which a PAL signal having a required PAL frame frequency is converted.
3 shows a circuit for converting to a CIF signal having a CIF frame frequency higher than a PAL frame frequency.

In FIG. 1 (a), reference numeral 1 denotes a pre-stage memory that applies a periodic variable delay to a PAL signal, and 2 denotes a post-stage memory that applies a fixed delay to a signal obtained by applying a periodic variable delay to the PAL signal from the pre-stage memory 1. 3 receives a PAL signal, an output signal from the pre-stage memory 1, and an output signal from the post-stage memory 2, and performs frame interpolation in the time direction on these signals to output a signal having a temporary frame frequency higher than the CIF frame frequency. Frame interpolation processing circuit,
Reference numeral 4 denotes a time correction circuit for invalidating and outputting a frame synchronization signal having a provisional frame frequency once per a required number of frames, and using the frame synchronization signal from the time correction circuit 4 to output from the frame interpolation processing circuit 3. The signal is drawn for one frame for a required number of frames.

Here, the pre-stage memory 1 and the post-stage memory 2 may each be constituted by a FIFO memory (claim 2), or the pre-stage memory 1 may be formed by a write / read signal generated by a carry-out signal output count variable counter. In addition to the configuration in which the number of delays is controlled, the latter-stage memory 2 may be configured to control the number of delays by a write / read signal generated by a counter having a fixed carry-out signal output count value. Further, the frame interpolation processing circuit 3 includes a selector for selecting one of the PAL signal and the output signal of the pre-stage memory 1, a multiplier for multiplying the output signal from the selector by a required interpolation coefficient, and a post-stage memory 2
A multiplier for multiplying the output signal from by a required interpolation coefficient,
ROM for giving an interpolation coefficient for weight distribution to each multiplier,
An adder that adds the output signals of the multipliers and outputs a signal having a temporary frame frequency higher than the CIF frame frequency may be provided. Further, the time correction circuit 4 includes a counter for counting whether the required number of frames has been reached for the frame synchronization signal having the temporary frame frequency, and a frame interpolation process when the counter detects that the required number of frames has been reached. The output signal of the circuit 3 may be provided with a gate circuit for invalidating the frame synchronization signal in order to thin out one frame of the output signal (claim 5).

On the other hand, FIG. 1 (b) is a principle block diagram according to a second invention of the present invention, wherein a CIF having a required CIF frame frequency is provided.
FIG. 4 shows a circuit for converting a signal to a PAL signal having a PAL frame frequency lower than the CIF frame frequency.

In FIG. 1B, reference numeral 21 denotes a time correction circuit for outputting a signal having a temporary frame frequency higher than the CIF frame frequency by superimposing one frame for a required number of frames on the CIF signal, and 22 a temporary frame. A pre-stage memory that performs a periodic variable delay on a signal having a frequency, a selector 23 selects one of a signal having a temporary frame frequency and an output signal from the pre-stage memory 22, and 24 has a fixed delay for a signal from the selector 22. A post-stage memory 25 to be subjected to frame interpolation processing which receives an output signal from the pre-stage memory 22 and an output signal from the post-stage memory 24 and performs frame interpolation in the time direction on these signals to output a PAL signal having a PAL frame frequency. Circuit.

Here, the time correction circuit 21 stores a pair of memories that store the CIF signal with a required time difference, a selector that selects and outputs the output from these memories, and whether the required number of frames for the CIF signal has been reached. And a counter for counting whether or not the required number of frames is detected by the counter. By switching the selector, the CIF signal is overlapped by one frame for the required number of frames. (Claim 7). In addition, the first-stage memory 22 and the second-stage memory 24 include:
Each may be constituted by a FIFO memory (claim 8),
The pre-stage memory 22 is configured to control the number of delays by a write / read signal generated by a variable counter of the carry-out signal output count value.
May be configured such that the number of delays is controlled by a write / read signal generated by a counter having a fixed carry-out signal output count value. Further, the frame interpolation processing circuit 25 includes a multiplier for multiplying the output signal from the preceding memory 22 by a required interpolation coefficient, a multiplier for multiplying the output signal from the subsequent memory 24 by a required interpolation coefficient, and May be configured by a ROM for providing an interpolation coefficient for weight distribution to the adder, and an adder for adding the output signals of the respective multipliers and outputting a PAL signal having a PAL frame frequency (claim 10).

[Operation] The PA according to the first invention of the present invention shown in FIG.
In the L signal / CIF signal conversion circuit, the input PAL signal is subjected to a periodic variable delay by the pre-stage memory 1 and a fixed delay by the post-stage memory 2, and the PAL signal and the PAL signal are output by the frame interpolation processing circuit 3. Each memory
By performing frame interpolation in the time direction on the output signals from 1 and 2, a temporary frame frequency higher than the CIF frame frequency is set so that the least common divisor of the frame frequencies of the PAL signal and the CIF signal becomes a simple integer value. Is generated and output.

Then, the time synchronization circuit 4 outputs a frame synchronization signal having a provisional frame frequency to the required number of frames by one.
The output signal from the frame interpolation processing circuit 3 is extracted for one frame for a required number of frames by the thinned frame synchronization signal, and a PAL signal having a required PAL frame frequency is converted to the PAL signal. It is converted to a CIF signal having a higher CIF frame frequency than the frame frequency.

On the other hand, in the PAL signal / CIF signal conversion circuit according to the second invention of the present invention shown in FIG. 1 (b), first, the time correction circuit 21 converts the input CIF signal for each required number of frames. A signal having a temporary frame frequency higher than the CIF frame frequency is created and output so that one frame is superimposed so that the least common divisor of the frame frequencies of the PAL signal and the CIF signal becomes a simple integer value.

Then, the signal having the temporary frame frequency from the time correction circuit 21 is subjected to a periodic variable delay by the pre-stage memory 22 and a fixed delay by the post-stage memory 24. At this time, the signal from the time correction circuit 21 is directly input to the subsequent memory 24 by skipping the former memory 22 once every predetermined number of times by the selector 23 interposed between the former memory 22 and the latter memory 24. Switch to be. Thereafter, the frame interpolation processing circuit 25 performs time-direction frame interpolation on the output signals from the memories 22 and 24, and the CIF signal having the required CIF frame frequency has a PAL frame frequency lower than the CIF frame frequency. It is converted to a PAL signal having

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

(A) Description of First Embodiment FIG. 2 is a block diagram showing a first embodiment of the present invention. In this first embodiment, a PAL signal having a frame frequency of 25 Hz is converted into a CIF signal having a frame frequency of 29.97 Hz. The circuit will be described.

In FIG. 2, 1A is a first-stage FIFO memory for performing a periodic variable delay on the PAL signal A as shown in Table 1 described later, and 2A is a second-stage FIFO memory for performing a fixed delay on the signal B from the first-stage FIFO memory 1A. FIFO memory 1A is by the write signal W ₁ and the read signal R ₁ from the carry-out signal output count variable of the counter 5, for example, with the control the number of delay as shown in the following table 1, the FIFO memory 2A
Is adapted to be controlled by the write W ₂ and read signal R ₂ from the carry-out signal output count fixed counter 6, for example, the number of delay as shown in Table 1 below.

The unit of the value in Table 1 below is a clock, which is a value when sampling at 13.5 MHz. Further, as shown in FIG. 3, f1 to f5 correspond to codes sequentially assigned to each frame of a set of five PAL signal A frames.

3A is a PAL signal A and an output signal B from the FIFO memory 1A.
A frame interpolation processing circuit which receives the output signal C from the FIFO memory 2A and performs frame interpolation in the time direction on these signals A to C to output a CIF conversion signal D having a temporary frame frequency of 30 Hz.

The frame interpolation processing circuit 3A uses the PAL signal A and the FIF
A selector 7 for selecting one of the output signals B of the O memory 1A, a multiplier 8 for multiplying the output signal from the selector 7 by a required interpolation coefficient X, and a required correction for the output signal C from the FIFO memory 2A A multiplier 9 for multiplying the interpolating coefficient Y, and a ROM 10 for the interpolating coefficient storing the interpolating coefficients X and Y as shown in Table 2 below.
And the output signals of the multipliers 8 and 9 are added, and the temporary frame frequency 3
And an adder 11 for outputting a CIF conversion signal D having 0 Hz.

As shown in FIG. 3, f'1 to f'6 in Table 2 below represent frames of the CIF conversion signal D having a temporary frame frequency of 30 Hz obtained by the interpolation processing of the frame interpolation processing circuit 3A. Are set as a set of six, and correspond to the codes sequentially given to each frame.

Further, 4A uses a 30 Hz frame synchronizing signal by 1, in order to thin out one frame per 1,000 required frames of the CIF conversion signal D from the frame interpolation processing circuit 3A.
This is a time correction circuit that invalidates and outputs only once every 000 times.

The time correction circuit 4A includes a counter 12 for calculating whether or not the required number of frames of the 30 Hz frame synchronization signal has reached 1,000, and the counter 12 has a required number of frames of 1,000.
When it is detected that the value has become 0, the frame interpolation processing circuit 3A
And a gate circuit 13 for invalidating the 30 Hz frame synchronization signal in order to thin out one frame of the CIF conversion signal D from the CIF.

The 30 Hz frame synchronization signal is obtained by converting a 25 Hz frame synchronization signal obtained when the output of the television camera is converted into a digital signal by a frequency change circuit (not shown).

Reference numeral 14 denotes a controller for controlling the apparatus of the present embodiment, particularly, the counters 5 and 6 and the interpolation coefficient ROM 10.

With the above configuration, the PAL signal A having a frame frequency of 25 Hz
Is converted to a CIF signal E having a frame frequency of 29.97 Hz as follows.

First, a PAL signal A having a frame frequency of 25 Hz is converted into a CIF conversion signal D having a temporary frame frequency of 30 Hz. in this case,
As shown in FIG. 4, the time between a certain coordinate in the frame and the same coordinate in the next frame is 40 ms for the PAL signal A and about 33.36 ms for the CIF conversion signal D.

The PAL digital signal A sampled by the 13.5 MHz clock is a two-stage FIFO memory (one stage has at least a CI
It is input to a circuit composed of 1A and 2A (having a capacity for one frame of the F signal).

In front FIFO memory 1A, the write signal W ₁ and the read signal R ₁ counter 5 to make the number of delay is set as shown in Table 1, each frame of the PAL signal A F1～f
5 is sequentially delayed by five periods of variable periods of 33.3, 26.7, 20, 13.3, and 6.7 ms, and an output B as shown in FIG. 3 is obtained.
In the later stage FIFO memories 2A, by writing W ₂ and read signal R ₂ counter 6 makes, the number of delay is set to a constant value as shown in Table 1, sequentially a predetermined time to the output B from the FIFO memory 1A 33.3 A delay is given in ms, and an output C as shown in FIG. 3 is obtained.

The selector 7 in the frame interpolation processing circuit 3A
Thus, the PAL signal A of 25 Hz is selected only once in six cycles, and the output signal B of the previous-stage FIFO memory 1A is selected for the rest.
The outputs A and B from the selector 7 and the output C from the subsequent-stage FIFO memory 2A are respectively used by the multipliers 8 and 9 to obtain the interpolation coefficients X and Y (0
≦ X, Y ≦ 1), the multiplication results from the multipliers 8 and 9 are added by the adder 11. Thereby, the PAL signal A
From the five frames f1 to f5, as shown in FIG. 3, six frames f'1 to f'6, a CIF conversion signal D having a tentative frame frequency of 30 Hz is obtained. That is, the frame f 'uses one frame f1 as it is, and the frames f'2 to f'6 are f1 and f2 and f2, respectively.
And f3, f3 and f4, f4 and f5, and f5 and the next f1 are multiplied by interpolation coefficients X and Y shown in Table 2 and then added.

CIF with a temporary frame frequency of 30 Hz created as described above
The conversion signal D is sent to the codec side. At this time, the 30 Hz frame synchronization signal is counted by the counter 12, and
When it is detected that the count value has reached 1,000, 30Hz
The frame synchronization signal is invalidated by thinning out one frame by the gate circuit 13. In other words, the frame synchronization signal with a temporary frame frequency of 30 Hz is invalidated once every 1,000 times,
By using this frame synchronization signal, the effective
A CIF signal with a frame frequency of 29.97 Hz is created and output.

FIG. 5 shows the format of the PAL signal A of 25 Hz. As shown in FIG.
The frame is interlaced with an odd field and an even field. On the other hand, FIG. 6 shows the format of the signal D for CIF conversion. As shown in FIG. 6, the signal D has only 288 non-interlaced signals in one frame. Is necessary, it is sufficient if there is an odd field portion of the PAL signal A, and the format of the CIF conversion signal D ends in the middle of the line, but there is no problem in conversion to the CIF signal E. That is, the CIF conversion signal D as shown in FIG. 6 can be used without converting the number of pixels and the number of lines of one line of the PAL signal A.

In addition, the frame interpolation processing circuit 3A operates on the same phase clock.

As described above, according to the PAL signal / CIF signal conversion circuit of the first embodiment of the present invention, the two-stage FIFO memories 1A and 2A and the frame interpolation processing circuit 3A provide a frame frequency of 25 Hz.
Interpolation processing of the PAL signal A in the time direction is performed, and six frames are created from five frames to generate a temporary frame frequency of 30.
Hz CIF conversion signal D and time correction circuit 4A
, A 30 Hz frame synchronization signal is thinned out once every 1,000 times, and a CIF signal having a frame frequency of 29.97 Hz is obtained by using the frame synchronization signal. As a result, as shown in Tables 1 and 2, the period of the delay number and the weight distribution of the interpolation count are determined very easily, and the PAL signal A having a frame frequency of 25 Hz is converted to a frame frequency of 29.97 by a simple control.
It can be reliably converted to the CIF signal E of Hz.

(B) Description of the Second Embodiment FIG. 7 is a block diagram showing a second embodiment of the present invention. In the second embodiment, contrary to the first embodiment, a CIF signal having a frame frequency of 29.97 Hz is transmitted. A circuit for converting a PAL signal having a frame frequency of 25 Hz will be described.

In Figure 7, 21A is a time correction circuit for outputting a signal B ₁ having a temporary frame frequency 30Hz by superimposing one frame per predetermined frame number 1000 for CIF signal A _1.

The time correction circuit 21A includes a pair of memories 26 and 27 for storing with a a CIF signal A ₁ required time difference, these memory 2
Selector 28 that selects and outputs the output from 6, 27, and CIF
For CIF signal A ₁ counts the sync signal of the frame frequency 29.97Hz signal A ₁ is composed of a counter 29 for counting now? Required frame 1,000, the number required frames that counter 29 1,000 Is detected, the selector 28 is switched to set the CIF signal A1 to ₁ per 1,000 required frames.
Frames are superimposed.

Reference numeral 22A denotes a _first- stage FI that applies a periodic variable delay to the signal B1 from the time correction circuit 21A as shown in Table 3 described later.
FO memory, 23 for selecting either the output signal C ₁ from the signal B ₁ and preceding the FIFO memory 22A from the time correcting circuit 21A selector, 24A are signals B ₁ or C ₁ from the selector 23
A fixed delay is applied to the subsequent FIFO memory.
22A is a variable counter 3 for the carry-out signal output count value.
By the write signal W ₁ and the read signal R ₁ from 0, for example, with the control the number of delay as shown in the following table 3, FIFO memory 24A, the writing W ₂ and from the carry-out signal output count fixed counter 31 the read signal R _2, for example, is adapted to be control the number of delay as shown in table 3 below.

The unit of the value in Table 3 above is a clock, which is a value when sampling at 13.5 MHz. Further, f1 to f6 as shown in FIG. 8, a CIF signal B ₁ of the frame from the time correcting circuit 21A and six set, corresponds to the sequence given code to each frame.

Further, 25A output signals C ₁ and from the FIFO memory 22A
These signals C receives the output signal D ₁ of the from the FIFO memory 24A
_1, the frame interpolation processing circuit for outputting a PAL signal E ₁ of the frame frequency 25Hz by performing time-direction of the frame interpolation D _1.

The frame interpolation circuit 25A includes a multiplier 32 for multiplying the required interpolation coefficient X to the output signal C ₁ from the FIFO memory 22A
When, a multiplier 33 for multiplying the required interpolation coefficient Y to the output signal D ₁ of the from the FIFO memory 24A, the interpolation coefficients as shown in Table 4 below
X, an interpolation coefficient for ROM34 for storing Y, and an adder 35 for outputting a PAL signal E ₁ of the frame frequency 25Hz by adding the output signal of the multiplier 32 and 33.

Incidentally, F'1～f'5 in table 4, as shown in FIG. 8, five of the frame PAL signal E ₁ having a frame frequency 25Hz obtained by the interpolation process of the frame interpolation circuit 25A One set corresponds to the code sequentially given to each frame.

Reference numeral 36 in FIG. 7 denotes a controller for controlling the apparatus of this embodiment, in particular, the counters 30 and 31 and the interpolation coefficient ROM 34.

With the above configuration, a CIF signal with a frame frequency of 29.97 Hz
A ₁ is a PAL signal E with a frame frequency of 25 Hz as follows.
Converted to ₁ .

First, the CIF signal A ₁ of the frame frequency 29.97 Hz, is converted by the time correction circuit 21A to the signal B ₁ of the temporary frame frequency 30 Hz. That is, in the time correction circuit 21A, CIF signal A ₁ of the frame frequency 29.97Hz is written into the memory 27 sequentially reads at 30Hz gives first one frame delay. Due to the difference between the writing speed and the reading speed, the number of delays of the memory 27 gradually decreases. Also, memory 27
Is written to the memory 26 at 30 Hz. In the memory 26, reading is always performed with a delay of one frame. Thus, CIF signal A ₁ in memories 26 and 27 are stored with a predetermined time difference.

Then, the counter 29 counts the frame synchronizing signal synchronized with the frame frequency 29.97Hz of CIF signal A _1, when the count value is detected to be became 1,000, selector 2
8 is switched to select the output of the memory 26, and the same frame is superimposed only once in 1,000 times. At this time, memory 27
Is stopped. That is, the frame frequency is 29.97Hz
By superimposing once the CIF signal A ₁ to 1,000, prolonged to the frame frequency 30Hz signal B ₁ is being created output.

Next, the frame frequency 30Hz created as described above
Signal B ₁ of the two-stage FIFO memories 22A, 24A and the selector 2
Input to the circuit composed of 3.

In front FIFO memory 22A, the write signal W ₁ and the read signal R ₁ counter 5 to make the number of delay is set as shown in Table 3, the frame frequency 30Hz of CIF
About five f2~f6 other than f1 of each frame f1~f6 signals B _1, successively 5 variable cycle time 6.7,13.3,20,26.7,33.
The delay is given by 3 ms, and the output signal C ₁ as shown in FIG.
Is obtained.

An output signal C ₁ from the FIFO memory 22A, the CIF signal B ₁ from the time correction circuit 21A is input to the selector 23. The selector 23, the output signal C ₁ CIF signal B ₁ is a frame f1
Subsequent FIFO but only when a frame f6, and the subsequent stage FIFO memory 24A by selecting the CIF signal B ₁ frame f1, in other cases is always selects the output signal C ₁ from the FIFO memory 22A Output to memory 24A.

Then, in the latter-stage FIFO memory 24A, the counter 31
The delay number is set to a constant value as shown in Table 3 by the write W ₂ and read signal R ₂ generated by the selector 23, and the output B ₁ or C ₁ from the selector 23 is sequentially delayed for a constant time of 40 ms. an output D ₁ as shown in FIG obtained.

Outputs C ₁ and D ₁ from the FIFO memories 22A and 24A are input to multipliers 32 and 33 in the frame interpolation processing circuit 25A, respectively, and the interpolation coefficients X and Y shown in Table 4 read out from the interpolation coefficient ROM 34. (0 ≦ X, Y ≦ 1), then each multiplier
The multiplication results from 32 and 33 are added by the adder 35. As a result, frame interpolation processing is performed from the six frames f1 to f6 of the CIF signal B ₁ (A ₁ ) as shown as five frames f′1 to f′5 in FIG.
PAL signal E ₁ is obtained. That is, the frame f'1 uses the frame f1 as it is, and the frames f'2 to f'5 are shown in Table 4 as two frames f2 and f3, f3 and f4, f4 and f5, and f5 and f6, respectively. It is created by multiplying the indicated interpolation coefficients X and Y and then adding them.

As shown in FIGS. 5 and 6, in the format of the CIF signals A ₁ and B ₁ , valid data in one frame is converted into a format in which two fields of an odd field and an even field are non-interlaced. Whereas PAL
In the signal format, both odd and even fields are interlaced. Such conversion into a PAL signal is performed, for example, by using a field memory (FIG. 4) in order to use the CIF signal twice, in a case where the CIF signal is used for an odd field and in a case where the CIF signal is delayed by one field and used for an even field. (Not shown).

As described above, according to the PAL signal / CIF signal conversion circuit of the second embodiment of the present invention, first, 1,0
By performing the superposition of 00 one on frames, converts the CIF signal A ₁ of the frame frequency 29.97Hz the CIF signal B ₁ of the temporary frame frequency 30 Hz, 2-stage configuration of the FIFO memories 22A, 24A, the selector 23 and frame interpolation processing circuit 25
The A, performs time direction interpolation processing of the frame frequency 30Hz signals B _1, PAL signal E ₁ of the frame frequency 25Hz is obtained by creating five frames from 6 frames.
Thus, the period of delay number as shown in Tables 3 and 4, while very easily determine the weight distribution of the interpolation coefficients, CIF signal A ₁ the frame frequency of the frame frequency 29.97Hz a simple control
It is the reliably converted to a PAL signal E ₁ of 25 Hz.

In the above-described embodiment, the circuit for converting the PAL signal to the CIF signal and the circuit for converting the CIF signal to the PAL signal are separately described as the first embodiment and the second embodiment. Is usually configured to have circuit functions in these two conversion directions.

[Effects of the Invention] As described above in detail, according to the PAL signal / CIF signal conversion circuit of the present invention (claims 1 to 5), the two-stage memory and the frame interpolation processing circuit make the time direction of the PAL signal The interpolation process is performed to obtain a signal of the provisional frame frequency, and the time correction circuit thins out the frame synchronization signal to obtain a CIF signal of a required CIF frame frequency. , The weight distribution of the interpolation coefficient can be determined very easily, and the PAL signal can be
This has the effect that it can be reliably converted to an IF signal.

Further, the PAL signal / CIF signal conversion circuit of the present invention (claim 6)
According to 10), after a frame is overlapped by a time correction circuit to generate a signal of a temporary frame frequency,
The memory of the stage configuration, the selector and the frame interpolation processing circuit perform interpolation processing in the time direction of the signal of the temporary frame frequency to obtain the PAL signal of the required PAL frame frequency. Weight distribution can be determined very easily, and there is an effect that the CIF signal can be surely converted into the PAL signal by simple control.

[Brief description of the drawings]

FIG. 1 (a) is a principle block diagram according to the first invention of the present invention, FIG. 1 (b) is a principle block diagram according to the second invention of the present invention, and FIG. 2 is a first embodiment of the present invention. FIG. 3 is a block diagram showing an example, FIG. 3 is a time chart for explaining the operation of the first embodiment of the present invention, FIG. 4 is a diagram showing a frame interval between a PAL signal and a CIF conversion signal in a time axis direction, FIG. 5 is a diagram showing a format of a PAL signal, FIG. 6 is a diagram showing a format of a CIF signal, FIG. 7 is a block diagram showing a second embodiment of the present invention, and FIG. 8 is a second embodiment of the present invention. FIG. 9 is a block diagram of a case where an image taken by a PAL television camera is viewed on an NTSC monitor. In the figure, 1 is a pre-stage memory, 1A is a pre-stage FIFO memory, 2 is a post-stage memory, 2A is a post-stage FIFO memory, 3, 3A is a frame interpolation processing circuit, 4, 4A is a time correction circuit, 5, 6 is a counter, and 7 is a counter. Selector, 8 and 9 are multipliers, 10 is interpolation coefficient ROM, 11 is adder, 12 is counter, 13 is gate circuit, 14 is controller, 21, 21A is time correction circuit, 22 is previous stage memory, 22A is previous stage FIFO memory, 23 is a selector, 24 is a post-stage memory, 24A is a post-stage FIFO memory, 25 and 25A are frame interpolation processing circuits, 26 and 27 are memories, 28 is a selector, 29 to 31 are counters, 32 and 33 are multipliers, 34 is a ROM for interpolation coefficients, 35 is an adder, and 36 is a controller.

────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kiichi Matsuda 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (58) Fields investigated (Int.Cl. ⁶ , DB name) H04N 7/01

Claims (10)

(57) [Claims] 1. A pre-stage memory (1, 1) that performs a periodic variable delay on a PAL signal having a required PAL frame frequency so as to convert the PAL signal into a CIF signal having a CIF frame frequency higher than the PAL frame frequency. 1A); a post-stage memory (2, 2A) that applies a fixed delay to a signal obtained by performing a periodic variable delay on the PAL signal from the pre-stage memory (1, 1A); , 1A) and the output signal from the subsequent memory (2, 2A), and by performing frame interpolation in the time direction on these signals,
A frame interpolation processing circuit (3, 3A) for outputting a signal having a temporary frame frequency higher than the CIF frame frequency, and disabling the frame synchronization signal having the temporary frame frequency once for a required number of frames; A time correction circuit (4, 4A) for outputting, and using the frame synchronization signal from the time correction circuit (4, 4A), an output signal from the frame interpolation processing circuit (3, 3A) is output for a required number of frames. A PAL signal / CIF signal conversion circuit, which is configured to subtract one frame. 2. The PAL signal / CIF signal conversion circuit according to claim 1, wherein said first-stage memory (1, 1A) and said second-stage memory (2, 2A) are each constituted by a FIFO memory. 3. The memory (1, 1A) of the preceding stage is configured such that the number of delays is controlled by a write / read signal generated by a counter (5) of a variable carry-out signal output count value, 3. A PAL signal / CIF according to claim 2, wherein the delay number is controlled by a write / read signal generated by a counter (6) fixed to the carry-out signal output count value. Signal conversion circuit. 4. The frame interpolation processing circuit (3,3A)
A selector (7) for selecting either the L signal or the output signal of the pre-stage memory (1, 1A), and a multiplier (8) for multiplying the output signal from the selector (7) by a required interpolation coefficient
And a multiplier (9) for multiplying an output signal from the post-stage memory (2, 2A) by a required interpolation coefficient, and each of the multipliers (8,
ROM (10) that gives interpolation coefficients for weight distribution to 9),
An adder (11) for adding the output signals of the multipliers (8, 9) and outputting a signal having a temporary frame frequency higher than the CIF frame frequency. 2. The PAL signal / CIF signal conversion circuit according to 1. 5. A counter (12) for counting whether the time correction circuit (4, 4A) has reached a required number of frames for a frame synchronization signal having the temporary frame frequency, When it is detected that the number of frames has reached the number of frames, a gate circuit (13) for invalidating the frame synchronization signal in order to thin out one frame from the output signal of the frame interpolation processing circuit (3, 3A) is provided. The PAL signal / CIF according to claim 1, wherein the PAL signal / CIF is provided.
Signal conversion circuit. 6. A method for converting a CIF signal having a required CIF frame frequency into a PAL signal having a PAL frame frequency lower than the CIF frame frequency by superimposing one frame per required number of frames on the CIF signal. And a time correction circuit (21, 21A) for outputting a signal having a temporary frame frequency higher than the CIF frame frequency, and a pre-stage memory (22, 22A) for performing a periodic variable delay on the signal having the temporary frame frequency A selector (23) for selecting one of the signal having the provisional frame frequency and the output signal from the pre-stage memory (22, 22A); and a post-stage memory ( 24, 24A) and an output signal from the pre-stage memory (22, 22A) and an output signal from the post-stage memory (24, 24A). By applying between, characterized in that it is configured to include a frame interpolation process circuit for outputting a PAL signal (25, 25A) having the PAL frame frequency, PAL signal / CIF signal conversion circuit. 7. A pair of memories (26, 2A) for storing the CIF signal with a required time difference between the pair of memories (26, 2A).
7), a selector (28) for selecting and outputting an output from these memories (26, 27), and a counter (29) for calculating whether the required number of frames has been reached for the CIF signal.
When the counter (29) detects that the required number of frames has been reached, the selector (2)
7. The PAL signal / CIF according to claim 6, wherein by switching 8), the CIF signal is configured to overlap one frame for a required number of frames.
Signal conversion circuit. 8. The PAL signal / CIF signal conversion circuit according to claim 6, wherein said pre-stage memory (22, 22A) and said post-stage memory (23, 23A) are each constituted by a FIFO memory. 9. The write and read operation performed by the counter (30) in which the preceding-stage memory (22, 22A) has a variable carry-out signal output count value.
The delay number is controlled by the read signal, and the subsequent memory (24, 24A) is controlled by the write / read signal generated by the counter (31) having a fixed carry-out signal output count value. The PAL signal / CI according to claim 8, characterized in that:
F signal conversion circuit. 10. The frame interpolation processing circuit (25, 25A)
A multiplier (32) for multiplying an output signal from the pre-stage memory (22, 22A) by a required interpolation coefficient, and a post-stage memory (24, 24A)
Multiplier (3) that multiplies the output signal from
3), a ROM (34) for giving an interpolation coefficient for weight distribution to each of the multipliers (32, 33), and each of the multipliers (32, 33)
PAL having the PAL frame frequency
7. A PAL signal / CIF signal conversion circuit according to claim 6, comprising an adder (35) for outputting a signal.