JP2001217384A - Laminated semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a laminated semiconductor device with less restriction of size of semiconductor chips to be laminated, and also to provide such a semiconductor device. SOLUTION: In the method of manufacturing a laminated semiconductor device by stacking semiconductor chips 31 to 34 in plural stages, the plurality of semiconductor chips are stacked within accommodation substrates (1) having an internal hollow (2), the hollow 2 has spaces 21 to 24 for disposition of the chips which are sequentially spread from its bottom surface side, and the substrates 1 are previously integrally formed. In the laminated semiconductor device having the chips 31 to 34 laminated, the chips are formed as stacked within the hollow 2 of the substrates 1, and the hollow 2 has the spaces 31 to 34 sequentially spread from its bottom surface side, and the substrates are integrally formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a stacked semiconductor device and a stacked semiconductor device obtainable by the manufacturing method. The present invention particularly relates to a method for manufacturing a stacked semiconductor device in which a plurality of semiconductor chips are stacked,
And the stacked semiconductor device. The present invention can be used, for example, for an IC package obtained by stacking and assembling a large number of IC chips.

[0002]

2. Description of the Related Art Conventionally, due to demands for miniaturization and high density, a plurality of semiconductor chips are stacked to form a stacked semiconductor device. For example, an IC package in which a plurality of IC chips are stacked and assembled is known, and is called a stacked IC package or the like.

In a conventional IC package of this type, which is obtained by wire connection, another IC chip to be positioned above the lower IC chip is mounted on the lower IC chip.
It is fixed through an attach paste.
In this case, it is difficult to arrange the IC chip in the upper stage unless the size of the IC chip is in an area that does not contact the pads of the IC chip located in the lower stage. For this reason, there is a restriction on the size of the IC chips to be stacked, and there is a problem that the formation of a plurality of IC chips in a stacked IC package is greatly restricted.

[0004] Further, in the conventional multi-stage lamination in the manufacturing method of a stacked semiconductor device, layers of each stage are formed independently, and thereafter, bonding and assembling are performed using solder bonding or the like. That is, the joining step is necessary in another step. The bonding of the layers in each step required many steps.

[0005] In the conventional method, wires are connected to the substrate on the same surface of each IC, so that the wires are complicated and there is a problem of contact between the wires. That is, the wires are often arranged in multiple layers, for example, up and down, left and right, and the contact between the wires has increased the difficulty in manufacturing.

[0006]

SUMMARY OF THE INVENTION The present invention solves the above-mentioned problems and reduces the size of semiconductor chips to be stacked in a stacked semiconductor device. For example, a plurality of chips of different sizes can be used. It is an object of the present invention to provide a method of manufacturing a stacked semiconductor device that can be stacked in a plurality of stages or a plurality of stacked chips of the same size, and a stacked semiconductor device obtained by the method.

[0007]

A method of manufacturing a stacked semiconductor device according to the present invention is a method of manufacturing a stacked semiconductor device in which a plurality of semiconductor chips are stacked to form a stacked semiconductor device. A plurality of semiconductor chips are stacked in the storage substrate, and the hollow space of the substrate is such that the space for disposing the semiconductor chips is gradually increased from the bottom side, and the substrate is formed integrally in advance. Is what you do.

[0008] A stacked semiconductor device according to the present invention is a stacked semiconductor device formed by stacking a plurality of semiconductor chips in a plurality of stages. The stacked semiconductor device is formed by stacking a plurality of semiconductor chips in a hollow storage substrate. The hollow space of the substrate is characterized in that the semiconductor chip mounting space is gradually increased from the bottom side, and the substrate is formed integrally.

According to the present invention, since the substrates which are formed integrally in advance are used, it is not necessary to arrange and mount the substrates of each stage on which the semiconductor chips to be stacked are mounted for each stage.

In the substrate, the space in which the semiconductor chips are arranged is arranged such that the space in which the semiconductor chips are arranged is gradually widened from the bottom side, that is, for example, it is stepped. The upper surface of the lower chip can supply a free surface to the upper chip, so that there is almost no restriction on the chip size. In addition, there are almost no restrictions on pad areas and wires.

Further, since the semiconductor chip mounting space where the semiconductor chip of the substrate is housed is gradually increased from the bottom side (for example, a step-like shape), the wire can be prevented from being complicated, and the problem of contact between the wires can be prevented. Can be easily avoided.

Japanese Unexamined Patent Publication (Kokai) No. 6-037248 discloses a stacked semiconductor multi-chip module in which semiconductor chips are stacked. This module uses a heat conductive flexible substrate, and an internally housed substrate is used. It is not used, and the size of the arrangement surface of each semiconductor chip is the same. Japanese Patent Application Laid-Open No. 7-161924 describes a semiconductor device in which carriers on which semiconductor chips are mounted are stacked, but this also has a configuration in which carriers of the same size are stacked and assembled. JP-A-6-14
Japanese Patent Application Publication No. 0738 discloses a configuration in which carriers having semiconductor chips mounted in a concave mounting space are stacked in a plurality of stages. However, the carriers have the same shape and size. Is used. In each case, a substrate that is formed integrally in advance is not used, and the space for disposing the semiconductor chip of the substrate is not gradually widened from the bottom side.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The embodiments of the present invention will be further described below, and preferred specific examples will be described with reference to the drawings. Needless to say, the present invention is not limited to the illustrated embodiment.

In the present invention, a plurality of semiconductor chips are provided in the hollow space for accommodating the substrate. Such an internal storage type substrate may be appropriately referred to as an interposer substrate in this specification. In the present invention, the hollow space of the substrate is such that the semiconductor chip mounting space is gradually increased from the bottom side. In the practice of the present invention, the semiconductor chip mounting space depends on the number of semiconductor chips to be mounted. Stepping is a preferred form.

In the present invention, the substrate is integrally formed in advance, but it is sufficient that the substrate is integrally assembled at the time of mounting the semiconductor chip. The substrate may be bonded and fixed in advance and integrated.

In the present invention, the semiconductor chips are stacked in the hollow space for accommodating the substrate which is integrally formed in advance to form a stacked semiconductor device. This can be achieved by repeatedly stacking a plurality of semiconductor chips by repeatedly mounting and arranging semiconductor chips on the semiconductor device.

Since the present invention has the above-mentioned configuration, in implementing the present invention, for example, an IC
By performing die mounting, wire connection, resin sealing, and curing of the chip, the upper surface of the chip such as an IC located at the lower stage can supply a free surface to the chip located at the upper stage. Thus, the formation of a stacked semiconductor device can be achieved with almost no restrictions on the size of a chip such as an IC, pad area, and wires. For example, stacking of IC chips can be realized.

In the lamination, since a substrate which is integrally formed in advance is used, it is not necessary to dispose and mount substrates of each stage on which semiconductor chips to be laminated are mounted for each stage.

Further, as the substrate, the space in which the semiconductor chip is arranged and accommodated and the space in which the semiconductor chip is arranged is gradually widened (for example, in the form of a step) from the bottom side is used. The problem of contact between them can be easily avoided.

The substrate used in the present invention will be described with reference to FIGS. 2 and 3. FIG.
Internal storage type board (interposer board) shown in
Is an example of a case of three-stage stacking (three-stage chip stacking).

FIG. 2 is a perspective view showing the structure of an example of a substrate which can be used in the present invention. The substrate 1 in this example has a box shape with a hollow inside, and the hollow inside is a chip disposition space 2 for storing chips. The semiconductor chip mounting space 2 is sequentially formed from the bottom side.
The arrangement space is wide. As a specific example of this example, as shown in a partially cutaway view in which a chip and a wire are arranged in FIG.
The space for each chip is provided. In FIG. 3, reference numeral 3a denotes a lower semiconductor chip (for example, lower IC chip), 3b denotes a middle semiconductor chip (for example, middle IC chip), and 3c denotes an upper semiconductor chip. (For example, an upper IC chip). Code 4
Indicates a wire.

A pad 5 is shown in FIG. In particular,
Shows a second pad. The substrate 1 is formed in the above-described manner and is integrally formed in advance. A plurality (three in the example) of such a storage substrate 1
Each of the semiconductor chips 3a, 3b, and 3c is formed by stacking the semiconductor chips 3a, 3b, and 3c. By repeatedly mounting and arranging semiconductor chips for each stage, a plurality of semiconductor chips are stacked to obtain a stacked semiconductor device.

In the layered assembly, for each layer of each stage,
For example, when die mount, wire connection, resin sealing, and curing of an IC chip are performed, the upper surface of a chip such as an IC positioned at a lower level can supply a free surface to a chip positioned at an upper level. The formation of a stacked semiconductor device can be achieved with almost no restrictions on the size of chips such as ICs, pad areas, and wires. At this time, since a substrate that is integrally formed in advance is used, it is not necessary to arrange and mount the substrates of each stage on which the semiconductor chips to be stacked are mounted, for each stage. Since the substrate 1 is formed in a stepped shape, for example, the semiconductor chips 3a, 3b, 3c and the wires 4 can be arranged in an orderly manner as shown in the figure, so that complicated wires can be prevented, and the problem of contact between the wires can be avoided.

Next, preferred specific embodiments of the present invention will be described with reference to FIG.

Embodiment 1 Referring to FIG. FIG. 1 is a sectional view showing a completed package structure of a stacked semiconductor device according to the present embodiment.

The stacked semiconductor device according to the present invention is formed by stacking a plurality of semiconductor chips in a housing substrate. In this embodiment, a plurality of IC chips are stacked to form one package. FIG. 1 particularly shows a stacked package using four IC chips.

Referring to FIG. The substrate 1 in the present embodiment is formed by joining the substrates 101 to 106 and integrally. The inside of the substrate 1 is a storage space in which a plurality of semiconductor chips 31 to 34 can be arranged, and thus the substrate 1 forms an internal storage (interposer) substrate.

The substrate 1 has a storage space 21 on which a lowermost semiconductor chip 31 is disposed on a substrate 101 serving as a bottom plate.
Is laminated on the second substrate 102 from the bottom, which is opened at the center, and the third substrate 103, which is opened at the center on the storage space 22 for disposing the next semiconductor chip 32, is laminated thereon. On top of this, a fourth substrate 104 having a storage space 23 in which the next semiconductor chip 33 is disposed is opened at the center, and the next (topmost) semiconductor chip 34 is further placed thereon. A fifth substrate 104 having an opening at the center of the storage space 24 to be provided is laminated, and a substrate 105 forming a frame is laminated on the outermost surface to be integrally formed. Each of the substrates 101 to 106 includes a semiconductor chip 31 to 34
Is formed in a step-like form, and each of the storage spaces 21 to 24 is sequentially widened from the bottom side (the lower side in the figure). In this example, each of the semiconductor chips 31 to 34 is an IC chip.

In the present embodiment, the substrate 1 thus configured
Is configured such that the position of each step is substantially flush with the upper surface of the semiconductor chip to be mounted.
That is, the upper surface of the substrate 102 (the step formed by the substrate 102) is substantially flush with the upper surface of the semiconductor chip 31, and the upper surface of the substrate 103 (the step formed by the substrate 103)
Substantially on the same plane as the upper surface of the semiconductor chip 32,
The upper surface of the substrate 04 (the step formed by the substrate 104) is substantially flush with the upper surface of the semiconductor chip 33, and the upper surface of the substrate 105 (the step formed by the substrate 105) is substantially flush with the upper surface of the semiconductor chip 34. As in

The material of the substrate 1 is arbitrary, and may be, for example, a ceramic or an organic substrate.

The semiconductor chips 31 to 34 are mounted on the substrate 1 having the above-mentioned structure, which is formed integrally in advance, to form a stacked semiconductor device as follows.

A die paste 61 for bonding is applied to the bottom surface of the chip storage space 21 at the center of the substrate 102 (corresponding to the center of the upper surface of the substrate 101). Here is the semiconductor chip 31
(First IC chip) is mounted. After mounting,
The die paste 61 is cured, and the semiconductor chip 31 (first IC chip) is temporarily fixed.

The pads 71 of the semiconductor chip 31 (first IC chip) and the lands 81 of the substrate 102 are
Connect with 1. The sealing resin 91 is injected until the wires 41 (the wires of the first IC chip) are covered.
At this time, care should be taken that the sealing resin 91 does not rest on the upper surface of the substrate 103 thereon.

After the resin is injected, vacuum defoaming is performed, and the sealing resin 9 is removed.
1. Remove the air. After curing, the sealing resin 9
1 is pre-cured.

The upper surface of the sealing resin 91 becomes a mounting surface for the next semiconductor chip 32 (second IC chip). Substrate 1
Are formed in steps, so that the next semiconductor chip 32
The mounting surface of the (second IC chip) is the semiconductor chip 3
1 (first IC chip).

That is, the die paste 62 is applied to the center of the upper surface of the sealing resin 91. Here, the semiconductor chip 32 (second IC chip) is mounted. After the mounting, the die paste 62 is cured, and the semiconductor chip 32 is cured.
(Second IC chip) is temporarily fixed.

The pad 72 of the semiconductor chip 32 (second IC chip) and the land 82 of the substrate 103 are connected to the wire 4
Connect with 2. The sealing resin 92 is injected until the wires 42 (the wires of the second IC chip) are covered.
At this time, care should be taken that the sealing resin 92 does not rest on the upper surface of the substrate 104 thereon.

After injecting the resin, vacuum defoaming is performed, and the sealing resin 9 is removed.
2. Remove the air. After curing, the sealing resin 9
2 is temporarily cured.

In the same manner as the mounting operation of the semiconductor chip 32 (second IC chip), the semiconductor chips 33 and 34
(A third IC chip and a fourth IC chip) are mounted. That is, the same stacking operation as described above is repeated to form a stacked semiconductor device. Reference numerals 63 and 64 indicate die pastes for bonding the semiconductor chips 33 and 34, reference numerals 73 and 74 indicate pads of the semiconductor chips 33 and 34,
Lands of the substrates 104 and 105 at 83 and 84, 43 and 44
Indicates a wire, and 93 and 94 indicate a sealing resin.

After injecting the sealing resin 94 of the uppermost semiconductor chip 34 (fourth IC chip), the surface is squeezed. After the squeezing, the entire obtained package is cured to obtain a laminated IC package.

In FIG. 1, reference numeral 7 denotes a land, 8 denotes a reinforcing land, and 9 denotes a resist formed as required for processing.

According to the present embodiment, the storage cavities 21 to 24 in which the semiconductor chips 31 to 34 are disposed are sequentially widened from the bottom surface side, and the upper surface of the mounting position of the semiconductor chip is located at the upper position. By providing a free mounting surface for, the limitations on chip size can be almost eliminated. Therefore, a plurality of layers can be stacked without being affected by the size of the semiconductor chip (IC chip). Almost no restrictions on pad area or wire. It is easy to prevent the wires from being complicated, and the problem of contact between the wires can be avoided.

In addition, since the substrate 1 is formed integrally in advance, a complicated process for bonding the substrates when mounting the semiconductor chips 31 to 34 is not required. Multi-layer stacking of semiconductor chips such as IC chips is possible using a single integrated substrate, and the process of multi-layering can be simplified. Hierarchy of more than four levels can be easily achieved.

Further, it is possible to greatly reduce the mounting area on the mother board. By stacking a plurality of semiconductor chips (IC chips and the like), miniaturization of an IC package and the like can be achieved, which is useful for miniaturization of a mobile device and the like.

By laminating a plurality of semiconductor chips (IC chips and the like), there is also an effect that mother mounting processing cost can be reduced.

[0046]

As described above, according to the method for manufacturing a stacked semiconductor device and the stacked semiconductor device of the present invention, the size of semiconductor chips to be stacked is less restricted, and for example, a plurality of chips of different sizes are stacked. Can be stacked in a plurality of stages, or chips of the same size can be stacked in a plurality of stages, and the effect that multi-stage stacking can be easily realized can be exhibited.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a stacked semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram illustrating a configuration example of a substrate that can be used in a stacked semiconductor device according to the present invention.

FIG. 3 is a partial cross-sectional view illustrating a configuration example of a stacked semiconductor device according to the present invention.

[Explanation of symbols]

1 ... substrate, 2 ... hollow inside the substrate (chip arrangement space), 21 to 24 ... (each semiconductor chip) arrangement space, 31 to 34 ... semiconductor chip (IC chip), 4
1-44. Wire.

Claims (5)

[Claims] 1. A method for manufacturing a stacked semiconductor device, comprising stacking a plurality of semiconductor chips to form a stacked semiconductor device, comprising: stacking a plurality of semiconductor chips in an internal hollow storage substrate; A semiconductor chip mounting space is gradually increased from the bottom side, and the substrate is formed integrally in advance. 2. The method according to claim 1, wherein the semiconductor chip mounting space of the substrate has a stepped shape corresponding to the number of semiconductor chips to be mounted. 3. The method according to claim 1, wherein the step of arranging the plurality of semiconductor chips includes stacking the plurality of semiconductor chips by repeating mounting and arranging the semiconductor chips in each stage. A manufacturing method of the stacked semiconductor device according to the above. 4. A stacked semiconductor device formed by stacking a plurality of semiconductor chips in a plurality of stages, wherein a plurality of semiconductor chips are stacked in a storage substrate having a hollow inside, and the hollow of the substrate is: A stacked semiconductor device, wherein the space for disposing a semiconductor chip is gradually increased from the bottom side, and the substrate is formed integrally. 5. The stacked semiconductor device according to claim 4, wherein the semiconductor chip mounting space of the substrate has a stepped shape corresponding to the number of semiconductor chips to be mounted.