JP2001217268A - Semiconductor device and it manufacturing method - Google Patents

Semiconductor device and it manufacturing method

Info

Publication number
JP2001217268A
JP2001217268A JP2000028895A JP2000028895A JP2001217268A JP 2001217268 A JP2001217268 A JP 2001217268A JP 2000028895 A JP2000028895 A JP 2000028895A JP 2000028895 A JP2000028895 A JP 2000028895A JP 2001217268 A JP2001217268 A JP 2001217268A
Authority
JP
Japan
Prior art keywords
resin
filler
semiconductor element
semiconductor device
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000028895A
Other languages
Japanese (ja)
Inventor
Hiroyuki Hozoji
裕之 宝蔵寺
Madoka Kinoshita
円 木下
Yoshihide Yamaguchi
欣秀 山口
Shigeharu Tsunoda
重晴 角田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP2000028895A priority Critical patent/JP2001217268A/en
Publication of JP2001217268A publication Critical patent/JP2001217268A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/75Apparatus for connecting with bump connectors or layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/921Connecting a surface with connectors of different types
    • H01L2224/9212Sequential connecting processes
    • H01L2224/92122Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01322Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To prevent drop in the reliability of a semiconductor device due to bias of a filler in a liquid resin in the semiconductor device in which a semiconductor element is bonded to a wiring board by using bump electrodes, and in which the gap between the semiconductor element and the writing board is filled with the liquid containing the filler so as to be hardened. SOLUTION: The semiconductor element 1 is bonded to the wiring board 3 by using bump electrodes 5. Liquid resin 9 is filled between the semiconductor element 1 and the wiring board so as to be hardened. In order to reduce the coefficient of thermal expansion of the resin after its hardening, a filler 7 such as silica filler or the like is filled into a resin composition 6. The specific gravity of the filler 7 which is mixed with the resin composition 6 is made to agree nearly with the specific gravity of the resin composition 6, and the filler which has a hollow structure at a space rate of 40 to 60% is used. As a result, the filler in the resin is dispended uniformly into the resin without being unbalanced, and the reliability of the semiconductor device is enhanced.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体装置及びそ
の製造方法に係わり、特に半導体素子をはんだバンプ等
の突起電極を介して配線基板へ搭載後、半導体素子と配
線基板間の隙間を樹脂で充填する半導体装置およびその
製造方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a method for mounting a semiconductor element on a wiring board through a bump electrode such as a solder bump, and then filling a gap between the semiconductor element and the wiring board with a resin. The present invention relates to a semiconductor device to be filled and a manufacturing method thereof.

【0002】[0002]

【従来の技術】情報端末機器等の小型化、高機能化に伴
い、これに搭載する半導体装置も小型で高速の半導体装
置が要求されている。半導体素子をはんだバンプ等の突
起電極を介して配線基板(以下、基板と略称する)に接
続する方法は、半導体素子と基板との接続距離が短いた
め電気特性に優れ、搭載面積も小さいことから、小型の
情報端末機器等への適用が進んでいる。
2. Description of the Related Art As information terminal equipment and the like have become smaller and more sophisticated, there has been a demand for smaller and faster semiconductor devices to be mounted thereon. A method of connecting a semiconductor element to a wiring board (hereinafter, simply referred to as a substrate) via a bump electrode such as a solder bump is excellent in electric characteristics and a mounting area is small because a connection distance between the semiconductor element and the substrate is short. Application to small information terminal devices and the like is progressing.

【0003】この半導体装置は、はんだバンプ等の接続
部の長寿命化や、あるいは半導体素子から基板への熱伝
達を効率よく行うため、絶縁性あるいは高熱伝導性、ま
たはその両方の特性を有する樹脂を、半導体素子と基板
間の隙間に充填している。従って、この樹脂の充填を確
実且つ迅速に行うことが、半導体装置の信頼性向上と製
造効率向上の点でより重要となっている。
In order to extend the life of a connection portion such as a solder bump or to efficiently transfer heat from a semiconductor element to a substrate, this semiconductor device is made of a resin having an insulating property and / or a high thermal conductivity, or both. Is filled in the gap between the semiconductor element and the substrate. Therefore, it is more important to reliably and quickly fill the resin in terms of improving the reliability and manufacturing efficiency of the semiconductor device.

【0004】従来、このような半導体素子と基板間の樹
脂充填には、例えば特開平8−241900号公報等に開示さ
れているように液状の樹脂が用いられ、充填樹脂用シリ
ンジにより半導体素子近傍に供給し、毛管現象を利用し
て半導体素子と基板間を樹脂で充填する方法が採られて
いた。
Conventionally, for filling the resin between the semiconductor element and the substrate, a liquid resin is used as disclosed in, for example, Japanese Patent Application Laid-Open No. 8-241900. And filling the space between the semiconductor element and the substrate with a resin by utilizing the capillary phenomenon.

【0005】図4は従来の半導体装置の樹脂充填方法を
示したもので、半導体素子1は、はんだバンプ等からな
る突起状電極5により基板3上の電極4と半導体素子上
の電極2に接続されている。この半導体素子1と基板3
間にシリンジ8を用いて液状の充填樹脂9を充填する。
樹脂の充填が完了した後、この半導体装置はオーブン等
で高温に保持され、充填樹脂の硬化を行う。
FIG. 4 shows a conventional resin filling method for a semiconductor device. A semiconductor element 1 is connected to an electrode 4 on a substrate 3 and an electrode 2 on the semiconductor element by a protruding electrode 5 made of a solder bump or the like. Have been. The semiconductor element 1 and the substrate 3
The liquid filling resin 9 is filled using the syringe 8 between them.
After the filling of the resin is completed, the semiconductor device is kept at a high temperature in an oven or the like to cure the filling resin.

【0006】[0006]

【発明が解決しようとする課題】前記図4に示した従来
の半導体装置を製造するに際し、半導体素子1と基板3
間に充填する樹脂9には、通常樹脂の熱膨張係数を小さ
くし半導体素子1と基板3との接続部に発生する熱応力
を低減するため、シリカ粉からなる充填剤を樹脂成分に
対し55〜70重量%程度配合している。
In manufacturing the conventional semiconductor device shown in FIG. 4, a semiconductor element 1 and a substrate 3 are manufactured.
In order to reduce the thermal expansion coefficient of the resin 9 and to reduce the thermal stress generated at the connection portion between the semiconductor element 1 and the substrate 3, a filler made of silica powder is added to the resin 9 with respect to the resin component. About 70% by weight is blended.

【0007】樹脂の硬化過程では充填樹脂中の樹脂粘度
が低下し、樹脂と充填剤の比重差により配合している充
填剤が下方へ沈降しやすいという問題がある。このよう
な状態で樹脂を硬化すると充填剤が樹脂中に偏って存在
することになる。
During the curing process of the resin, there is a problem that the viscosity of the resin in the filler resin decreases, and the filler compounded tends to settle down due to the difference in specific gravity between the resin and the filler. When the resin is cured in such a state, the filler is present unevenly in the resin.

【0008】すなわち、樹脂中の充填剤の配合状態が不
均一になると、本来樹脂に充填剤を配合し熱膨張係数を
小さくして実装状態における半導体素子とこれを搭載し
た基板との接合部等に発生する応力を低減させ、接続寿
命等を向上させる効果が不十分となり、半導体装置の信
頼性を著しく低下させる。そこで、樹脂の硬化過程での
充填剤の沈降防止が強く望まれていた。
That is, when the compounding state of the filler in the resin becomes non-uniform, the filler is originally mixed with the resin to reduce the coefficient of thermal expansion so that the junction between the semiconductor element in the mounted state and the substrate on which the semiconductor element is mounted, etc. And the effect of improving the connection life and the like becomes insufficient, thereby significantly reducing the reliability of the semiconductor device. Therefore, it has been strongly desired to prevent the filler from settling during the curing process of the resin.

【0009】したがって、本発明の目的は、上記従来の
問題点を解消することにあり、その第1の目的は硬化樹
脂中に充填剤が均一に分散されている半導体装置を提供
することにあり、第2の目的は樹脂の充填時間を短縮し
作業性を向上させ得る半導体装置の製造方法を提供する
ことにある。
Therefore, an object of the present invention is to solve the above-mentioned conventional problems, and a first object of the present invention is to provide a semiconductor device in which a filler is uniformly dispersed in a cured resin. A second object is to provide a method of manufacturing a semiconductor device capable of shortening a resin filling time and improving workability.

【0010】[0010]

【課題を解決するための手段】充填剤の沈降を防止する
方法として、充填樹脂を構成する樹脂の粘度を高くする
方法や、配合する充填剤の粒子径を小さくする方法があ
る。しかし、充填樹脂中の樹脂粘度を高くすると充填樹
脂の粘度が高くなり、半導体素子とこれを搭載する基板
間に樹脂を充填する時間が長くなり、作業性が著しく低
下する。
As a method of preventing the settling of the filler, there are a method of increasing the viscosity of the resin constituting the filling resin and a method of reducing the particle size of the filler to be mixed. However, when the viscosity of the resin in the filling resin is increased, the viscosity of the filling resin increases, and the time for filling the resin between the semiconductor element and the substrate on which the semiconductor element is mounted becomes longer, thereby significantly reducing the workability.

【0011】また、一般に充填剤の配合量が一定で粒子
径を小さくした場合も充填用樹脂の粘度が高くなる傾向
があり、前述したように作業性が著しく低下する。
In general, even when the amount of the filler is constant and the particle diameter is reduced, the viscosity of the filling resin tends to increase, and the workability is significantly reduced as described above.

【0012】そこで、本発明者等は、上記目的を達成す
べく種々詳細に実験検討を行ったところ、このように作
業性を低下させずに充填樹脂中の充填剤の沈降を防止す
るためには、充填樹脂中の樹脂の密度と充填剤の見かけ
の密度との差を極力小さくすることが有効であると云う
知見を得た。
The inventors of the present invention have conducted various experiments and studies in order to achieve the above object, and have found that in order to prevent the settling of the filler in the filling resin without reducing the workability as described above. Has found that it is effective to minimize the difference between the density of the resin in the filling resin and the apparent density of the filler.

【0013】充填剤の見かけの密度を小さくするには充
填剤の材質を密度の小さいものに変える方法もあるが、
この場合には充填樹脂の熱膨張係数が大きくなり、この
樹脂組成物で封止した半導体装置の温度サイクル試験等
における接続信頼性を低下させる可能性がある。
In order to reduce the apparent density of the filler, there is a method of changing the material of the filler to a material having a lower density.
In this case, the thermal expansion coefficient of the filling resin increases, and there is a possibility that the connection reliability in a temperature cycle test or the like of the semiconductor device sealed with this resin composition may be reduced.

【0014】そこで、樹脂組成物の熱膨張係数に対する
影響が少なく、充填材の沈降を防止するには、充填用樹
脂に配合する充填剤が気泡を含んだものを用いることに
より上記課題が解決可能となることが明らかになった。
Therefore, in order to prevent the sedimentation of the filler, since the influence on the thermal expansion coefficient of the resin composition is small, the above-mentioned problem can be solved by using a filler containing air bubbles in the filler resin. It became clear that.

【0015】本願によって開示される発明のうち、代表
的なものの概要を簡単に説明すれば下記の通りである。
The outline of a typical invention among the inventions disclosed by the present application will be briefly described as follows.

【0016】すなわち、本発明の半導体装置の特徴とす
るところは、半導体素子を配線基板上に突起電極を介し
て搭載接続し、この半導体素子と配線基板間の隙間に充
填剤を含む樹脂を充填した構造を有する半導体装置であ
って、樹脂中の充填剤を樹脂の比重にほぼ均しい中空構
造を有するもので構成し樹脂中に均一に分散せしめたこ
とにある。中空構造とは、充填剤が気泡を含んだものを
意味している。
That is, the semiconductor device of the present invention is characterized in that a semiconductor element is mounted and connected on a wiring board via a protruding electrode, and a resin containing a filler is filled in a gap between the semiconductor element and the wiring board. A semiconductor device having a structure as described above, wherein the filler in the resin has a hollow structure substantially equal to the specific gravity of the resin, and is uniformly dispersed in the resin. The hollow structure means that the filler contains bubbles.

【0017】この種の半導体装置に充填する樹脂の比重
は、樹脂の種類にもよるが一般に0.9〜1.0程度で
ある。それに対して、従来の代表的な充填剤である例え
ばシリカ粒子の場合、比重は2.0〜2.2であり空隙
がほとんど無い(空間率≒0%)。
The specific gravity of the resin filled in this type of semiconductor device depends on the type of the resin, but is generally about 0.9 to 1.0. On the other hand, in the case of, for example, silica particles, which are a conventional typical filler, the specific gravity is 2.0 to 2.2, and there is almost no void (void ratio ≒ 0%).

【0018】しかし、本発明に使用する充填剤は、前述
の通り樹脂の比重にほぼ均しい中空構造を有している。
樹脂の比重にほぼ均しいとは、0.8〜1.1程度の比
重を有していることを意味している。
However, the filler used in the present invention has a hollow structure almost equal to the specific gravity of the resin as described above.
Being substantially equal to the specific gravity of the resin means having a specific gravity of about 0.8 to 1.1.

【0019】また、本発明の半導体装置の製造方法の特
徴とするところは、半導体素子を配線基板上に突起電極
を介して搭載接続する工程と、この配線基板上に搭載接
続された半導体素子と配線基板との隙間に充填剤を配合
した液状樹脂を注入し隙間を樹脂で充填する工程と、充
填した液状樹脂を硬化する工程とを含む半導体装置の製
造方法であって、上記充填剤を配合した液状樹脂を注入
し隙間を樹脂で充填する工程においては、充填剤として
樹脂の比重にほぼ均しい中空構造を有する充填剤を樹脂
中に配合し、均一に分散混合して液状樹脂を調製する工
程を有することにある。
Further, the method of manufacturing a semiconductor device according to the present invention is characterized in that a semiconductor element is mounted and connected on a wiring board via a protruding electrode, and the semiconductor element mounted and connected on the wiring board is connected to a semiconductor device. A method of manufacturing a semiconductor device, comprising: a step of injecting a liquid resin containing a filler into a gap between the wiring board and filling the gap with the resin; and a step of curing the filled liquid resin. In the step of injecting the filled liquid resin and filling the gap with the resin, a filler having a hollow structure almost equal to the specific gravity of the resin is blended into the resin as a filler, and uniformly dispersed and mixed to prepare a liquid resin. It has a process.

【0020】[0020]

【発明の実施の形態】以下、図面を参照しながら本発明
を更に具体的に説明する。図1は、本発明に係る一実施
の形態となる半導体装置の断面概略を示したものであ
る。本発明の半導体装置は、半導体素子1に設けられた
電極2と基板3に設けた電極4が、はんだや金あるいは
導電性樹脂等からなる接続端子5により電気的に接続さ
れ、半導体素子1と基板3の隙間には樹脂成分6に充填
剤7を配合した液状樹脂9が例えばシリンジで注入充填
され、これを硬化して樹脂中に充填剤が均一に分散され
た樹脂充填層を形成している。
Hereinafter, the present invention will be described more specifically with reference to the drawings. FIG. 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention. In the semiconductor device of the present invention, the electrode 2 provided on the semiconductor element 1 and the electrode 4 provided on the substrate 3 are electrically connected by a connection terminal 5 made of solder, gold, conductive resin, or the like. A liquid resin 9 in which a filler 7 is blended with a resin component 6 is injected and filled into the gaps between the substrates 3 by, for example, a syringe, and cured to form a resin filled layer in which the filler is uniformly dispersed in the resin. I have.

【0021】電気的な接続は、上述したように接続端子
5としては金、はんだ、銀の充填剤を配合した導電性樹
脂、あるいは球状の高分子表面をNi等の導体金属で被覆
したものや、銅等の金属球が用いられる。
For the electrical connection, as described above, the connection terminal 5 may be a conductive resin containing a filler of gold, solder or silver, a spherical polymer surface coated with a conductive metal such as Ni, or the like. And a metal sphere such as copper.

【0022】電極4は、一般的には銅配線表面をニッケ
ル/金のメッキを施したものが用いられるが、接続端子
5の材質によっては錫メッキや銅の電極上をフラックス
で塗布する方式や、予めはんだをコーティングしておく
方式等も適用可能である。
The electrode 4 generally has a copper wiring surface plated with nickel / gold. Depending on the material of the connection terminal 5, tin plating or a method of coating the copper electrode with a flux may be used. Alternatively, a method of pre-coating solder may be applied.

【0023】半導体素子1と基板3間の隙間を充填する
樹脂9には、接続端子部分に発生する応力を低減させる
ことを目的に樹脂の熱膨張係数を小さくするための例え
ばシリカ(二酸化珪素)、アルミナ、窒化ホウ素等から
なる無機系の充填剤7が予め配合されており、この充填
剤が半導体素子1と基板3間に充填した樹脂中に均一に
分散している。
The resin 9 filling the gap between the semiconductor element 1 and the substrate 3 includes, for example, silica (silicon dioxide) for reducing the coefficient of thermal expansion of the resin for the purpose of reducing the stress generated in the connection terminal portion. An inorganic filler 7 made of, for example, alumina, boron nitride, or the like is previously mixed, and the filler is uniformly dispersed in the resin filled between the semiconductor element 1 and the substrate 3.

【0024】上記充填剤は、球形、角形いずれの粒子形
状のものを使用しても良いが、充填剤の配合量を増加さ
せても樹脂の流動性を低下させないためには球形のもの
を用いるほうが望ましい。さらに充填剤が樹脂中に均一
に分散し、かつ半導体装置の製造工程で樹脂成分と充填
剤が分離しないようにするために、充填剤は気泡を含み
樹脂の比重にほぼ均しい中空構造を有している。
The filler may be in the form of particles having any of a spherical shape and a square shape. However, a spherical shape is used in order not to decrease the fluidity of the resin even if the amount of the filler is increased. Is more desirable. In addition, the filler has a hollow structure that contains air bubbles and is almost equal to the specific gravity of the resin in order to disperse the filler uniformly in the resin and to prevent the resin component and the filler from separating during the semiconductor device manufacturing process. are doing.

【0025】充填剤中の空間の割合(空間率)は、空間
の占める割合が少ないと充填剤の沈降を防止する効果が
不充分であり、空間の占める割合が多いと半導体装置の
製造工程で充填剤が上方に浮いてしまい充填剤に偏りが
生じるので、概ね空間率40〜60%が望ましい。
When the proportion of the space in the filler (the porosity) is small, the effect of preventing the settling of the filler is insufficient if the proportion of the space is small, and if the proportion of the space is large, the proportion in the semiconductor device manufacturing process is low. Since the filler floats upward and the bias is generated in the filler, a porosity of approximately 40 to 60% is desirable.

【0026】半導体素子表面の電極2は半導体素子内部
の回路へ、基板3上の電極4は基板の内部とそれぞれ接
続されている。半導体素子1と基板3の隙間を埋める樹
脂成分6としては、上記充填剤7を配合したもので、一
般にエポキシ樹脂、フェノール樹脂、ポリイミド樹脂等
の熱硬化性樹脂、さらにはこの熱硬化性樹脂にシリコー
ン、ポリエチレンテレフタレート、ポリブタジエン等の
熱可塑性成分を配合したものが使用される。
The electrode 2 on the surface of the semiconductor element is connected to a circuit inside the semiconductor element, and the electrode 4 on the substrate 3 is connected to the inside of the substrate. As the resin component 6 that fills the gap between the semiconductor element 1 and the substrate 3, the above-mentioned filler 7 is blended. Generally, a thermosetting resin such as an epoxy resin, a phenol resin, and a polyimide resin, and furthermore, A mixture containing a thermoplastic component such as silicone, polyethylene terephthalate, or polybutadiene is used.

【0027】樹脂成分6に対する充填剤7の好ましい配
合割合は、通常、22〜42重量%程度である。
The preferred compounding ratio of the filler 7 to the resin component 6 is usually about 22 to 42% by weight.

【0028】液状樹脂9の調製は、上記配合割合で樹脂
成分と充填剤とを配合し、これらを周知の撹拌機で十分
にかきまぜ樹脂中に充填剤をよく分散させる。充填剤の
材質もしくは配合量により周知の分散剤を添加して分散
性を高めるか、また、予め充填剤の表面を分散剤で表面
処理してもよい。さらには、樹脂中に臭素化エポキシや
Sb23等の難燃剤を添加することもできる。
For the preparation of the liquid resin 9, the resin component and the filler are mixed in the above mixing ratio, and these are sufficiently stirred by a well-known stirrer to disperse the filler well in the resin. A well-known dispersant may be added depending on the material or the amount of the filler to enhance the dispersibility, or the surface of the filler may be previously treated with a dispersant. Further, a flame retardant such as brominated epoxy or Sb 2 O 3 can be added to the resin.

【0029】[0029]

【実施例】図2及び図2Aは、図1に示した半導体装置
の製造工程の概略を示したものである。図2(a)では、
半導体素子1の電極2に接続端子となる突起電極(はん
だ)5を形成したものを基板3上に搭載し、これを図2
(b)に示すように赤外線リフロ、ベーパリフロ等によ
り、はんだを溶融し基板3の電極4と接続する。
FIG. 2 and FIG. 2A schematically show a manufacturing process of the semiconductor device shown in FIG. In FIG. 2A,
A semiconductor element 1 having an electrode 2 on which a protruding electrode (solder) 5 serving as a connection terminal is formed is mounted on a substrate 3.
As shown in (b), the solder is melted by infrared reflow, vapor reflow, or the like, and connected to the electrode 4 of the substrate 3.

【0030】その後、図2(c)に示すように、シリンジ
8により予め調製した液状樹脂9を半導体素子1と基板
3の隙間に注入充填する。この充填は、室温でも良い
し、基板や半導体素子あるいは樹脂を予め適当な温度に
加熱して樹脂の充填を行うことも可能である。
Thereafter, as shown in FIG. 2C, a liquid resin 9 prepared in advance by a syringe 8 is injected and filled into the gap between the semiconductor element 1 and the substrate 3. This filling may be performed at room temperature, or the filling of the resin may be performed by heating the substrate, the semiconductor element or the resin to an appropriate temperature in advance.

【0031】図2A(d)は、半導体素子1と基板3の隙
間に液状樹脂9を完全に充填した状態を示している。こ
の後、図2A(e)に示したように、高温槽10内でヒータ
ー11に通電し、樹脂を加熱して硬化を行う。樹脂中に配
合されたシリカ(二酸化珪素)、アルミナ、窒化ホウ素
等の充填剤の比重は、これらを含まない樹脂とほぼ同等
であり、硬化過程で充填剤が沈降や浮上を起こさず樹脂
の硬化反応が進行し、最終形態である図2A(f)が得ら
れる。
FIG. 2A (d) shows a state in which the gap between the semiconductor element 1 and the substrate 3 is completely filled with the liquid resin 9. Thereafter, as shown in FIG. 2A (e), the heater 11 is energized in the high-temperature bath 10 to heat and cure the resin. The specific gravity of fillers such as silica (silicon dioxide), alumina, boron nitride, etc., incorporated in the resin is almost the same as that of resins that do not contain them, and the resin hardens without causing settling or floating during the curing process. The reaction proceeds, and the final form, FIG. 2A (f), is obtained.

【0032】なお、図2では樹脂を注入充填するに際
し、半導体素子1と基板3の隙間を水平状態としたが、
垂直状態で行ってもよい。樹脂の注入充填に時間がかか
ると、樹脂の充填過程で充填剤の移動が起こり、半導体
素子表面に存在する充填剤量に大きな偏りが生じる場合
がある。そこで図3に示したように、半導体素子と基板
を立て隙間を垂直状態として樹脂の注入充填を行えば、
注入時間が短縮され充填剤の移動に偏りが少なくなり信
頼性が向上する。
In FIG. 2, the gap between the semiconductor element 1 and the substrate 3 is horizontal when the resin is injected and filled.
It may be performed in a vertical state. If it takes a long time to inject and fill the resin, the filler moves during the resin filling process, which may cause a large unevenness in the amount of the filler present on the surface of the semiconductor element. Therefore, as shown in FIG. 3, if the semiconductor element and the substrate are set up and the gap is set vertically, and the resin is injected and filled,
The injection time is shortened, the unevenness of the movement of the filler is reduced, and the reliability is improved.

【0033】さらに、本発明の方法では、図4に示した
ように、基板の両面に半導体素子を搭載し、樹脂で半導
体素子と基板間を充填する場合においても、両面の樹脂
充填を行ってから樹脂の硬化を行うことが可能であり、
この場合も充填樹脂中の充填剤に偏り等が生じない。
Further, according to the method of the present invention, as shown in FIG. 4, when semiconductor elements are mounted on both sides of a substrate and the space between the semiconductor element and the substrate is filled with resin, the resin is filled on both sides. It is possible to cure the resin from
Also in this case, the filler in the filler resin does not become uneven.

【0034】一方、図5及び図6は、比較例となる従来
の充填剤7を配合した液状樹脂9を半導体素子1と基板
3の隙間に注入し硬化を行ったものである。図5は半導
体素子1が上側になるようにして樹脂6の硬化を行った
場合であり、樹脂中の充填剤7は硬化時に下側となる基
板3側に偏った状態となる。
On the other hand, FIGS. 5 and 6 show a comparative example in which a liquid resin 9 containing a conventional filler 7 is injected into a gap between the semiconductor element 1 and the substrate 3 and cured. FIG. 5 shows a case where the resin 6 is cured such that the semiconductor element 1 is on the upper side, and the filler 7 in the resin is biased toward the lower substrate 3 during curing.

【0035】また、図6は基板3の両面に半導体素子1
を搭載し、図5の場合と同様の従来の充填剤7を配合し
た液状樹脂9を用いて樹脂充填を行った後、樹脂の硬化
を行ったものであるが、樹脂6の硬化過程で充填剤7が
沈降し、基板3下側の充填樹脂部分では半導体素子1側
に充填剤7が偏り、基板3上面の樹脂部分では基板3側
に充填剤7が偏っている。
FIG. 6 shows a semiconductor device 1 on both surfaces of a substrate 3.
The resin is filled using a liquid resin 9 containing the same conventional filler 7 as in the case of FIG. 5, and then the resin is cured. The filler 7 is settled, and the filler 7 is biased toward the semiconductor element 1 in the filled resin portion below the substrate 3, and is biased toward the substrate 3 in the resin portion on the upper surface of the substrate 3.

【0036】表1は、各種充填用樹脂を使用し温度サイ
クル試験を行った信頼性評価結果について、本実施例を
比較例(従来例)と対比して纏めたものである。
Table 1 summarizes the results of a reliability evaluation of a temperature cycle test using various filling resins, in comparison with a comparative example (conventional example).

【0037】[0037]

【表1】 [Table 1]

【0038】各実施例及び各比較例ともに、充填用液状
樹脂9の調製は、樹脂成分6としてビスフェノールタイ
プのエポキシ樹脂(比重0.90〜0.99)、無水酸硬化剤を
当量配合したものに、イミダゾール系硬化促進剤を1重
量%配合し、更に充填剤7として平均粒子径5μmの球
状溶融シリカ粉を配合して作成した。各実施例及び比較
例に使用したシリカ粉の空間率及び配合量は表中に表示
した。
In each of the examples and comparative examples, the filling liquid resin 9 was prepared by mixing an imidazole-based resin with an equivalent amount of a bisphenol type epoxy resin (specific gravity 0.90 to 0.99) and an acid anhydride curing agent as the resin component 6. 1% by weight of a curing accelerator was blended, and spherical fused silica powder having an average particle diameter of 5 μm was further blended as a filler 7 to prepare the composition. The porosity and amount of the silica powder used in each of the examples and comparative examples are shown in the table.

【0039】基板3としては通常のガラスエポキシ基板
を、半導体素子1としては10mm角で周囲に500μmピッチ
で400ピン並んだものを使用し、基板3と半導体素子1
の接続には接続用端子5として高さ300μmの錫−鉛共晶
はんだを使用した。
As the substrate 3, a normal glass epoxy substrate is used. As the semiconductor element 1, a 10 mm square substrate having 400 pins arranged at a pitch of 500 μm is used.
For the connection, a tin-lead eutectic solder having a height of 300 μm was used as the connection terminal 5.

【0040】樹脂の充填は、図2(c)の工程図に示し
た方法で行った。すなわち、予め充填剤7を配合した液
状樹脂9を各々調製しておき、シリンジ8を用い約75℃
に加熱した熱板上に基板3を置いて半導体素子と基板の
隙間に注入充填した。
The resin was filled by the method shown in the process diagram of FIG. That is, a liquid resin 9 in which a filler 7 is previously blended is prepared in advance, and a syringe 8 is used at about 75 ° C.
The substrate 3 was placed on a hot plate heated to a temperature of 5 ° C., and was filled into the gap between the semiconductor element and the substrate.

【0041】実施例1〜3は、それぞれ異なる空間率を
有する中空の充填剤7を液状樹脂中に配合したもので、
空間率は実施例1が50%(比重1.0〜1.1)、実施例2
が40%(比重1.1〜1.2)、実施例3が60%(比重0.9
〜1.0)である。樹脂の硬化は、図2A(e)に示したよ
うに、150℃の高温槽10で2時間行った。
In Examples 1 to 3, hollow fillers 7 having different void ratios were mixed in a liquid resin.
Example 1 had a porosity of 50% (specific gravity 1.0 to 1.1), and Example 2
Is 40% (specific gravity 1.1 to 1.2), and Example 3 is 60% (specific gravity 0.9).
~ 1.0). The curing of the resin was performed in a high-temperature bath 10 at 150 ° C. for 2 hours as shown in FIG. 2A (e).

【0042】比較例1〜3も充填剤の空間率及び配合量
を除き上記実施例と同一条件で樹脂を充填したが、比較
例1は充填剤に空間が無いもの(空間率0%/比重2.
2)、比較例2は空間率20%(比重1.6〜1.8)、比較例
3は空間率75%(比重0.6)のものを配合した樹脂を用
いて充填した。
In Comparative Examples 1 to 3, the resin was filled under the same conditions as in the above Examples except for the porosity and blending amount of the filler. In Comparative Example 1, the filler had no space (0% porosity / specific gravity). 2.
2), Comparative Example 2 was filled with a resin having a porosity of 20% (specific gravity 1.6 to 1.8), and Comparative Example 3 was filled with a resin having a porosity of 75% (specific gravity 0.6).

【0043】樹脂硬化後の半導体装置は、−55℃/10
分、125℃/10分の温度サイクル試験(500サイクル、100
0サイクル、2000サイクル)を行い、各サイクル試験後に
おける半導体素子1と基板3の接続部の導通の有無を調
べた。
The semiconductor device after the resin curing is -55 ° C./10
Min, 125 ° C / 10 min temperature cycle test (500 cycles, 100
(0 cycles, 2000 cycles), and after each cycle test, the connection of the semiconductor element 1 and the substrate 3 was checked for conduction.

【0044】表1の結果について説明すると、実施例、
比較例とも充填剤中の空間率の有無にかかわらず充填時
間は45秒(s)であり、空間率による差は見られなかっ
た。しかし、樹脂中の充填剤の偏り状態と温度サイクル
試験に大きな差が生じた。
The results in Table 1 will be described.
In the comparative examples, the filling time was 45 seconds (s) regardless of the presence or absence of the porosity in the filler, and there was no difference due to the porosity. However, there was a large difference between the bias state of the filler in the resin and the temperature cycle test.

【0045】すなわち、本実施例の空間率40〜60%の場
合、充填剤の偏り(沈降)は見られず、温度サイクル試験
も試験個数10中0(表中1/10と表示)であり、極め
て信頼性が高く良好な結果が得られた。一方、比較例の
場合にはいずれも、2000サイクルの試験で1/10と導
通の無い不良品が発生した。
That is, in the case of the porosity of 40 to 60% in this embodiment, no bias (settling) of the filler was observed, and the temperature cycle test was 0 out of 10 (shown as 1/10 in the table). Very high reliability and good results were obtained. On the other hand, in the case of the comparative examples, a defective product having no conduction, which was 1/10 in the 2000-cycle test, occurred.

【0046】比較例においてはいずれも樹脂中の充填剤
の分散性が劣り、偏りが認められた。比較例1の空間率
0%の場合は勿論のこと、比較例2の20%と小さい場合
には、充填剤は下側(基板上)に沈降し、比較例3のよ
うに逆に空間率が75%と大きい場合には充填剤が上側
(半導体素子側)に浮きやすい傾向が見られる。
In each of the comparative examples, the dispersibility of the filler in the resin was inferior, and unevenness was observed. When the void ratio is 0% in Comparative Example 1, and when the void ratio is as small as 20% in Comparative Example 2, the filler settles down (on the substrate). Is higher than 75%
(Semiconductor element side) tend to float.

【0047】表1から明らかなように本実施例の場合、
接続寿命が長く、充填剤の偏りが小さく、樹脂中に均一
によく分散していることが確認できる。
As is clear from Table 1, in the case of this embodiment,
It can be confirmed that the connection life is long, the bias of the filler is small, and the filler is uniformly and well dispersed in the resin.

【0048】接続寿命が長いと云うことは、充填剤を均
一に分散させることにより熱膨張係数を小さくして実装
状態における半導体素子とこれを搭載した基板との接合
部等に発生する応力を十分に低減し得る効果を有してい
ることを示している。
The fact that the connection life is long means that the filler which is uniformly dispersed reduces the coefficient of thermal expansion to sufficiently reduce the stress generated at the junction between the semiconductor element in the mounted state and the substrate on which it is mounted. It has an effect that can be reduced.

【0049】また、本発明の製造方法によれば、液状樹
脂中に充填剤が均一に分散していることから、従来のよ
うに沈降する心配がないので半導体素子と基板との隙間
に液状樹脂を注入充填する工程の時間管理が容易とな
り、高信頼性の半導体装置を製造する歩留まりが格段に
向上する。
Further, according to the production method of the present invention, since the filler is uniformly dispersed in the liquid resin, there is no need to worry about sedimentation unlike the prior art, so that the liquid resin is filled in the gap between the semiconductor element and the substrate. , And the yield of manufacturing highly reliable semiconductor devices is significantly improved.

【0050】[0050]

【発明の効果】以上詳述したように、本発明により、半
導体素子と基板との隙間に充填する樹脂中に充填剤を均
一に分散すると云う所期の目的を達成することができ
た。すなわち、半導体素子をはんだバンプ等の突起電極
を介して配線基板へ搭載後、半導体素子と配線基板間の
隙間を樹脂で充填する半導体装置の接続信頼性を著しく
向上させることができる。
As described in detail above, according to the present invention, the intended object of uniformly dispersing the filler in the resin filling the gap between the semiconductor element and the substrate can be achieved. That is, the connection reliability of the semiconductor device in which the semiconductor element is mounted on the wiring board via the bump electrode such as a solder bump and then the gap between the semiconductor element and the wiring board is filled with the resin can be remarkably improved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施の形態を説明する断面概略図。FIG. 1 is a schematic cross-sectional view illustrating an embodiment of the present invention.

【図2】本発明の一実施例となる半導体装置の製造工程
を示す概略図。
FIG. 2 is a schematic view showing a manufacturing process of a semiconductor device according to one embodiment of the present invention.

【図2A】本発明の一実施例となる半導体装置の製造工
程を示す概略図。
FIG. 2A is a schematic view showing a manufacturing process of a semiconductor device according to one embodiment of the present invention;

【図3】本発明の他の実施例となる樹脂充填工程図。FIG. 3 is a resin filling step diagram according to another embodiment of the present invention.

【図4】従来の方式による樹脂充填工程概略図。FIG. 4 is a schematic view of a resin filling process according to a conventional method.

【図5】比較例となる樹脂充填の断面観察図。FIG. 5 is a cross-sectional observation view of resin filling as a comparative example.

【図6】他の比較例となる樹脂充填の断面観察図。FIG. 6 is a cross-sectional observation view of resin filling as another comparative example.

【符号の説明】[Explanation of symbols]

1…半導体素子、 2…半導体素子上の電極、 3…配線基板、 4…配線基板上の電極、 5…接続用端子(突起電極) 6…樹脂、 7…充填剤、 8…シリンジ、 9…液状樹脂、 10…高温槽、 11…ヒーター。 DESCRIPTION OF SYMBOLS 1 ... Semiconductor element, 2 ... Electrode on a semiconductor element, 3 ... Wiring board, 4 ... Electrode on a wiring board, 5 ... Connection terminal (projection electrode) 6 ... Resin, 7 ... Filler, 8 ... Syringe, 9 ... Liquid resin, 10… high temperature bath, 11… heater.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 山口 欣秀 神奈川県横浜市戸塚区吉田町292番地 株 式会社日立製作所生産技術研究所内 (72)発明者 角田 重晴 神奈川県横浜市戸塚区吉田町292番地 株 式会社日立製作所生産技術研究所内 Fターム(参考) 5F044 LL01 RR17 5F061 AA01 BA03 CA04 CB02  ──────────────────────────────────────────────────続 き Continued on the front page (72) Yoshihide Yamaguchi, 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Research Institute of Production Technology, Hitachi, Ltd. (72) Shigeharu Tsunoda 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Address F-term in Hitachi, Ltd. Production Engineering Laboratory (reference) 5F044 LL01 RR17 5F061 AA01 BA03 CA04 CB02

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】半導体素子を配線基板上に突起電極を介し
て搭載接続し、前記半導体素子と配線基板間の隙間に充
填剤を含む樹脂を充填した構造を有する半導体装置であ
って、前記樹脂中の充填剤を樹脂の比重にほぼ均しい中
空構造を有するもので構成し樹脂中に均一に分散せしめ
たことを特徴とする半導体装置。
1. A semiconductor device having a structure in which a semiconductor element is mounted and connected on a wiring board via a protruding electrode, and a gap between the semiconductor element and the wiring board is filled with a resin containing a filler. A semiconductor device comprising a filler having a hollow structure substantially equal to the specific gravity of a resin and uniformly dispersed in the resin.
【請求項2】半導体素子を配線基板上に突起電極を介し
て搭載接続し、前記半導体素子と配線基板間の隙間に充
填剤を含む樹脂を充填した構造を有する半導体装置であ
って、前記樹脂中の充填剤を樹脂の比重にほぼ均しく空
間率40〜60%の中空構造を有するもので構成し樹脂
中に均一に分散せしめたことを特徴とする半導体装置。
2. A semiconductor device having a structure in which a semiconductor element is mounted and connected on a wiring board via a protruding electrode, and a gap between the semiconductor element and the wiring board is filled with a resin containing a filler. A semiconductor device characterized in that the filler therein is made of a material having a hollow structure with a porosity of about 40 to 60% substantially equal to the specific gravity of the resin and uniformly dispersed in the resin.
【請求項3】半導体素子を配線基板上に突起電極を介し
て搭載接続する工程と、前記配線基板上に搭載接続され
た半導体素子と配線基板との隙間に充填剤を配合した液
状樹脂を注入し隙間を樹脂で充填する工程と、前記樹脂
を硬化する工程とを含む半導体装置の製造方法であっ
て、前記充填剤を配合した液状樹脂を注入し隙間を樹脂
で充填する工程においては、前記充填剤として樹脂の比
重にほぼ均しい中空構造を有する充填剤を樹脂中に配合
し、均一に分散混合して液状樹脂を調製する工程を有す
ることを特徴とする半導体装置の製造方法。
3. A step of mounting and connecting a semiconductor element on a wiring board via a protruding electrode, and injecting a liquid resin containing a filler into a gap between the semiconductor element mounted and connected on the wiring board and the wiring board. Filling a gap with a resin, and a method of manufacturing a semiconductor device including a step of curing the resin, wherein in the step of injecting a liquid resin containing the filler and filling the gap with the resin, A method for manufacturing a semiconductor device, comprising a step of blending a filler having a hollow structure almost equal to the specific gravity of the resin into the resin as a filler, and uniformly dispersing and mixing to prepare a liquid resin.
【請求項4】前記液状樹脂中に配合する充填剤を、空間
率40〜60%の中空構造を有する充填剤で構成し樹脂
中に均一に分散混合せしめる工程を有することを特徴と
する請求項3記載の半導体装置の製造方法。
4. The method according to claim 1, wherein the filler compounded in the liquid resin comprises a filler having a hollow structure having a porosity of 40 to 60%, and a step of uniformly dispersing and mixing the filler in the resin is provided. 4. The method for manufacturing a semiconductor device according to item 3.
【請求項5】前記樹脂を熱硬化性樹脂もしくはこれに熱
可塑性樹脂成分を配合した樹脂で構成すると共に、前記
充填剤を無機系充填剤で構成し、樹脂に対する充填剤の
配合割合を重量比で22〜42%としたことを特徴とす
る請求項3もしくは4記載の半導体装置の製造方法。
5. The resin is composed of a thermosetting resin or a resin in which a thermoplastic resin component is blended, and the filler is composed of an inorganic filler. 5. The method for manufacturing a semiconductor device according to claim 3, wherein 22% to 42% is obtained.
【請求項6】前記熱硬化性樹脂がエポキシ樹脂、フェノ
ール樹脂及びポリイミド樹脂の少なくとも1種であり、
前記熱可塑性樹脂がシリコーン、ポリエチレンテレフタ
レート及びポリブタジエンの少なくとも1種であって、
前記充填剤がシリカ、アルミナ及び窒化ホウ素の少なく
とも1種の無機系充填剤であることを特徴とする請求項
3乃至5のいずれか一つに記載の半導体装置の製造方
法。
6. The thermosetting resin is at least one of an epoxy resin, a phenol resin and a polyimide resin,
The thermoplastic resin is at least one of silicone, polyethylene terephthalate and polybutadiene,
The method of manufacturing a semiconductor device according to claim 3, wherein the filler is at least one inorganic filler of silica, alumina, and boron nitride.
JP2000028895A 2000-02-01 2000-02-01 Semiconductor device and it manufacturing method Pending JP2001217268A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000028895A JP2001217268A (en) 2000-02-01 2000-02-01 Semiconductor device and it manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000028895A JP2001217268A (en) 2000-02-01 2000-02-01 Semiconductor device and it manufacturing method

Publications (1)

Publication Number Publication Date
JP2001217268A true JP2001217268A (en) 2001-08-10

Family

ID=18554230

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000028895A Pending JP2001217268A (en) 2000-02-01 2000-02-01 Semiconductor device and it manufacturing method

Country Status (1)

Country Link
JP (1) JP2001217268A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7122896B2 (en) 2003-08-21 2006-10-17 Seiko Epson Corporation Mounting structure of electronic component, electro-optic device, electronic equipment, and method for mounting electronic component

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7122896B2 (en) 2003-08-21 2006-10-17 Seiko Epson Corporation Mounting structure of electronic component, electro-optic device, electronic equipment, and method for mounting electronic component

Similar Documents

Publication Publication Date Title
US10682732B2 (en) Engineered polymer-based electronic materials
EP0878839B1 (en) Semiconductor unit package and semiconductor unit packaging method, and encapsulant for use in semiconductor unit packaging
US7638883B2 (en) Flip chip mounting method and bump forming method
US7820021B2 (en) Flip chip mounting method and method for connecting substrates
JP4477062B2 (en) Flip chip mounting method
WO2010084858A1 (en) Surface mounting method for component to be mounted, structure with mounted component obtained by the method, and liquid epoxy resin composition for underfill used in the method
JP4816333B2 (en) Manufacturing method of semiconductor device
JP3999840B2 (en) Resin sheet for sealing
JP2004111253A (en) Conductive composition for electrical connection of electronic device, and electron device
SE522253C2 (en) Semiconductor Capsule, Semiconductor Enclosure Procedure and Enclosure for Use in Semiconductor Enclosure
JPH11288979A (en) Manufacture of semiconductor device
JP2001217268A (en) Semiconductor device and it manufacturing method
JP2001102749A (en) Circuit board
JP2005206664A (en) Semiconductor sealing resin composition
JP2003277585A (en) Epoxy resin composition and semiconductor device
JP4940486B2 (en) Epoxy resin composition, semiconductor device and manufacturing method thereof
JP4267428B2 (en) Method for producing thermosetting resin composition for semiconductor encapsulation
KR20100007035A (en) Manufacturing method of anistropic conductive film and anistropic conductive film manufactured thereby
JP2015108155A (en) Liquid epoxy resin composition for underfill, structure with mounted component using the same and surface mounting method of mounted component
JP5958799B2 (en) Liquid epoxy resin composition for semiconductor encapsulation and semiconductor device using the same
JP5135287B2 (en) Epoxy resin composition, method for manufacturing semiconductor device, and semiconductor device
JP2001266642A (en) Heat conductive paste
JPH10150128A (en) Semiconductor device and its manufacture
TW201838101A (en) Conductive paste
JP2003012773A (en) Epoxy resin composition and semiconductor device