JP2001216857A - Interlock circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a compact interlock circuit, capable of controlling a power supply corresponding to the mechanical operation such as the opening and closing of a cover or the like of an electronic device, while preventing deterioration. SOLUTION: In this interlock circuit 1, an interlock switch SW11 is opened and closed in interlockingly with the mechanical operations, such as the opening and closing of a cover or the like of an electronic device, and the supply of a power source voltage V1 to a part 10 to be supplied of a power source voltage V2 is cut, when the interlock switch SW11 is opened. When the interlock switch SW11 is closed in this condition, the power source voltage V1 is not supplied instantaneously to the part 10 to be supplied, but the power is supplied to the part 10 to be supplied, when FET Q12 is switched on, at least after the elapse of a delay time t, which is determined on the basis of a time constant of R11×C11. Accordingly, an alligator clip of the interlock switch SW11 can be prevented effectively from being carbonized and deteriorated, and the runaway of the program of the electronic device due to noise can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interlock circuit, and more particularly, to an interlock circuit for controlling power supply in response to a mechanical operation of opening and closing a cover or the like of an electronic device such as a laser facsimile machine, a copying machine, and a printer. Related to lock circuit.

[0002]

2. Description of the Related Art Conventionally, in an electronic apparatus having a load using a high voltage or a load generating a high temperature inside a laser facsimile apparatus, a copying apparatus, a printer, or the like, a cover is provided to prevent electric shock and burns. An interlock circuit is provided for controlling power supply to the load according to mechanical operations such as opening and closing.

[0003] Conventionally, as this interlock circuit,
An interlock circuit in which an interlock switch that turns on and off in response to mechanical operations of the electronic device such as opening and closing of the cover is inserted in series between the power supply and the load, and a relay that links in response to the mechanical operation of the electronic device Turn on the power supply to the coil /
There is a relay provided with a relay which is turned off, and a contact of the relay inserted in series between a power supply and a load.

However, in such a conventional interlock circuit, when an interlock switch or a relay contact is closed, a transiently large rush current flows through a current line, and this rush current causes malfunction of a load or noise. It causes the occurrence.

Therefore, conventionally, there is provided an opening / closing means which is provided in series with a power supply line between a power supply and a load without having a capacitor in the vicinity thereof, and which opens and closes in conjunction with a mechanical operation of the device, An interlock circuit comprising a coil provided in series with the power supply line has been proposed (JP-A-6-29556).
No. 38).

That is, in this interlock circuit, a coil is provided in series with a power supply line in the vicinity of the opening / closing means to reduce an inrush current due to stray capacitance of the power supply line.

In a conventional interlock circuit for controlling stop and release of power supply to a power supply unit of the apparatus in response to a predetermined operation on the apparatus,
A first power supply circuit for supplying a power supply voltage to the power supply unit via a resistor and a first switch; and a second power supply circuit for supplying a power supply voltage to the power supply unit via a second switch.
When stopping power supply to the power supply circuit and the power supply unit, both the first opening and closing means and the second opening and closing means are opened to stop the power supply to the power supply unit. When canceling, there is proposed an interlock circuit having a control means for closing the first opening / closing means for a predetermined time and then closing the second opening / closing means. (See JP-A-8-314548).

That is, in this interlock circuit, when power is supplied to the power supply unit, the first opening / closing means is closed, and the resistance of the first power supply circuit and the capacity of the power supply unit are reduced. Power is supplied through an integrating circuit constituted by the load and the inrush current flowing from the power supply to the power-supplied portion, and a predetermined time after the first switching means is closed, By closing the opening / closing means 2, the integration circuit is invalidated, the power supply voltage is directly supplied to the power-supplied portion by the second power supply circuit, and the rush current when the power is applied is suppressed, and the The reliability of the lock circuit is improved.

[0009]

However, in such a conventional interlock circuit, in order to prevent the deterioration of the interlock switch of the interlock circuit and to simplify the interlock circuit. There was a need for improvement.

That is, in the interlock circuit described in JP-A-6-295538, a coil is provided in series with the power supply line in the vicinity of the opening / closing means to reduce the rush current due to the stray capacitance of the power supply line. Therefore, the inrush current at the moment when the interlock switch is closed cannot be stopped at the moment when the interlock switch is closed by the interlock switch. There was a problem that the crocodile of the lock switch deteriorated by carbonization.

In the interlock circuit described in Japanese Patent Application Laid-Open No. 8-314548, the capacitive load of the power-supplied portion is charged by the resistance of the first power-supply circuit, and the second load is supplied after a predetermined time. Since the power supply circuit supplies the power supply voltage to the power-supplied parts, the rush current at the moment when the interlock switch is closed can be suppressed with a resistor, but it cannot be stopped at all. Alligator carbonized and deteriorated, and two power supply circuits were required, resulting in a large circuit.

Therefore, according to the present invention, the power supply unit is connected in series to a power supply line for supplying power to the power supply unit of the apparatus, and opens and closes in conjunction with a predetermined mechanical operation of the apparatus. When the interlock switch for stopping and canceling the supply of power to the interlock switch is closed, the power supply delay circuit causes the power supply delay circuit to operate more than the interlock switch after a predetermined delay time has elapsed from the closing operation of the interlock switch. Simple and compact circuit configuration by turning on the power supply circuit that is provided on the supply side and that turns off and on in response to opening and closing operations of the interlock switch to stop and release power supply When the interlock switch is closed and chattering occurs, inrush current flows through the interlock switch, There is prevented from being carbonized degradation, and its object is to provide an interlock circuit which can prevent noise in the apparatus may run away.

According to a second aspect of the present invention, an energy-saving control means for executing an energy-saving mode process for stopping the supply of power to a power-supplied portion of the apparatus generates an energy-saving factor for shifting to the energy-saving mode and returns from the energy-saving mode. The power supply circuit of claim 1 is turned off and turned on in response to occurrence of an energy-saving return factor to perform the energy-saving mode processing, thereby preventing the alligator of the interlock switch from carbonizing and deteriorating and performing the energy-saving processing. It is another object of the present invention to provide a more compact and inexpensive interlock circuit even when performing the operation.

According to a third aspect of the present invention, there is provided a power supply line which is disposed closer to a power supply unit than an interlock switch of at least one power supply line among a plurality of power supply lines and is turned off / on to stop power supply. And a power supply circuit for canceling the stop and interlock monitor means for monitoring the power supply state of the power supply lines other than the power supply line provided with the power supply circuit and detecting the opening / closing operation of the interlock switch. When the interlock monitor detects the opening operation of the interlock switch, the power supply control means turns off the power supply circuit to stop the power supply, and the interlock monitor means closes the interlock switch. Upon detection, after a predetermined delay time elapses from the detection of the closing operation, the power supply circuit is turned on to turn on the power supply unit. By stopping the power supply stop, if there is a power supply line with almost no capacitive load even in one line, the power supply state of this power supply line is monitored and the power supply is performed in accordance with the opening operation of the interlock switch. When the interlock switch is stopped and the interlock switch is detected to be closed, the power supply is started after the delay time has elapsed, and the interlock switch is closed and chattering occurs with a simpler and smaller circuit configuration. It is an object of the present invention to provide an interlock circuit capable of preventing an inrush current from flowing through the interlock switch, thereby preventing the alligator of the interlock switch from carbonizing and deteriorating, and preventing runaway of the device due to noise. .

According to a fourth aspect of the present invention, the power supply control means of the third aspect turns off the power supply circuit when a predetermined energy saving factor occurs to stop the supply of power to the power supply unit. When an energy-saving return factor for returning to the energy-saving mode occurs when the mode is switched to the power-saving mode, the power supply circuit is turned on to release the stop of the supply of power to the power-supplied unit, and the energy-saving mode processing for returning from the energy-saving mode is performed. It is therefore an object of the present invention to prevent the alligator of the interlock switch from carbonizing and deteriorating, and to provide a more compact and inexpensive interlock circuit even when performing energy saving processing.

[0016]

According to a first aspect of the present invention, there is provided an interlock circuit, which is connected in series to a power supply line for supplying power to a power-supplied portion of a device, and interlocks with a predetermined mechanical operation of the device. In an interlock circuit provided with an interlock switch that performs opening and closing operations to stop and release the supply of power to the power supply unit, the power supply line is closer to the power supply unit than the interlock switch. A power supply circuit disposed to turn off / on the power supply in accordance with the opening / closing operation of the interlock switch to stop and release the supply of the power; and a predetermined delay time after the interlock switch is closed. The above object is achieved by providing a power supply delay circuit that turns on the power supply circuit after a lapse of time.

According to the above arrangement, the power supply line for supplying power to the power-supplied portion of the device is opened and closed in conjunction with a predetermined mechanical operation of the device to open and close the power supply to the power-supplied portion. When the interlock switch for stopping the supply and releasing the stop is closed, the power supply delay circuit causes the power supply delay circuit to be closer to the power supply unit than the interlock switch after a predetermined delay time has elapsed from the closing operation of the interlock switch. The power supply circuit, which is disposed and turns off / on in response to the opening / closing operation of the interlock switch to stop and release the supply of power, is turned on, so that the interlock switch has a simple and small circuit configuration. Is closed and chattering occurs, the inrush current flows through the interlock switch, and the crocodile of the interlock switch deteriorates. It is possible to prevent, it is possible to prevent the noise in the apparatus may run away.

In this case, for example, as set forth in claim 2, the interlock circuit further includes an energy-saving control unit that performs an energy-saving mode process for stopping supply of power to the power supply unit of the device. The energy saving control means performs the energy saving mode process by turning off and on the power supply circuit according to occurrence of an energy saving factor for shifting to the energy saving mode and occurrence of an energy saving return factor for returning from the energy saving mode. It may be something.

According to the above configuration, the energy-saving control means for executing the energy-saving mode process for stopping the supply of power to the power-supplied portion of the apparatus generates the energy-saving factor for shifting to the energy-saving mode, and returns to the energy-saving mode for returning from the energy-saving mode. According to the occurrence of the factor, the power supply circuit of claim 1 is turned off and on to perform the energy saving mode processing, so that it is possible to prevent the alligator of the interlock switch from being carbonized and deteriorated, and to perform the energy saving processing. In this case, the interlock circuit can be made smaller and cheaper.

According to a third aspect of the present invention, there is provided an interlock circuit, which is connected in series to a plurality of power supply lines for supplying power to a plurality of power-supplied portions of the device, and interlocks with a predetermined mechanical operation of the device. An interlock circuit including an interlock switch for opening and closing to stop and release the supply of power to the power supply unit corresponding to the power line, wherein at least one or more of the plurality of power lines is provided. A power supply circuit that is disposed closer to the power supply unit than the interlock switch of the power supply line and that performs an off / on operation to stop and cancel the supply of the power; and a power supply circuit. Interlock monitoring means for monitoring a power supply state of a power supply line other than the power supply line to detect an opening / closing operation of the interlock switch; When the interlock monitor detects the opening operation of the interlock switch, the interlock switch turns off the power supply circuit to stop the supply of the power, and the interlock monitor detects the closing operation of the interlock switch. A power supply control means for turning on the power supply circuit and canceling the stop of the power supply after a predetermined delay time has elapsed from the detection of the closing operation, thereby achieving the above object. I have.

According to the above construction, the power supply is stopped / stopped by turning off / on the power supply line, which is disposed closer to the power supply unit than the interlock switch of at least one of the plurality of power supply lines. Power supply circuit for canceling the power supply, and interlock monitoring means for monitoring the power supply state of power supply lines other than the power supply line provided with the power supply circuit and detecting the opening / closing operation of the interlock switch. When the interlock monitor detects the opening operation of the interlock switch, the supply control unit turns off the power supply circuit to stop the supply of power, and when the interlock monitoring unit detects the closing operation of the interlock switch, After a lapse of a predetermined delay time from the detection of the closing operation, the power supply circuit is turned on to supply power to the power supply unit. Because to release the stop of the supply of the source,
When there is a power line having almost no capacitive load even in one line, the power supply state of this power line is monitored to stop the power supply in accordance with the opening operation of the interlock switch, and the closing operation of the interlock switch is performed. Is detected, the supply of power is started after the delay time has elapsed, and with an even simpler and smaller circuit configuration, inrush current flows through the interlock switch while the interlock switch is closed and chattering is occurring, It is possible to prevent the alligator of the interlock switch from carbonizing and deteriorating, and to prevent the device from running away due to noise.

In this case, for example, when a predetermined energy-saving factor occurs, the power supply control means turns off the power supply circuit to turn off the power to the power supply unit. When the power-saving mode is changed to the energy-saving mode in which the supply is stopped and the energy-saving return factor is returned from the energy-saving mode, the power supply circuit is turned on to cancel the power supply to the power-supplied unit, and the power-supply-supplied unit is released from the energy-saving mode. An energy-saving mode process for restoring may be performed.

According to the above configuration, the power supply control means according to the third aspect of the present invention provides an energy saving mode in which when a predetermined energy saving factor occurs, the power supply circuit is turned off to stop the supply of power to the power supply unit. When an energy-saving return factor that causes a transition and returns from the energy-saving mode occurs, an energy-saving mode process is performed in which the power supply circuit is turned on to release the stop of power supply to the power supply unit and return from the energy-saving mode. The crocodile of the interlock switch can be prevented from being deteriorated by carbonization, and the interlock circuit can be made smaller and less expensive even when energy saving processing is performed.

[0024]

Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings. It should be noted that the embodiments described below are preferred embodiments of the present invention, and therefore, various technically preferable limitations are added. However, the scope of the present invention is not limited to the following description. The embodiments are not limited to these embodiments unless otherwise specified.

FIGS. 1 and 2 are diagrams showing a first embodiment of an interlock circuit according to the present invention. This embodiment corresponds to claim 1 of the present invention.

FIG. 1 is a schematic circuit diagram of an interlock circuit 1 to which the first embodiment of the interlock circuit of the present invention is applied, and FIG. 2 is a diagram for explaining the operation of the interlock circuit 1 of FIG. It is a waveform diagram.

In FIG. 1, the interlock circuit 1 is
The present invention is applied to an electronic device having a load using a high voltage or a load generating a high temperature inside a laser facsimile machine, a copying machine, a printer, or the like, and a power supply line supplied from the power supply of the electronic device to the power supply unit 10 They are connected in series.

The interlock circuit 1 includes an interlock switch SW11, resistors R11, R12, R13, R1.
4, R15, capacitor C11, diode D11, transistor Q11 and FET (Field Effect Transistor)
r) An interlock switch S having Q12 and the like is provided.
When W11 changes from open to closed, a current is caused to flow through the power supply unit 10 after a delay of a predetermined delay time t.

The interlock switch SW11 is connected in series to a power supply line of the electronic device by a harness or the like, and supplies the power supply V1 from the power supply to the power supply unit 10 as the power supply V2. Interlock switch SW1
Numeral 1 is opened and closed in conjunction with a mechanical operation such as opening and closing of a cover of the electronic device, and shuts off and supplies power V1 from a power source of the electronic device.

The power supply unit 10 generally has a large number of capacitive loads. In FIG. 1, the capacitive loads of the power supply unit 10 are collectively shown as a capacitor Cf.

An FET (power supply circuit) Q12 is connected between the interlock switch SW11 and the power supply unit 10, and its source is connected to the interlock switch SW1.
1, its drain is connected to the power supply unit 10, and its gate is connected to the collector of the transistor Q11 via the resistor R14. A resistor R13 is connected between the source and the gate of the FET Q12.

The terminal of the interlock switch SW11 on the side of the power supply unit 10 includes a resistor R12 and a diode D11 connected in series and a resistor R1 connected in parallel to these.
1 and a capacitor C1 connected in series to these
1, is connected to the base of the transistor Q11 via a resistor R15, and the emitter of the transistor Q11 is grounded.

The diode D11 and the resistor R12
When the interlock switch SW11 is opened,
This is for quickly discharging the electric charge charged in the capacitor C11. The transistor Q11 and the resistor R
11 to R14, diode D11 and capacitor C11
F is a power supply circuit after a predetermined delay time t has elapsed since the interlock switch SW11 closed.
It functions as a power supply delay circuit 11 that turns on the ETQ 12.

Next, the operation of the present embodiment will be described. The interlock circuit 1 includes an interlock switch SW1
When the switch 1 is closed from the open state, after a delay of a predetermined delay time t, the current flows through the power supply unit 10.

That is, in the interlock circuit 1, the interlock switch SW11 is opened / closed in conjunction with a mechanical operation such as opening / closing of the cover of the electronic device, and cuts off and supplies the power V1 from the power source of the electronic device. Now, when the cover or the like is opened, the interlock switch SW11 opens,
The supply of the power supply V2 from the power supply V1 to the power supply unit 10 is cut off. When the interlock switch SW11 is open, the plus (+) of the capacitor C11
As shown in FIG. 2, the voltage V1 ′ on the side and the power supply V2 supplied to the power supply unit 10 are discharged by a load such as the power supply unit 10 and the power supply unit 10 and the interlock switch. The power supply voltage is not applied to the crocodile of SW11.

In this state, when the cover or the like is closed, the interlock switch SW11 is closed, but the voltage V1 'on the positive side of the capacitor C11 becomes, as shown in FIG.
Through a resistor R11 and a capacitor C11, R11 × C
The voltage gradually increases in accordance with the time constant t of 11, and is applied to the base of the transistor Q11 through the resistor R15. This R
The resistance R increases gradually according to the time constant t of 11 × C11.
When the voltage applied to the base of the transistor Q11 through 15 reaches the base voltage at which the transistor Q11 operates, the transistor Q11 is turned on, and the switch 11
A voltage value obtained by dividing the power supply V1 applied through the resistor by the resistors R13 and R14 is applied to the gate of the FET Q12. When the voltage applied to the gate of the FET Q12 reaches the gate voltage at which the FET Q12 operates, the FET Q12 is turned on, and as shown in FIG.
Power supply V1 is interlock switch SW11 and FET
The power is supplied as power V2 to the power supply unit 10 through Q12.

That is, as shown in FIG. 2, even if the interlock switch SW11 is closed, the power supply V1 is not instantaneously supplied to the power-supplied portion 10, but at least has a delay determined by the time constant t. After the elapse of the time t, the power supply V2 is supplied to the power supply unit 10. At this time, at the moment when the interlock switch SW11 is closed, the current is only the current flowing through the resistor R11 and the capacitor C11, and is almost zero.

The delay time t determined by the time constant t
After the time elapses, an inrush current flows to the capacitive load Cf of the power supply unit 10 only after the FET Q12 is turned on.

That is, the interlock switch SW1
1 is closed, the interlock switch SW11
, Chattering occurs due to the mechanical structure, and when inrush current flows while this chattering is occurring,
The inrush current intermittently flows in synchronization with the chattering, and the alligator of the interlock switch SW11 is carbonized and deteriorated. In the worst case, the noise may cause the program of the electronic device to run away.

However, in the interlock circuit 1 of the present embodiment, even if the interlock switch SW11 is closed, the power supply V1 is not instantaneously supplied to the power supply unit 10, but is determined at least by the time constant t. After the elapse of the delay time t, the power supply V2 is supplied to the power supply unit 10 through the interlock switch SW11. Therefore, during the chattering after the interlock switch SW11 is closed, almost no current flows, the chattering disappears, and the interlock switch SW1 is surely removed.
After the FET 1 is closed, the FET Q12 is turned on to supply the power supply V2 to the power supply unit 10. As a result, it is possible to appropriately prevent the alligator of the interlock switch SW11 from carbonizing and deteriorating, and it is possible to reliably prevent the program runaway of the electronic device due to noise.

As described above, the interlock circuit 1 according to the present embodiment is connected to the power supply line for supplying the power supply V2 to the power supply unit 10 of the electronic device in series, and is provided with a predetermined mechanism for opening and closing the cover of the electronic device. When the interlock switch SW11 for opening / closing the power supply to the power supply unit 10 to stop and release the stop by interlocking with the manual operation is closed, the power supply delay circuit 11 turns on the interlock switch SW1.
After the delay time t has elapsed from the closing operation of the FET Q12, the FET Q12
Is turned on.

Therefore, with a simple and small circuit configuration, the inrush current flows through the interlock switch SW11 in a state where the interlock switch SW11 is closed and chattering occurs, and the alligator of the interlock switch SW11 is carbonized and deteriorated. Can be prevented, and runaway of the electronic device due to noise can be prevented.

FIGS. 3 to 7 are diagrams showing a second embodiment of the interlock circuit according to the present invention. This embodiment corresponds to claim 3.

FIG. 3 is a schematic circuit diagram of a laser facsimile apparatus 20 to which the interlock circuit according to the second embodiment of the present invention is applied, and FIG.
4 is a schematic circuit configuration diagram of an interlock circuit 30 applied to the laser facsimile machine 20 of FIG.

In FIG. 3, a laser facsimile apparatus 2
0 is a power supply 21, a control circuit 22, a laser diode 2
3, a plurality of electrical components 24 and 25, an interlock switch SW21, a power supply / control circuit 26, and the like.
As shown in FIG. 4, the interlock switch SW21 and the power supply / control circuit 26
Is composed.

The power supply 21 supplies +5 V as the power supply V3,
As the power supply V4, two power supplies supplying + 24V are output, and the power supply V3 of + 5V is directly supplied to the control circuit 22 by +
24, the power supply V4 is supplied directly to the electrical component 25, the power supply V3 is supplied to the laser diode 23, which is a power-supplied portion, via the interlock switch SW21, and the power supply V4 is supplied to the interlock switch SW21.
The power is supplied to an electrical component 24 which is a power-supplied portion via a power supply / control circuit 26. In the present embodiment, the power supply 21 has two output systems, but is not limited to two systems, and may have more output systems.

The interlock switch SW21 is of a double type in accordance with the number of output systems, and is connected in series to two power lines of + 5V power supply V3 and + 24V power supply V4 by a harness or the like. . The interlock switch SW21 is opened / closed in conjunction with a mechanical operation such as opening / closing of a cover of the laser facsimile machine 20, and the power supply 2
The power supply V3 and the power supply V4 from 1 are cut off and supplied.

The electrical component 24 is a stepping motor, a polygon motor, a main motor, and the like. As shown in FIG. 4, the power supply / control circuit 26 supplies a +24 V interlock (power supply V4). is there. Therefore, the cover or the like is opened and the interlock switch S is opened.
When W21 opens, the supply of the + 24V interlock is cut off, and the operation stops for safety. In the electrical component 24, a large number of capacitive loads exist in the stepping motor, the polygon motor, the main motor, and the like, and these capacitive loads are collectively shown by a capacitor Cf in FIG.

The electrical component 25 is an electrical component other than the electrical component 24 and does not require power control by the interlock circuit 27. As described above, the power of +24 V is directly supplied from the power source 21. I have.

The laser diode 23 is a laser diode for optical writing of the laser facsimile machine 20, and is supplied with the power supply V5 of +5 V via the interlock switch SW21 as described above in order to secure safety. When the interlock switch SW21 is opened, the operation stops.

+ 5V of interlock switch SW21
Is connected to a control circuit 22 via a resistor R21, and an interlock monitor is input to the control circuit 22 through the resistor R21. Therefore, the resistance R
The line connecting the resistor 21 and the resistor R21 to the control circuit 22 functions as an interlock monitor.

As shown in FIG. 4, the power supply / control circuit 26 includes a transistor Q21, a FET Q22 and a resistor R2.
2, R23 and R24, and when the interlock switch SW21 is closed from open, the power supply V4 of + 24V is delayed by a predetermined delay time t and supplied to the electrical component 24 which is the power supply unit.

The collector of the transistor Q21 is connected to the gate of the FET Q22 via the resistor R23, and the emitter is grounded. Transistor Q2
1 is supplied with a power control signal from the control circuit 22 via the resistor R24, and the transistor Q21
Turns on when a high power control signal is input to the base, and turns off when a low power control signal is input to the base.

The source of the FET (power supply circuit) Q22 is connected to the terminal of the power supply V4 of the interlock switch SW21, and the resistor R2 is connected between the source and the gate.
2 has been inserted. The FET Q22 has its drain connected to the electrical component 24, which is a power-supplied portion, and when turned on, supplies the + 24V power source V4 from the power source 21 to the electrical component 24 as the power source V6 through the interlock switch SW21.

As described above, the control circuit 22 includes the resistor R
The interlock monitor is input via 21 and
When the interlock switch SW21 is opened and the interlock monitor is in a low state, the control circuit 22 determines that the interlock switch SW21 is open and sets the power control signal to low. Further, when the interlock switch SW21 is closed and the interlock monitor is set to a high state, the control circuit 22 controls the interlock switch SW21.
21 is determined to be closed, and after waiting for a preset delay time t, the power supply control signal is set to high. The delay time t is set as a time from when the interlock switch SW21 is closed to when chattering is surely eliminated.

The control circuit 22, the transistor Q21 and the resistors R22 to R24 are connected to the interlock monitor SW which is input via the resistor R21.
When the opening operation of the interlock switch 21 is detected, the FET Q22 is turned off to stop the supply of the power supply V6 to the electric component 24. When the interlock monitor detects the closing operation of the interlock switch SW21, the detection of the closing operation is delayed. Time t
Is passed, the FET Q22 is turned on and the electrical component 2
4 functions as a power supply control unit 28 that releases the suspension of the supply of the power V6 to the power supply 4.

Next, the operation of the present embodiment will be described. The interlock circuit 27 of the present embodiment takes in the control circuit 22 a power supply line that does not require the delay of the rush current among the two power supply lines as the interlock monitor, and closes the interlock switch SW21.
The power supply line which requires the delay is turned on by a predetermined delay time t, and an inrush current flows through the interlock switch SW21 in which chattering has disappeared.

That is, when the cover or the like of the laser facsimile apparatus 20 is opened and the interlock switch SW21 is opened, the power supply V5 and the power supply V6 are connected to the laser diode 23 which is a power-supplied portion as shown in FIG.
In addition, the power supply voltage is not applied to the laser diode 23, the electric component 24, and the alligator of the interlock switch SW21.

In this state, the laser facsimile machine 20
Is closed and the interlock switch SW21 is closed.
Is closed, +5 V of the power supply V3 is supplied from the power supply 21 to the laser diode 23 as the power supply V5 (+5 V interlock) through the interlock switch SW21, and the voltage supplied to the laser diode 23 rises. The interlock monitor whose voltage is input to the control circuit 22 via the resistor R21 also rises as shown in FIG. The control circuit 22 determines from the interlock monitor that the interlock switch SW21 has been closed. At this time, since the laser diode 23 serving as the power-supplied portion has almost no capacitive load, at the moment when the interlock switch SW21 is closed, the laser diode 23 has the V3 system current as shown in FIG. Inrush current hardly flows.

Then, even if the control circuit 22 monitors the interlock monitor and determines that the interlock switch SW21 has been closed, as shown in FIG. Lock switch SW2
After a delay time t from when 1 is closed until chattering is surely eliminated, the power supply control signal output to the base of the transistor Q21 via the resistor R24 is set high. When the power supply control signal becomes high, the transistor Q21 turns on, and the + 24V power supply V4 input via the interlock switch SW21 is connected to the resistor R22.
When the voltage input to the gate of the FET Q22 rises and reaches the operating voltage of the FET Q22, the FET Q22 is turned on, and the power supply V4, which is + 24V of the power supply 21, is switched between the interlock switches SW21 and SW21.
The power is supplied to the electrical component 24 that is the power supply unit through the ETQ 22. That is, the interlock switch SW21
After the delay time t has passed since the closing of the
The power supply V6 is supplied to the electrical component 24, which is a power supply unit having a large number of f.

That is, the control circuit 22 monitors the interlock monitor as shown in FIG. 6 (step S10).
1) When the interlock monitor goes high, it waits for time t (delay time t) (step S102), and turns on (high) the power supply control signal (step S103).

Then, as shown as a V4 system current in FIG. 5, when the FET Q22 is turned on, an inrush current flows to the capacitive load Cf. At this time, the interlock switch SW21 operates as described above for chattering. Is completely disappeared and completely closed, so that the alligator of the interlock switch SW21 does not deteriorate due to carbonization, and no noise is generated.
Runaway of the program can be prevented.

Thereafter, when the cover or the like of the laser facsimile machine 20 is opened and the interlock switch SW21 is opened, the power supply V3 is cut off by the interlock switch SW21, so that the power supply V5 is gradually lowered, and accordingly. As shown in FIG. 5, the interlock monitor also lowers, and the control circuit 22 determines that the interlock switch SW21 has been opened by the lowering of the interlock monitor, and outputs a power supply signal as shown in FIG. Set low (off).

That is, as shown in FIG. 7, the control circuit 22 monitors the interlock monitor (step S20).
1) As soon as the interlock monitor goes low,
Turn off (low) the power control signal (step S20)
2).

When the power supply signal goes low, the transistor Q21 and the FET Q22 are turned off, and as shown in FIG. 5, the supply of the power V6 to the electrical component 24, which is the power-supplied portion, is cut off. Power supply V to the electrical component 24 which is the power supply unit
6 is interrupted, the electrical component 2 which is the power supply unit
4, the charge of the capacitive load Cf is gradually discharged, and with the discharge of the capacitive load Cf, the power supply V6 gradually falls as shown in FIG.

When the interlock switch SW21 is opened, the power supply V4 from the power supply 21 is cut off.
Is turned off, and the power supply V to the
However, in the present embodiment, when the control circuit 22 determines that the interlock switch SW21 has been opened, the control circuit 22 sets the power supply signal to low. this is,
As described above, when the interlock switch SW21 is closed, the power control signal is set to low when the interlock switch SW21 is closed, so that the power control signal is set to be high by delaying the delay time t. .

As described above, the interlock circuit 27 of the present embodiment is disposed closer to the electrical component 24 as the power supply unit than the interlock switch SW21 of one of the two power supply lines. FET Q22 which performs off / on operation to stop the supply of power and release the stop
And monitor the power supply state of power supply lines other than the power supply line provided with the FET Q22, and
And a resistor R21 for detecting an opening / closing operation of W21.
When the interlock monitor detects the opening operation of the interlock switch SW21, the power supply control unit 28
Turn off the ETQ22 to stop the power supply,
Interlock monitor is interlock switch SW2
When the closing operation is detected, the FET Q22 is turned on after the delay time t elapses from the detection of the closing operation to cancel the stop of the supply of power to the electrical component 24 which is the power supply unit.

Therefore, when there is a power supply line having almost no capacitive load even in one line, the power supply state of this power supply line is monitored and the interlock switch SW is monitored.
When the power supply is stopped in accordance with the opening operation of the interlock switch 21 and the closing operation of the interlock switch SW21 is detected, the supply of the power is started after the elapse of the delay time t. In a state where the lock switch SW21 is closed and chattering occurs, an inrush current flows through the interlock switch SW21, thereby preventing the alligator of the interlock switch SW21 from being carbonized and deteriorated. Can be prevented from running away.

FIGS. 8 to 10 show a third embodiment of the interlock circuit according to the present invention. This embodiment corresponds to claim 2 of the present invention.

This embodiment is applied to the same interlock circuit as that of the first embodiment. In the description of this embodiment, the interlock circuit of the first embodiment will be described. The same components as those in 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

FIG. 8 is a schematic circuit diagram of a power supply control circuit 30 to which the interlock circuit according to the third embodiment of the present invention is applied.

In FIG. 8, a power supply control circuit 30 has an energy-saving power supply control circuit 31 connected to the interlock circuit 1 of the first embodiment. The interlock circuit 1 includes an interlock switch SW11 and a resistor. R1
1, R12, R13, R14, R15, capacitor C1
1, diode D11, transistor Q11 and FET
Q12 and the like.

The energy-saving power supply control circuit (energy-saving control means) 31 includes an energy-saving control unit 32, resistors R31 and R32, and a transistor Q31.
When an electronic device to which the present invention is applied, for example, a laser facsimile machine, a copying machine, a printer, or the like, does not perform any operation or operation for a preset time, an energy saving transition factor (energy saving factor) occurs. Power supply V to supply unit 10
The supply of the power supply V2 to the power supply unit 10 is started by interrupting the supply of the power supply V2 to the electronic device and shifting the electronic device to the energy saving mode. Return the device from the energy saving mode.

The energy saving control section 32 outputs an energy saving power control signal to the base of the transistor Q31 via the resistor R32, and the emitter of the transistor Q31 is grounded. The collector of the transistor Q31 is connected to the plus side of the capacitor C11 of the interlock circuit 1 via the resistor R31.

When the interlock switch SW11 is closed and the electronic device to which the power supply control circuit 30 is applied with an energy-saving transition factor while the interlock switch SW11 is closed, a high energy-saving power supply control signal is transmitted through the resistor R32 to the transistor Q31. To turn on the transistor Q31, discharge the charge stored in the capacitor C11 of the interlock circuit 1, and turn off the transistor Q11 and the FET Q12 as described later. When the transistor Q11 and the FET Q12 are turned off, the supply of power to the power supply unit 10 is cut off, and the mode is shifted to the energy saving mode. In addition, in the energy saving mode, if there is an energy saving return factor, the energy saving control unit 32 outputs a low energy saving power control signal to the base of the transistor Q31 through the resistor R32, turns off the transistor Q31, and turns off the capacitor of the interlock circuit 1. C11 is charged through the resistor R11 to turn on the transistor Q11 and the FET Q12 as described later. When the transistor Q11 and the FET Q12 are turned on, the supply of power to the power-supplied unit 10 is started to return from the energy saving mode.

Next, the operation of the present embodiment will be described. The interlock circuit 1 of the present embodiment is connected to an energy-saving power supply control circuit 31 to constitute a power supply control circuit 30. The energy-saving power supply control circuit 31 controls on / off of the transistors Q11 and Q12. The feature is that the transition to the energy saving mode and the return from the energy saving mode are performed.

That is, the power supply control circuit 30
Similarly to the embodiment, the interlock switch SW1
When the electronic device 1 is opened / closed in conjunction with a mechanical operation such as opening / closing of a cover of the electronic device, the power supply V1 from the power supply of the electronic device is cut off and supplied, but the interlock switch SW11 is changed from the open state to the closed state. Then, as shown in FIG. 9, the voltage V1 ′ on the positive side of the capacitor C11 passes through the resistor R11 and the capacitor C11, and the time constant t of R11 × C11 is reached.
, And is applied to the base of the transistor Q11 through the resistor R15. When the voltage applied to the base of the transistor Q11 through the resistor R15 and gradually increases according to the time constant t of R11 × C11 reaches the base voltage at which the transistor Q11 operates, the transistor Q11 is turned on, and the transistor Q11 is turned on. A voltage value obtained by dividing the applied voltage of the power supply V1 by the resistors R13 and R14 is applied to the gate of the FET Q12. When the voltage applied to the gate of the FET Q12 reaches the operating gate voltage of the FET Q12,
The FET Q12 is turned on, and as shown in FIG.
Is supplied as power V2 to the power supply unit 10 through the interlock switch SW11 and the FET Q12.

That is, as shown in FIG. 9, even if the interlock switch SW11 is closed, the power supply V1 is not instantaneously supplied to the power-supplied supply unit 10 and at least a delay determined by the time constant t. After the elapse of the time t, the power supply V2 is supplied to the power supply unit 10. At this time, at the moment when the interlock switch SW11 is closed, the current is only the current flowing through the resistor R11 and the capacitor C11, and is almost zero.

Then, the interlock switch SW11
Even if is closed, the power supply V1 is instantaneously
0, and at least after a delay time t determined by the time constant t has elapsed, the interlock switch SW1
The power supply V2 is supplied to the power supply unit 10 through the power supply unit 1.
Therefore, during the chattering after the interlock switch SW11 is closed, almost no current flows, the chattering disappears, the interlock switch SW11 is securely closed, and then the FET Q12 is turned on to turn on the power supply unit 10. To the power supply V2. As a result, it is possible to appropriately prevent the alligator of the interlock switch SW11 from carbonizing and deteriorating, and it is possible to reliably prevent the program runaway of the electronic device due to noise.

When the interlock switch SW11 is closed, as shown in FIG.
Since the capacitor C11 is charged to the voltage V1 through the resistor R11, the transistor Q11 and the FET Q12 are in the ON state,
The power supply unit 10 is supplied with a power supply V2.

As described above, the interlock switch SW1
In a state where the power supply control circuit 1 is closed, as shown in FIG. 10, when an energy saving transition factor occurs in the electronic device to which the power supply control circuit 30 is applied (step S301), the energy saving power supply control circuit 3
The first energy saving control unit 32 outputs a high energy saving power control signal to the base of the transistor Q31 through the resistor R32 to turn on the transistor Q31 (step S3).
02).

When the transistor Q31 is turned on, discharging of the electric charge stored in the capacitor C11 of the interlock circuit 1 is started. As the electric charge of the capacitor C11 is discharged, the voltage V1 'on the positive side of the capacitor C11 is discharged.
As shown in FIG. 9, the voltage of the power supply V1 is converged to a voltage value obtained by dividing the voltage by the resistors R11 and R31, and the voltage V1 ′ applied to the base of the transistor Q11 through the resistor R15 is When the voltage drops to the off-state voltage, the transistor Q11 is turned off, and the transistor Q11 is turned off, so that the FET Q12 is turned off. As shown in FIG. 9, the power is supplied to the power supply unit 10 through the interlock switch SW11 and the FET Q12. The power supply V2 is cut off, and the mode shifts to the energy saving mode.

In this energy saving mode, if there is an energy saving return factor as shown in FIG. 10 (step S303), the energy saving control unit 32 outputs a low energy saving power control signal to the resistor R.
32 to the base of transistor Q31,
The transistor Q31 is turned off (step S30).
4).

When the transistor Q31 is turned off, the capacitor C11 of the interlock circuit 1 is charged through the resistor R11, and the voltage V on the plus side of the capacitor C11 is charged.
1 ′ is charged to the voltage of the power supply V1, the capacitor C11 is charged, and when the voltage V1 ′ rises to the ON operation voltage of the transistor Q11, the transistor Q11 and the FET Q
12 turns on. Transistor Q11 and FET Q12
Is turned on, the supply of power to the power-supplied portion 10 is restarted, and the device returns from the energy-saving mode.

When returning from the energy-saving mode, as shown in FIG. 9, after the energy-saving power control signal changes from high to low, the power supply V2 is supplied to the power supply unit 10 until the power supply V2 is supplied to the power supply unit 10. There is no delay time t as when the lock switch SW11 changes from open to closed. This is because the interlock switch SW11 of the interlock circuit 1 does not open and close during the transition to the energy saving mode and the return from the energy saving mode. This is because the alligator of the interlock switch SW11 is not deteriorated by carbonization.

As described above, the interlock circuit 1 of the present embodiment is a power supply in which the energy-saving power supply control circuit 31 for performing the energy-saving mode processing for stopping the supply of power to the power supply unit 10 of the electronic device is incorporated. The control circuit 30 is configured. The energy-saving power supply control circuit 31 turns off the FET Q12, which is a power supply circuit, in response to occurrence of an energy-saving factor for shifting to the energy-saving mode and occurrence of an energy-saving return factor for returning from the energy-saving mode. Energy saving mode processing is performed by operating and turning on.

Therefore, the interlock switch SW
In addition to preventing carbonization deterioration of the crocodile 11, the interlock circuit 1 can be made smaller and less expensive even when energy saving processing is performed.

FIGS. 11 to 13 are diagrams showing a fourth embodiment of the interlock circuit of the present invention. This embodiment corresponds to claim 4.

This embodiment is applied to the same laser facsimile apparatus and interlock circuit as the second embodiment, and in the description of the present embodiment, the second embodiment will be described. The same components as those of the laser facsimile apparatus 20 and the interlock circuit 27 are denoted by the same reference numerals, and detailed description thereof will be omitted.

FIG. 11 is a schematic circuit diagram of an interlock circuit 40 to which the interlock circuit according to the fourth embodiment of the present invention is applied.

In FIG. 11, the interlock circuit 40
Are the same as the interlock switch SW21, the resistor R21, and the like of the interlock circuit 27 of the second embodiment.
R22, R23, R24 and a transistor Q21, and a control circuit 41.
Similarly to the interlock circuit 27 of the embodiment, the control of the +5 V power supply V5 to the laser diode 23 as the power supply unit of the laser facsimile machine 20 and the +24 V power supply to the electric component 24 as the power supply unit V6 is controlled.

The control circuit 41 controls high (on) / low (off) of the power control signal and the energy-saving power control signal based on the interlock monitor in the same manner as in the second embodiment, to thereby control the transistor Q21. Is turned on / off, the FET Q22 is turned on / off to shut off the power supply V6 to the electric component (power supply unit) 24 and start supplying the power supply V6 with the delay time t. High (ON) of the power control signal and the power control signal based on the energy saving factor and the energy saving return factor of the facsimile machine 20
/ Low (off) to turn on / off the transistor Q21, thereby turning on / off the FET Q22 to cut off and supply power to the electrical component (power-supplied unit) 24 to save the energy. I do.

That is, the interlock circuit 40 of the present embodiment is different from the interlock circuit 27 of the second embodiment only in the function of the control circuit 41.

The control circuit 41, the resistors R22 to R24, and the transistor Q21 are connected to the interlock monitor SW input through the resistor R21.
When the opening operation of the switch 21 is detected, the FET Q22 is turned off to stop the supply of power. When the interlock monitor detects the closing operation of the interlock switch SW21, the delay time t has elapsed since the detection of the closing operation. , F
The ETQ 22 functions as a power supply control unit 42 that turns on the ETQ 22 to release the suspension of power supply.

Next, the operation of the present embodiment will be described. The interlock circuit 40 according to the present embodiment opens and closes the interlock switch SW21 in conjunction with opening and closing of the cover of the laser facsimile apparatus 20, and the laser diode 2
3, the power supply to the electrical component 24 based on the interlock monitor and the start of the power supply with the delay time t are started, and the energy saving factor and the energy saving return factor of the laser facsimile machine 20 are reduced. The feature is that the high / low of the power control signal and the energy-saving power control signal is controlled based on the power control signal and the power is cut off and supplied to the electrical component 24 to perform the energy-saving control.

That is, the control circuit 41 of the interlock circuit 40 sets the interlock switch SW11 to the laser facsimile apparatus 20 similarly to the second embodiment.
When the interlock switch SW21 is opened and closed in response to a mechanical operation such as opening and closing of the cover, the power supply voltages V3 and V4 from the power supply 21 are cut off and supplied. The power supply V5 is immediately supplied to the laser diode 23, but the electric component 24 is supplied to the transistor Q after the delay time t has elapsed, as shown in FIG.
The power supply control signal and the energy-saving power supply control signal input to the base of the power supply 21 are turned high, the transistor Q21 is turned on, the transistors Q21 and Q22 are turned on, and as shown in FIG. And an electric component 24 which is a power supply unit through the FET Q22.

That is, the power supply V5 is supplied to the laser diode 23 as soon as the interlock switch SW21 is closed. However, as shown in FIG. The power supply V6 is not supplied instantaneously, but is supplied after the delay time t has elapsed. At this time, at the moment when the interlock switch SW21 is closed, the current is +
The power supply V3 of 5 V is used as the power supply V5 as the laser diode 23.
Only the current flowing through it, which is almost nil.

Then, the interlock switch SW21
Is closed, the power supply V4 is not instantaneously supplied to the electrical component 24 as the power supply V6, and after the delay time t elapses,
The power supply V6 is supplied to the electrical component 24 through the interlock switch SW21 and the FET Q22. Therefore, during the chattering after the interlock switch SW21 is closed, almost no current flows, the chattering disappears, and the interlock switch SW2 is surely removed.
After the FET 1 is closed, the FET Q22 is turned on to supply the power supply V6 to the electrical component 24. As a result, it is possible to appropriately prevent the alligator of the interlock switch SW21 from carbonizing and deteriorating, and it is possible to reliably prevent the program of the laser facsimile apparatus 20 from running out of control due to noise.

As described above, the interlock switch SW2
1 is closed, the power control signal and the energy-saving power control signal are high (on), and when an energy-saving shift factor occurs in the laser facsimile machine 20 as shown in FIG. 13 (step S401), the process is shown in FIG. As described above, the control circuit 41
Outputs an off (low) power control signal and an energy-saving power control signal to the base of the transistor Q21 through the resistor R24 to turn off the transistor Q21 (step S
402).

When the transistor Q21 turns off, the FET
Q22 is turned off, and as shown in FIG. 12, the power V6 supplied to the electric component 24, which is the power supply unit, through the interlock switch SW21 and the FET Q22 becomes F
It is shut off by the ETQ 22 and shifts to the energy saving mode.

In this energy saving mode, when there is an energy saving return factor as shown in FIG. 13 (step S403), the control circuit 41 turns on (high) power control signal & energy saving power control as shown in FIG. A signal is output to the base of the transistor Q21 through the resistor R24 to turn on the transistor Q21 (step S404).

When the transistor Q21 turns on, FIG.
As shown in (2), the +24 V power supply V4 input via the interlock switch SW21 is divided by the resistors R22 and R23, and the voltage input to the gate of the FET Q22 rises to reach the operating voltage of the FET Q22. Then, the FET Q22 is turned on, and the power supply V4, which is + 24V of the power supply 21, is turned on by the interlock switch SW21 and the FET.
The power is supplied to the electrical component 24 which is the power supply unit through Q22. That is, when the energy-saving hook factor occurs, the control circuit 41 immediately outputs the ON power control signal and the energy-saving power control signal to the transistor Q21 to supply the power V6 to the electrical component 24 which is the power-supplied portion, Return from energy saving mode.

When returning from the energy-saving mode, as shown in FIG. 12, when an energy-saving return factor occurs, the control circuit 41 immediately turns on (high) the power control signal and the energy-saving power control signal by using a transistor. Output to Q21, no delay time t is provided. This is because the interlock switch SW21 does not open and close during the transition to the energy saving mode and the return from the energy saving mode, so that the interlock switch SW21 does not cause chattering, and the interlock switch SW21 is turned off when returning from the energy saving mode. This is because the crocodile does not deteriorate due to carbonization.

As described above, in the interlock circuit 40 of the present embodiment, when a predetermined energy-saving factor occurs, the power supply control means 42 turns off the FET Q22 to turn off the electric component 24 which is a power supply target. When an energy-saving return factor for shifting to the energy-saving mode in which power supply is stopped and returning from the energy-saving mode occurs, the FET Q22 is turned on to cancel the power supply to the electrical component 24 and to return from the energy-saving mode. Mode processing is being performed.

Therefore, the interlock switch SW
The crocodile 21 can be prevented from carbonizing and deteriorating, and the interlock circuit 40 can be made smaller and less expensive even when energy saving processing is performed.

The invention made by the present inventor has been specifically described based on the preferred embodiments. However, the present invention is not limited to the above, and various modifications can be made without departing from the gist of the invention. It goes without saying that it is possible.

For example, in each of the above embodiments,

[0108]

According to the interlock circuit according to the first aspect of the present invention, the interlock circuit is connected in series to a power supply line for supplying power to a power supply unit of the apparatus, and opens and closes in conjunction with a predetermined mechanical operation of the apparatus. Then, when the interlock switch for stopping and canceling the supply of power to the power-supplied unit is closed, the power supply delay circuit sets the interlock switch after a predetermined delay time elapses from the closing operation of the interlock switch. Since the power supply circuit, which is disposed closer to the power supply unit than the lock switch and is turned on / off in response to the opening / closing operation of the interlock switch to stop and cancel the supply of power, is turned on, it is simple. In a small circuit configuration, the inrush current flows through the interlock switch while the interlock switch is closed and chattering is occurring. With Tsu alligator Ji can be prevented from being carbonized degradation, it is possible to prevent the noise in the apparatus may run away.

According to the interlock circuit according to the second aspect of the present invention, the energy saving control means for performing the energy saving mode processing for stopping the power supply to the power supply unit of the apparatus causes the generation of the energy saving factor for shifting to the energy saving mode. In addition, the power supply circuit of claim 1 is turned off and on to perform the energy saving mode processing in response to the occurrence of the energy saving return factor for returning from the energy saving mode, thereby preventing the crocodile of the interlock switch from carbonizing and deteriorating. In addition to this, the interlock circuit can be made smaller and less expensive even when energy saving processing is performed.

According to the interlock circuit of the third aspect of the present invention, the power supply line of at least one of the plurality of power supply lines is disposed closer to the power supply unit than the interlock switch of at least one of the power supply lines. And a power supply circuit for stopping and canceling the supply of power, and an interlock monitor means for monitoring a power supply state of a power supply line other than a power supply line provided with the power supply circuit and detecting an opening / closing operation of an interlock switch. When the interlock monitor detects the opening operation of the interlock switch, the power supply control means turns off the power supply circuit to stop the power supply, and the interlock monitor means Upon detecting the closing operation of the lock switch, after a predetermined delay time has elapsed from the detection of the closing operation, the power supply circuit is disconnected. When the power supply to the power-supplied unit is stopped, the power supply status of this power supply line is monitored by monitoring the power supply state of this power supply line when there is a power supply line with almost no capacitive load. While stopping the power supply according to the opening operation,
When the closing operation of the interlock switch is detected, the power supply is started after the delay time has elapsed, and an inrush current is generated in a state where the interlock switch is closed and chattering occurs with a simpler and smaller circuit configuration. It is possible to prevent the alligator of the interlock switch from carbonizing and deteriorating by flowing through the lock switch, and to prevent the device from running away due to noise.

According to the interlock circuit according to the fourth aspect of the present invention, the power supply control means according to the third aspect turns off the power supply circuit when a predetermined energy-saving factor occurs to supply power to the power supply unit. When the energy-saving return factor that returns from the energy-saving mode occurs when the power-supply circuit is turned on, the power-supply circuit is turned on to cancel the power-supply interruption to the power-supplied unit, and then returns from the energy-saving mode. Since the energy saving mode processing is performed, it is possible to prevent the alligator of the interlock switch from carbonizing and deteriorating, and it is possible to further reduce the size and cost of the interlock circuit when performing the energy saving processing.

[Brief description of the drawings]

FIG. 1 is a schematic circuit configuration diagram of an interlock circuit to which a first embodiment of an interlock circuit according to the present invention is applied.

FIG. 2 is a waveform chart for explaining the operation of the interlock circuit of FIG. 1;

FIG. 3 is a schematic circuit diagram of a laser facsimile apparatus to which an interlock circuit according to a second embodiment of the present invention is applied.

4 is a schematic circuit configuration diagram of an interlock circuit applied to the laser facsimile apparatus of FIG.

FIG. 5 is a waveform chart for explaining the operation of the interlock circuit of FIG. 4;

FIG. 6 is a diagram illustrating an operation flowchart when the interlock switch of the interlock circuit is closed by the control circuit of FIG. 4;

7 is a diagram showing an operation flowchart when the interlock switch of the interlock circuit is opened by the control circuit of FIG. 4;

FIG. 8 is a schematic circuit configuration diagram of a power supply control circuit to which an interlock circuit according to a third embodiment of the present invention is applied.

FIG. 9 is a waveform chart for explaining the operation of the interlock circuit of FIG. 8;

FIG. 10 is a flowchart showing energy saving control processing by the energy saving control unit of FIG. 8;

FIG. 11 is a schematic circuit configuration diagram of an interlock circuit to which an interlock circuit according to a fourth embodiment of the present invention is applied.

FIG. 12 is a waveform chart for explaining the operation of the interlock circuit of FIG. 11;

FIG. 13 is a flowchart showing energy saving control processing by the control circuit of FIG. 11;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Interlock circuit 10 Power supply part 11 Power supply delay circuit SW11 Interlock switch R11, R12, R13, R14, R15 Resistance C11, Cf Capacitor D11 Diode Q11 Transistor Q12 FET 20 Laser facsimile machine 21 Power supply 22 Control circuit 23 Laser diode 24, 25 Electrical components 26 Power supply / control circuit 27 Interlock circuit 28 Power supply control means SW21 Interlock switch Q21 Transistor Q22 FET R21, R22, R23, R24 Resistance 30 Power supply control circuit 31 Energy saving power supply control circuit 32 Energy saving control unit R31, R32 resistor Q31 transistor 40 interlock circuit 41 control circuit 42 power supply control means

Claims (4)

[Claims] 1. A power supply line for supplying power to a power-supplied portion of an apparatus is connected in series, and is opened and closed in conjunction with a predetermined mechanical operation of the device to stop supplying power to the power-supplied section. And an interlock circuit provided with an interlock switch for canceling stoppage, wherein the interlock switch is disposed on the power supply line closer to the power supply unit than the interlock switch, and is turned on / off in response to the opening / closing operation of the interlock switch. A power supply circuit that operates to stop and cancel the supply of the power, and a power supply delay circuit that turns on the power supply circuit after a predetermined delay time has elapsed since the interlock switch closed. And an interlock circuit comprising: 2. The interlock circuit further includes an energy saving control means for performing an energy saving mode process for stopping supply of power to the power supply unit of the apparatus, wherein the energy saving control means switches the energy saving mode to the energy saving mode. 2. The interlock according to claim 1, wherein the power supply circuit is turned off and turned on to perform the energy saving mode processing in accordance with the occurrence of a shifting energy saving factor and the occurrence of an energy saving returning factor returning from the energy saving mode. circuit. 3. A power supply line connected to a plurality of power supply lines for supplying power to a plurality of power-supplied portions of the device, and opened and closed in response to a predetermined mechanical operation of the device to correspond to the power supply line. In an interlock circuit including an interlock switch for stopping and canceling the supply of power to the power supply unit, the interlock circuit may include at least one or more power lines among the plurality of power lines. A power supply circuit disposed on the side of the power-supplied portion to perform an off / on operation to stop and release the supply of the power, and a power state of a power line other than the power line provided with the power supply circuit Interlock monitor means for monitoring the opening and closing operation of the interlock switch, and the interlock monitor means Upon detecting the opening operation of the click switch,
When the power supply circuit is turned off to stop the power supply, and the interlock monitor detects the closing operation of the interlock switch, after a predetermined delay time has elapsed from the detection of the closing operation, Power supply control means for turning on the power supply circuit and canceling the suspension of the power supply. 4. The power supply control means, when a predetermined energy saving factor occurs, shifts to an energy saving mode in which the power supply circuit is turned off to stop the supply of power to the power supply unit. When an energy-saving return factor for returning from the mode occurs, an energy-saving mode process of turning on the power supply circuit to cancel the stop of power supply to the power-supplied unit and returning from the energy-saving mode is performed. The interlock circuit according to claim 3.