JP2001216202A - Address line fault detector for memory, method therefor and recording medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technique for detecting a fault generated on a line for the address input of a memory. SOLUTION: A CPU 102 inputs an address through an address line 103 to the memory 101. A fault generated on the address line 103, prescribed data different from the others are written to a predetermined address, the data of the address specified by changing a logic value by the unit of the address line 103 are read from the address and the read are compared with the prescribed data. By the comparison, it is judged that the fault is generated in the address line 103 for which the prescribed data are read even when the logic value is changed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a RAM and a FROM.
The present invention relates to a technique for detecting a fault occurring on a line connected to each of a plurality of address input terminals provided in a writable memory.

[0002]

2. Description of the Related Art In a system having a writable memory such as a RAM, it is usual to check whether or not the memory operates normally when a power is turned on. By performing the check, it is possible to promptly respond to the occurrence of an abnormality in the memory and to prevent a malfunction of the system caused by the abnormality of the memory.

[0003]

A conventional memory check is performed by writing a predetermined value for each address, reading the value, and confirming whether the value matches the written value. ing. The confirmation is usually performed a plurality of times by changing the value to be written. However, in the check performed in such a manner, even if it is possible to confirm whether the memory operates normally or not, as described below, the lines connected to the plurality of terminals provided for the address input to the memory are as follows. The above fault cannot be detected.

[0004] For example, if a fault occurs in which a certain line is short-circuited and its logical value is always 0, the same address is specified regardless of the logical value of that line. However, even if an unintended address is specified due to a failure, access to that address can be performed. Therefore, even if the written value matches the read value, it does not mean that the intended address has been accessed, in other words, that no fault has occurred on the line.

[0005] Obstacles on the line are also caused by adhesion of dust to the substrate on which the memory is mounted. This causes a malfunction of the system as well as an abnormality of the memory itself, so that the influence is enormous. From this, it is considered that the effect obtained by detecting the fault on the line is great.

SUMMARY OF THE INVENTION An object of the present invention is to provide a technique for detecting a fault that has occurred on a memory address input line.

[0007]

SUMMARY OF THE INVENTION An address line fault detecting device for a memory according to the present invention is applied to a memory having a plurality of terminals for inputting an address, and is generated on a line connected to each of the plurality of terminals. Assuming that a failure is detected, first writing means for writing a predetermined value to at least one address on the memory, and at least an address at which the first writing means writes the predetermined value and a logical value of a predetermined number of lines A second writing means for writing a value different from the predetermined value to an address on the memory designated by differently writing, and reading the value from the address where the second writing means has written a value different from the predetermined value. Means, and a fault detecting means for comparing a value read by the reading means with a predetermined value, and detecting a fault occurring on the line based on the comparison result.

In the above configuration, the first writing means writes a predetermined value to an address designated by setting all logical values of the line to 1, and the second writing means writes the predetermined value to the first writing means. From the address at which the predetermined value is written, at least a value different from the predetermined value is written to each address designated by setting the logical value to 0 for only one line as the predetermined number of lines. If the value coincides with the value, the reading means sets the logical value to 0 in order to read the value.
It is desirable to determine that a failure has occurred on the line that has been set.

The first writing means writes a predetermined value to an address designated by setting all logical values of the line to 0, and the second writing means writes the predetermined value to the first writing means. From the address, at least a value different from the predetermined value is written to each address designated by setting the logical value to 1 for one line as the predetermined number of lines, and the failure detecting means determines that the value read by the reading means matches the predetermined value. Preferably, the reading means determines that a failure has occurred on a line having a logical value of 1 in order to read the value.

[0010] The second writing means may be configured to invert the logical value of the adjacent two lines as a predetermined number of lines from the address where the first writing means writes the predetermined value to a predetermined value. If at least the value read by the reading means matches the predetermined value, the failure detecting means generates a failure on a line having a different logical value for the reading means to read the value. It is desirable to determine that It is preferable that the first writing means writes a predetermined value to an address specified by setting a logical value of a line to 0 every other line and setting the remaining lines to 1s. Alternatively, it is desirable to write a predetermined value to an address where all the logical values of the line are specified as 1 or 0.

An address line fault detecting method for a memory according to the present invention is provided for detecting a fault occurring on a line connected to each of a plurality of terminals for a memory having a plurality of terminals for inputting an address. A predetermined value is written to at least one address on the memory,
At least a value different from the predetermined value is written to an address where the logical value of the predetermined number of lines differs from an address at which the predetermined value is written, a value is read from an address where a value different from the predetermined value is written, and the value is compared with the predetermined value. Based on the above, a fault occurring on the line is detected.

[0012] The recording medium of the present invention comprises a first writing means for writing a predetermined value to at least one address on a memory provided with a plurality of address input terminals to which lines are connected; A second writing unit for writing a value different from the predetermined value to an address on the memory designated by making a logical value of the predetermined line number different from an address where the predetermined value is written by the first writing unit; A reading means for reading a value from an address in which a value different from the predetermined value is written by the writing means of No. 2 and a value read by the reading means being compared with a predetermined value; A failure detecting means for detecting a failure and a program for realizing the failure are recorded.

[0013]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a diagram showing a configuration of a memory address line failure detection device (hereinafter, abbreviated as a failure detection device) according to the present embodiment.

The fault detecting device is mounted on, for example, a portable terminal device. As shown in FIG.
Alternatively, it is realized by the CPU 102 accessing the writable memory 101 such as an FROM. A program for checking the memory 101 described later is stored in, for example, a ROM mounted on the CPU 102 or a memory (not shown).

A plurality of address lines (lines) 103 are connected to address input terminals of the memory 101, respectively.
The address is input to the memory 101 via the. Here, as shown in FIG.
The description will be made on the assumption that the terminal provided with the numerical value of 16 is provided. When the terminal (or the address line 103) is specified, it is expressed using a numerical value assigned to the terminal, such as terminal 1.

The CPU 101 performs a system check including detection of whether or not a failure has occurred in the memory 101 when the power is turned on, for example. Hereinafter, the failure detection of the memory 101 performed by the CPU 102 will be described in detail with reference to various flowcharts illustrated in FIGS.

FIG. 3 is a flowchart of a memory failure detection process. The processing is realized by the CPU 102 executing a program stored in a ROM mounted on the CPU 102 or a memory (not shown).
This is a process for detecting a failure that has occurred on the first device. First, the processing will be described in detail with reference to FIG.

First, in step S1, a memory check process for confirming whether a specified address can be normally accessed is executed. In a succeeding step S2, an address line check process for detecting a failure occurring on the address line 103 is executed. After executing the processing, the series of processing ends.

The CPU 102 detects a fault that has occurred on the memory 101 by executing the above-described memory fault detecting process. Although the detailed description of the detection result is omitted, the user is notified by displaying the result on a display device (not shown) after the execution of the process. Thereby, the memory 1
In this case, the user can quickly and appropriately respond to a failure that has occurred on the device. Hereinafter, the subroutine processing executed in the memory failure detection processing will be described in detail.

FIG. 4 is a flowchart of a memory check process executed as step S1. In the subroutine process, the memory check process will first be described in detail with reference to FIG. The memory check process is basically the same as that conventionally performed for checking the operation of the memory.

First, in step S11, the memory 102
Is set as the access destination. In the following step S12, 00H (H represents a hexadecimal number), 55H, AAH, and FFH are written in the set address in that order, and every time data (value) is written, the data written immediately after that is read. Do. Thereafter, the process proceeds to step S13.

In step S13, it is determined for each data whether the written data matches the data read after the writing. If the written data and the data read after the writing all match for each data, the determination is YES and the process moves to step S15. If not, that is, if there is any written data that does not match the read data, the determination is NO, and an error (malfunction) occurs in the memory 101 in step S14. After storing the information indicating that the data has been read (the value of the address that could not be accessed normally, etc.) in the CPU 102 or in a memory not to be checked, the process proceeds to step S15.

In step S15, it is determined whether the address accessed in step S12 is the last address (address) of the memory 101. When the confirmation for all the addresses of the memory 101 has been completed, the determination is YES, and the series of processing ends. Otherwise, that is, if there is an unconfirmed address, the determination is N
In step S16, the access destination is changed to the next address (address) in step S16, and the process returns to step S12.

By executing the above memory check process, an abnormal address where normal writing or reading cannot be performed is detected (specified). By detecting (identifying) an abnormal address in this way, it is possible to promptly respond to the abnormality (for example, to access while avoiding the abnormal address) and to prevent a system malfunction due to the abnormality. be able to.

FIG. 5 is a flowchart of the address line check processing executed as step S2 in the memory failure detection processing shown in FIG. Next, the address line check processing will be described in detail with reference to FIG.

First, in step S21, address line 1
It is released as a fault that has occurred on 03 (here, for convenience, it is used to mean that the logical value is always 1)
An address line release check process for confirming whether or not the address line is open is executed. In the following step S22, as a fault that has occurred on the address line 103, an address line short-circuit check for confirming whether or not it is short-circuited (for convenience, it is used in the sense that the logical value is always 0) is performed. Execute the process. After the execution, the process proceeds to step S23, and as a fault occurring on the address line 103, a short-circuit check of the adjacent address line 103 for checking whether or not the adjacent address line 103 is electrically connected (short-circuited). Execute the process. After executing it, a series of processing ends.

By executing the above-described address line check processing, failures occurring on the address line (line) 103 include an open circuit, a short circuit, and an adjacent address line 1.
03 is detected. Hereinafter, various subroutine processes executed in the address line check process for detecting those faults will be described in detail.

FIG. 6 is a flowchart of the address line release check processing executed as step S21. In the subroutine processing executed in the address line check processing, first, the address line open check processing will be described in detail with reference to FIG.

For example, in a situation where a certain address line 103 is open and its logical value is always 1, the CPU 102 sets the open address line 10
No matter how the logical value of 3 is changed, the same address will be accessed. In other words, even if the specified addresses are different, the same address is actually accessed. In the present embodiment, by paying attention to this, it is detected whether or not the data (value) written at a certain address is read out by specifying an address different from that address, thereby detecting the opening of the address line 103. are doing.

First, in step S31, the memory 101
Is cleared, that is, its value is set to 0. In the following step S32, a value (here, 1) different from 0 is written to the final address. After writing 1 to the final address, the process proceeds to step S33, where the variable n for managing the address line 103 to be checked is set.
To 0. After that, it moves to step S34.

The final address is usually stored in each address line 10
It is specified by setting all logical values of 3 (bits) to 1. As shown in FIG. 2, if the terminals 101 to 16 are provided in the memory 101 for inputting an address, the address is designated by setting all logical values of the terminals 1 to 16 (all 16 bits) to 1. You. In step S34, among the logical values of each address line 103 when the final address is specified,
Only the logical value of the address line 103 corresponding to 2 to the nth power is set to 0
Reads the data at the address specified. Thus, for example, if the value of the variable n is 0 and the numerical value assigned to the terminal indicates the number of digits in the address, the terminal 1
Is set to 0, and the logical values of the other terminals 2 to 16 are all set to 1, and the data at the designated address is read.

In step S35 following step S34, it is determined whether the value of the data read in step S34 is "1". When the value of the read data is 1, even if the logical value of the address line 103 (bit) corresponding to 2 to the nth power is changed from 1 to 0, the logical value is set to 1 and written to the final address specified. That is, the data has been read. This means that the address line 103 whose logical value has been changed from 1 to 0 is open. From this, if the value of the read data is 1,
The determination is YES, and information indicating that the address line 103 corresponding to the power of 2 is open is stored in the CPU 102 or in a memory not to be checked in step S36, and then the process proceeds to step S37. Otherwise, the determination is no and that step S37
Move to

In step S37, it is determined whether or not the address line 103 whose logical value has been set to 0 in step S34 is the last one. As described above, in the present embodiment, the logical values are set to 0 in order from the address line 103 having the lowest address.
I have to. From this, the immediately preceding step S
When the data is read out by setting the logical value of the address line 103 connected to the terminal 16 to 0 at 34, the determination is YES and the series of processing ends. Otherwise, the determination is no, the value of the variable n is incremented in step S38, and the process returns to step S34.

As described above, based on the address (final address) at which data different from the others is written, data is read from the specified address by changing its logical value in units of the address line 103 (bit), and the data is read out. The data written is compared with the data written to the last address. Thus, it is possible to detect the address line 103 (here, the open address line 103) whose access destination does not change even when the logical value is changed.

FIG. 7 is a flowchart of the address line short-circuit check processing executed as step S22 in the address line check processing shown in FIG. Next, FIG.
, The address line short-circuit check processing will be described in detail.

The logical value of the address line 103 differs between a short circuit and an open circuit. For this reason, short-circuiting of the address line 103 is performed by writing data different from the other at an address different from the final address and confirming whether the data is read from another address.

First, in step S41, data different from the others is written to address 0, that is, the head address specified by setting all logical values of 1-bit signals input to the terminals 1 to 16 to 0. At this point, 1 should be written to the last address and 0 should be written to the other addresses, so 2 is written to the first address as data different from the other addresses. When the writing is performed, 0 is substituted for the variable n in step S42, and the process proceeds to step S43.

In step S43, 2n of the logical values of each address line 103 when the head address is specified
Only the logical value of the address line 103 corresponding to the power is set to 1 to read the data at the designated address. Thereby,
For example, if the value of the variable n is 0, only the logical value of the terminal 1 is set to 1 and the logical values of the other terminals 2 to 16 are all set to 0, and the data of the designated address is read.

In step S44 following step S43, it is determined whether or not the value of the data read in step S43 is 2. The read data value of 2 means that even if the logical value of the address line 103 (bit) corresponding to 2 to the nth power is changed from 0 to 1, the logical value is changed to 0 and written to the specified start address. That is, the data has been read. This means that the address line 103 whose logical value has been changed from 0 to 1 is short-circuited. From this, if the value of the read data is 2,
The determination is YES, and in step S45, information indicating that the address line 103 corresponding to 2 n is short-circuited is stored in the CPU 102 or in a memory not to be checked, and then the process proceeds to step S46. Otherwise, the determination is no and that step S46
Move to

In step S46, it is determined whether or not the address line 103 whose logical value is set to 1 in step S43 is the last one. As described above, in the present embodiment, the logical value is set to 1 in order from the lowest address line 103. Accordingly, when the data is read with the logical value of the address line 103 connected to the terminal 16 set to 1 in the immediately preceding step S43, the determination is YES, and the series of processing ends. Otherwise, the determination is no, and the value of the variable n is incremented in step S47, and the process returns to step S43.

As described above, in the address line short-circuit check processing, different data is written to an address different from the address line open check processing, and the address line 10
By changing the logical value from 0 to 1 in three units, a short circuit of the address line 103 is detected.

FIG. 8 is a flowchart of a short-circuit check process of an adjacent address line, which is executed as step S23 in the address line check process shown in FIG. Finally, the short-circuit check processing will be described in detail with reference to FIG. At the time of execution, 1 is written in the last address, 2 is written in the first address, and 0 is written in the other addresses.

When two or more adjacent address lines 103 are connected (when a short circuit occurs), the shorted address line 10
The logical values of 3 are all the same. Therefore, attention is paid to this fact, and a short circuit between the address lines 103 is detected. More specifically, for example, the address line 10
A predetermined value is written to an address specified by alternately changing the logical value of the logical address 3 and the logical value of the adjacent address line 103 is inverted from that address, that is, the address specified, that is, the logical value of the one address line 103 Is changed from 0 to 1 and the logical value of the other address line 103 is changed from 1 to 0 and a value is read from the specified address, and it is detected by confirming whether or not the read value matches a predetermined value. I have. For example, if an address is specified by 4 bits, for example, a predetermined value is written to address 0101, and the predetermined value is 0110, 0011,
And 1001 are compared with each other to determine whether they match the values read from addresses 1001 and 1001, respectively.
A short circuit (electric connection) between them has been detected.

First, in step S50, address line 1
Write 3 as data different from the others at an address designated as a logical value of 03 as 0 and 1 every other bit (one address line 103). In a succeeding step S51, 0 is substituted for a variable n. After that, in step S52, the process proceeds to
Each address line 1 when specifying the start address (address 0)
Among the logical values of 03, the address line 103 corresponding to 2 n power and the address line 103 corresponding to 2 (n + 1) power
The data at the specified address is read by inverting the logical value of the above with the logical value specified in step S50. Thus, for example, if the value of the variable n is 0, only the logical values of the terminals 1 and 2 are inverted, and the data of the specified address is read out while the logical values of the other terminals 3 to 16 remain unchanged. become.

In a step S53 following the step S52, it is determined whether or not the value of the data read in the step S52 is 3. When the value of the read data is 3, the logical value of each address line 103 (bit) corresponding to 2 to the n-th power, and further to 2 to the (n + 1) -th power, is changed from 0 to 1 or 1
That is, even if the data is changed from 0 to 0, the data written to the address specified by changing the logical value to 0 or 1 is read. This means that two adjacent address lines 103 whose logic values have been changed from 0 to 1 or 1 to 0 are both short-circuited. From this, if the value of the read data is 2, the determination is YES, and the address lines 103 corresponding to 2 n and further 2 (n + 1) are short-circuited in step S54. Is stored in the CPU 102 or in a memory that is not checked, and then the process proceeds to step S55. Otherwise, the determination is no and that step S
Go to 55.

In step S55, it is determined whether or not the address line 103 corresponding to 2 n raised to the inverted logical value in step S52 is immediately before the last (highest order).
If the logic value of the address line 103 connected to the terminal 15 corresponding to 2 n raised to the power of n is inverted and the data is read in the immediately preceding step S52, the determination is YE
In S, the series of processing ends. Otherwise, the determination is no, the value of the variable n is incremented in step S56, and the process returns to step S52.

As described above, the data is read by changing the logical values of the adjacent address lines 103 together, and the read data is compared with the data written in the head address, whereby the adjacent address lines 103 whose logical values have been changed are read.
Are both short-circuited.

In this embodiment, a short circuit between two adjacent address lines 103 is detected. However, both of them may be short circuited or open. Such release means that the logical values of two adjacent address lines 103 are both set to 0 and the logical values of the other address lines 103 are all set to 1
Can be detected by comparing the data read from that address with the data (here, 1) written to the final address. In the other short circuit, the logical value of the two adjacent address lines 103 is set to 1 and the logical values of the other address lines 103 are all set to 0 to specify an address, and data read from that address is written to the first address. It can be detected by comparing with data (here, 2).

Opening of two adjacent address lines 103,
Alternatively, the address at which a predetermined value (data) different from the others to detect a short circuit is not limited to the first address or the last address. The predetermined value may be written to an arbitrary address. The address from which the value is read may be determined according to the address at which the predetermined value is written.
Specifically, for example, if an address is specified by 4 bits, for example, if a predetermined value is written to address 0101, values (data) are read from addresses 0110, 0011, and 1001 and compared with the predetermined value. Good.

In this embodiment, in order to detect the opening or short circuit of one address line 103, data different from other addresses is written to the last address or the top address. Is not limited to the last address or the first address. As described above, data different from the others is written in the address where the data was written and one address line 1.
By comparing data read from an address with a different logical value of 03, it is possible to detect that the address line 103 is short-circuited or open. For this reason, different data may be written to various addresses. The number of the addresses may be three or more. However, the address to write data different from the others is
In order to be able to detect both short circuit and open circuit for each address line 103, the logical values of each address line 103 of each address are put together so that the logical values 0 and 1 are aligned in each address line 103. (If an address is designated by 4 bits, addresses 0101 and 1010, addresses 1001 and 0110 correspond to combinations of addresses to which a predetermined value is written).

The fault detecting device according to the present embodiment has the configuration shown in FIG.
As shown in FIG. 2, the CPU 102 directly accesses the memory 101. However, the CPU 102 can access the memory 10 via another device, for example, a memory controller.
1 may be accessed indirectly. In many cases, the address is specified by inputting a row address and a column address. In a memory in which an address is designated in such a manner, a fault on the address line 103 may be detected in, for example, a row address unit or a column address unit. As is apparent from this, the present invention is applicable regardless of the method of specifying an address.

A program for realizing the operation of the above-described failure detecting device may be recorded on a recording medium such as a CD-ROM, a floppy disk, or a magneto-optical disk and distributed. Alternatively, part or all of the program may be distributed using a communication line such as a public network. In such a case, the user can apply the present invention to the device by acquiring the program and loading it into an arbitrary failure detection device or data processing device. For this reason, the recording medium may be one that can be accessed by an apparatus that distributes the program.

[0053]

As described above, according to the present invention, a predetermined value is written to at least one address on a memory, and the logical value of a predetermined number of lines is different from the address at which the predetermined value is written. At least a value is written, a value is read from an address where a value different from the predetermined value is written, and the read value is compared with the predetermined value. For this reason, it is possible to detect an address line in which an actually specified address does not change even if the logical value is changed, that is, an address line in which a failure has occurred.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a memory address line fault detection device according to the present embodiment.

FIG. 2 is a diagram illustrating address lines connected to a memory.

FIG. 3 is a flowchart of a memory failure detection process.

FIG. 4 is a flowchart of a memory check process.

FIG. 5 is a flowchart of an address line check process.

FIG. 6 is a flowchart of an address line release check process.

FIG. 7 is a flowchart of an address line short-circuit check process.

FIG. 8 is a flowchart of a short-circuit check process of an adjacent address line.

[Explanation of symbols]

 101 memory 102 CPU 103 address line

Claims (8)

[Claims] 1. A device for detecting a fault occurring on a line connected to each of a plurality of terminals for a memory having a plurality of terminals for inputting an address, wherein at least one First writing means for writing a predetermined value to an address; at least an address on the memory designated by making the logical value of the predetermined number of lines different from the address at which the first writing means writes the predetermined value; Second writing means for writing a value different from the predetermined value; reading means for reading a value from an address at which the second writing means has written a value different from the predetermined value; and reading the value read by the reading means. A fault detecting means for comparing the predetermined value and detecting a fault occurring on the line based on a result of the comparison; and a fault detecting device for a memory address line. 2. The method according to claim 1, wherein the first writing unit writes the predetermined value to an address designated by setting all logical values of the line to be 1, and the second writing unit sets the first writing unit. From the address at which the predetermined value is written, 1 as the predetermined number of lines
At least a value different from the predetermined value is written to each address designated by setting the logical value to 0 only for the line, and the fault detecting means reads the read means when the value read by the reading means matches the predetermined value. 2. The memory address line fault detecting device according to claim 1, wherein it is determined that a fault has occurred on a line whose logical value is 0 in order to read the value. 3. The first writing means writes the predetermined value to an address designated by setting all logical values of the line to 0, and the second writing means comprises a first writing means. From the address at which the predetermined value is written, 1 as the predetermined number of lines
At least a value different from the predetermined value is written to each address designated by setting the logical value to 1 only for the line, and the failure detecting means reads the reading means when the value read by the reading means matches the predetermined value. 2. The memory address line fault detecting device according to claim 1, further comprising: determining that a fault has occurred on a line having a logical value of 1 to read the value. 4. The second writing means is designated by inverting a logical value of the adjacent two lines as the predetermined number of lines from an address at which the first writing means writes the predetermined value. At least a value different from the predetermined value is written in the address, and the failure detecting means changes the logical value so that the reading means reads the value when the value read by the reading means matches the predetermined value. 2. The address line fault detecting device for a memory according to claim 1, wherein it is determined that a fault has occurred on the failed line. 5. The method according to claim 1, wherein the first writing unit writes the predetermined value to an address specified by setting a logical value of the line to 0 every other line and setting the remaining lines to 1s. 5. The memory address line fault detecting device according to claim 4. 6. The memory address according to claim 4, wherein said first writing means writes the predetermined value to an address designated as a logical value of all ones or zeros of the line. Line fault detection device. 7. A method for detecting a fault occurring on a line connected to each of a plurality of terminals for a memory having a plurality of terminals for inputting an address, the method comprising: A predetermined value is written to one address, and at least a value different from the predetermined value is written to an address at which the logical value of the predetermined number of lines is different from the address at which the predetermined value is written. Reading out the address, comparing it with the predetermined value, and detecting a fault occurring on the line based on the comparison result. 8. A first writing means for writing a predetermined value to at least one address on a memory having a plurality of address input terminals to which lines are connected, and at least the first writing means. Second writing means for writing a value different from the predetermined value to an address on the memory designated by making the logical value of the predetermined number of lines different from the address where the predetermined value is written by the writing means; Reading means for reading a value from an address at which a value different from the predetermined value is written by the writing means; comparing the value read by the reading means with the predetermined value; A failure detecting means for detecting a failure that has occurred, and a recording medium that stores a program for realizing the following.