JP2001210825A - Polycrystalline thin-film transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance the current drive capability of a polycrystalline thin-film transistor in the transistor. SOLUTION: A critical path, having a high electrical conductivity between a source region and a drain region in comparison with that of other critical paths, exists in a polycrystalline semiconductor film. A defect in an MOS interface, the number of crystal grain boundaries and defects in the crystal grain boundaries in the critical path are reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a polycrystalline thin film transistor, and more particularly, to a polycrystalline thin film transistor realizing a high current driving capability.

[0002]

2. Description of the Related Art In recent years, polycrystalline thin film transistors have been used in a wide variety of devices such as display devices and sensors, and the range of use is expected to further expand in the future. The advantage of a polycrystalline thin film transistor is that not only can it be formed in each pixel as an active matrix element to perform switching, but also a drive circuit can be formed (H. Ohshima, Pro.
c. See Euro Display '96 Workshop, p17). In order to form a driving circuit, a polycrystalline transistor must have high current driving capability. In particular, recently, various crystallization processes have been developed in order to increase the current driving capability of the polycrystalline transistor, and the increase in the crystal grain size and the position control are being realized.

[0003] The inventor of the present invention is studying carrier conduction in a polycrystalline semiconductor. FIG. 1 is a first example of a simulation of carrier conduction in a polycrystalline semiconductor. (A) shows a simulation result, and (b) shows a structure used for the simulation. A voltage of 0.1 V is applied between the cathode 1 and the anode 2. At the grain boundaries 4 at the boundaries of the crystal grains 3, there are grain boundary defects, which trap carriers to reduce the number of carriers and form a potential barrier (Kimura Mutsumi, 47th Spring 2000) Applied Physics Alliance Lecture Meeting Proceedings, To be publish
ed). The curve shown is a current flow line 5 whose density corresponds to the current density. 2 to 10 are second to eighth examples of simulation of carrier conduction in a polycrystalline semiconductor. The positions of the cathode 1 and the anode 2 and the grain size of the crystal grains 3 are changed respectively.

The following can be seen from FIGS. There are places where the current density is high and places where the current density is low. The difference can be as much as 10 times.

[0005]

SUMMARY OF THE INVENTION An object of the present invention is to increase the current driving capability of a polycrystalline thin film transistor.

[0006]

According to the present invention, there is provided a polycrystalline semiconductor, a gate electrode, a gate insulating film between the polycrystalline semiconductor and the gate electrode, and a source region in which a dopant is introduced into the polycrystalline semiconductor. A polycrystalline thin film transistor, comprising: a polycrystalline thin film transistor having at least one critical path having a higher electric conductivity between the source region and the drain region than the others in the polycrystalline semiconductor. It is a crystalline thin film transistor.

According to the first aspect of the present invention, in the polycrystalline thin film transistor, the current driving capability can be enhanced.
It becomes possible.

According to a second aspect of the present invention, there is provided the polycrystalline thin film transistor according to the first aspect, wherein a MOS interface defect in a critical path is reduced.

According to the second aspect of the present invention, it is possible to further increase the current driving capability of the polycrystalline thin film transistor.

According to a third aspect of the present invention, there is provided the polycrystalline thin film transistor according to the first aspect, wherein the number of crystal grain boundaries in a critical path is reduced.

According to the third aspect of the present invention, it is possible to further increase the current driving capability of the polycrystalline thin film transistor.

According to a fourth aspect of the present invention, there is provided the polycrystalline thin film transistor according to the first aspect, wherein crystal grain boundary defects in a critical path are reduced.

According to the fourth aspect of the present invention, it is possible to further increase the current driving capability of the polycrystalline thin film transistor.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described.

(First Embodiment) FIG. 11 shows a first embodiment of the present invention.
Is a polycrystalline semiconductor according to the embodiment. FIG. 12 is a sectional view of the polycrystalline thin film transistor according to the first embodiment of the present invention. FIG. 11 is a view of the polycrystalline semiconductor 7 of FIG. 12 as viewed from above. In FIG. 11, there is at least one current path having a higher electric conductivity than the others. This is called critical path 6. Current flowing through the critical path 6 is dominant in carrier conduction in the polycrystalline semiconductor. The existence of the critical path 6 makes it possible to increase the current driving capability of the polycrystalline thin film transistor. Critical path 6
By reducing the MOS interface defects in the inside, it is possible to increase the free carriers (carriers that are not trapped by the defects and contribute to electric conduction) existing in the critical path 6 and further increase the current driving capability. .

(Second Embodiment) FIG. 13 shows a second embodiment of the present invention.
Is a polycrystalline semiconductor according to the embodiment. Compared with the first embodiment, the number of grain boundaries 4 in the critical path 6 is reduced. This makes it possible to further increase the current driving capability. In addition, by reducing the defects present at the grain boundaries 4 in the critical path 6, the number of free carriers existing in the critical path 6 is increased, and the potential barrier in the critical path 6 is reduced. Can be increased. Techniques for reducing the number of grain boundaries 4 in the critical path 6 include increasing the grain size of the crystal grains and controlling the position. As a specific method, various methods have been researched and developed as listed below. The concept of the present invention is effective in any manufacturing method as long as the structure described in the claims of the present invention is obtained.・ HJ Kim, Samsung Elect., Low-Temperature Poly
-Si TFT Technology, Proc.IDW '99, p147 ・ M. Matsumura, Tokyo Inst. Of Technol., Excimer-
Laser Processed Crystal-Si TFTs on Glass, Proc.Eu
ro Display '99, p351 ・ S. Maersch, Sopra, LACRASIL: Large Area Crystal
lization of AmorphousSilicon using a Mesa-shaped L
aser, Proc. Late-news Papers, Euro Display'99, p12
7 ・ K. Makihira, Kyushu Inst. Of Technol., Enhanced
Nucleation of a-Si Solid-Phase Crystallization by
Imprint Technology, Digest AM-LCD '99, p85 ・ M. Ozawa, Tokyo Inst. Of Technol., Excimer-Lase
r-Induced Lateral Crystallization in Pre-Patterned
Si Islands, Digest AM-LCD '99, p93 ・ R. Ishihara, Delft Univ. Of Technol., Microtext
ure Analysis of Location Controlled Large Grain Fo
rmed by Excimer-Laser Crystallization Method, Dige
st AM-LCD '99, p99 ・ C. Prat, SOPRA, Excimer-Laser Crystallization o
f Amorphous Silicon for Flat Panel Display Applica
tions: The Assets of a Long-Pulse Duration, Digest
AM-LCD '99, p115 ・ JS Im, Columbia Univ., Sequential Lateral So
lidification of Si Films for Polycrystalline and S
ingle Crystal Si TFTs, Digest AM-LCD '99, p229 ・ Y.Oana, Toshiba, Low Temperature Polycrystalli
ne Si TFT Technology for Liquid Crystal Displays,
Digest AM-LCD '99, p251 ・ C. -H. Oh, Tokyo Inst. Of Technol., Ultrahigh-P
erformance Low-Temperature "Poly-Si" TFTs, Digest
AM-LCD '99, p255 ・ A. Hara, Fujitsu Labs., A New Lateral Growth Me
thod of Poly-Silicon by Excimer Laser Irradiation,
Digest AM-LCD '99, p275 ・ L. Mariucci, CNR-IESS, A. Grain Location Contro
l by a Two-Pass Excimer Laser Crystallization Pro
cess, Digest AM-LCD '99, p283 ・ A. Mimura, Hitachi, Direct Laser Crystallizatio
n of PECVD a-Si for Flat and Large Poly-Si Grains
by New Multi-Chamber Processor, Digest AM-LCD '99,
p287 ・ JH.Jeon, Seoul National University, Excimer-L
aser Recrystallizationof Poly-Si Using Nucleation
Seeds, Digest SID '99, p382 ・ Z. Meng, The Hong Kong University of Science an
d Technology, Offset Metal-Induced Unilaterally Cr
ystallized Poly-Si TFTs, p386

[Brief description of the drawings]

FIG. 1 is a diagram showing a first example of a simulation of carrier conduction in a polycrystalline semiconductor. (A) shows a simulation result, and (b) shows a structure used for the simulation.

FIG. 2 is a diagram illustrating a second example of a simulation of carrier conduction in a polycrystalline semiconductor. (A) shows a simulation result, and (b) shows a structure used for the simulation.

FIG. 3 is a diagram showing a third example of a simulation of carrier conduction in a polycrystalline semiconductor. (A) shows a simulation result, and (b) shows a structure used for the simulation.

FIG. 4 is a diagram showing a fourth example of simulation of carrier conduction in a polycrystalline semiconductor. (A) shows a simulation result, and (b) shows a structure used for the simulation.

FIG. 5 is a diagram showing a fifth example of a simulation of carrier conduction in a polycrystalline semiconductor. (A) shows a simulation result, and (b) shows a structure used for the simulation.

FIG. 6 is a diagram showing a sixth example of a simulation of carrier conduction in a polycrystalline semiconductor. (A) shows a simulation result, and (b) shows a structure used for the simulation.

FIG. 7 is a diagram showing a seventh example of simulation of carrier conduction in a polycrystalline semiconductor. (A) shows a simulation result, and (b) shows a structure used for the simulation.

FIG. 8 is a diagram showing an eighth example of simulation of carrier conduction in a polycrystalline semiconductor. (A) shows a simulation result, and (b) shows a structure used for the simulation.

FIG. 9 is a view showing a ninth example of simulation of carrier conduction in a polycrystalline semiconductor. (A) shows a simulation result, and (b) shows a structure used for the simulation.

FIG. 10 is a diagram showing a tenth example of simulation of carrier conduction in a polycrystalline semiconductor. (A) shows a simulation result, and (b) shows a structure used for the simulation.

FIG. 11 is a diagram showing a polycrystalline semiconductor according to the first embodiment.

FIG. 12 is a sectional view of a polycrystalline thin film transistor according to the first embodiment.

FIG. 13 is a diagram showing a polycrystalline semiconductor according to a second embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Cathode 2 Anode 3 Crystal grain 4 Crystal grain boundary 5 Current flow line 6 Critical path 7 Polycrystalline semiconductor 8 Gate electrode 9 Gate insulating film 10 Source region 11 Drain region 12 MOS interface

Claims (4)

[Claims] 1. A polycrystalline semiconductor comprising: a polycrystalline semiconductor; a gate electrode; a gate insulating film between the polycrystalline semiconductor and the gate electrode; and a source region and a drain region in which a dopant is introduced into the polycrystalline semiconductor. In the thin film transistor, the polycrystalline semiconductor includes at least one critical path having a higher electric conductivity between the source region and the drain region than the others. 2. The polycrystalline thin film transistor according to claim 1, wherein MOS interface defects in the critical path are reduced. 3. The polycrystalline thin film transistor according to claim 1, wherein the number of crystal grain boundaries in the critical path is reduced. 4. The polycrystalline thin film transistor according to claim 1, wherein crystal grain boundary defects in the critical path are reduced.