JP2001209538A5 - - Google Patents

Download PDF

Info

Publication number
JP2001209538A5
JP2001209538A5 JP2001002040A JP2001002040A JP2001209538A5 JP 2001209538 A5 JP2001209538 A5 JP 2001209538A5 JP 2001002040 A JP2001002040 A JP 2001002040A JP 2001002040 A JP2001002040 A JP 2001002040A JP 2001209538 A5 JP2001209538 A5 JP 2001209538A5
Authority
JP
Japan
Prior art keywords
register identifier
decoding
attribute data
register
instruction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2001002040A
Other languages
English (en)
Japanese (ja)
Other versions
JP3756411B2 (ja
JP2001209538A (ja
Filing date
Publication date
Priority claimed from US09/490,389 external-priority patent/US6604192B1/en
Application filed filed Critical
Publication of JP2001209538A publication Critical patent/JP2001209538A/ja
Publication of JP2001209538A5 publication Critical patent/JP2001209538A5/ja
Application granted granted Critical
Publication of JP3756411B2 publication Critical patent/JP3756411B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

JP2001002040A 2000-01-24 2001-01-10 データハザードを検出するシステム Expired - Fee Related JP3756411B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/490389 2000-01-24
US09/490,389 US6604192B1 (en) 2000-01-24 2000-01-24 System and method for utilizing instruction attributes to detect data hazards

Publications (3)

Publication Number Publication Date
JP2001209538A JP2001209538A (ja) 2001-08-03
JP2001209538A5 true JP2001209538A5 (https=) 2005-06-02
JP3756411B2 JP3756411B2 (ja) 2006-03-15

Family

ID=23947830

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001002040A Expired - Fee Related JP3756411B2 (ja) 2000-01-24 2001-01-10 データハザードを検出するシステム

Country Status (2)

Country Link
US (1) US6604192B1 (https=)
JP (1) JP3756411B2 (https=)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7555634B1 (en) * 2004-04-22 2009-06-30 Sun Microsystems, Inc. Multiple data hazards detection and resolution unit
US20060200654A1 (en) * 2005-03-04 2006-09-07 Dieffenderfer James N Stop waiting for source operand when conditional instruction will not execute
US7454598B2 (en) * 2005-05-16 2008-11-18 Infineon Technologies Ag Controlling out of order execution pipelines issue tagging
US9710269B2 (en) 2006-01-20 2017-07-18 Qualcomm Incorporated Early conditional selection of an operand
US20090055636A1 (en) * 2007-08-22 2009-02-26 Heisig Stephen J Method for generating and applying a model to predict hardware performance hazards in a machine instruction sequence
US8205057B2 (en) * 2009-06-30 2012-06-19 Texas Instruments Incorporated Method and system for integrated pipeline write hazard handling using memory attributes
US9600280B2 (en) * 2013-09-24 2017-03-21 Apple Inc. Hazard check instructions for enhanced predicate vector operations
US9928069B2 (en) 2013-12-20 2018-03-27 Apple Inc. Predicated vector hazard check instruction

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USRE32493E (en) * 1980-05-19 1987-09-01 Hitachi, Ltd. Data processing unit with pipelined operands
US5471598A (en) * 1993-10-18 1995-11-28 Cyrix Corporation Data dependency detection and handling in a microprocessor with write buffer
US6073231A (en) * 1993-10-18 2000-06-06 Via-Cyrix, Inc. Pipelined processor with microcontrol of register translation hardware
US5765035A (en) * 1995-11-20 1998-06-09 Advanced Micro Devices, Inc. Recorder buffer capable of detecting dependencies between accesses to a pair of caches
US5860017A (en) 1996-06-28 1999-01-12 Intel Corporation Processor and method for speculatively executing instructions from multiple instruction streams indicated by a branch instruction
US5859999A (en) 1996-10-03 1999-01-12 Idea Corporation System for restoring predicate registers via a mask having at least a single bit corresponding to a plurality of registers
US6115808A (en) * 1998-12-30 2000-09-05 Intel Corporation Method and apparatus for performing predicate hazard detection
US6304955B1 (en) * 1998-12-30 2001-10-16 Intel Corporation Method and apparatus for performing latency based hazard detection
US6219781B1 (en) * 1998-12-30 2001-04-17 Intel Corporation Method and apparatus for performing register hazard detection
US6438681B1 (en) * 2000-01-24 2002-08-20 Hewlett-Packard Company Detection of data hazards between instructions by decoding register indentifiers in each stage of processing system pipeline and comparing asserted bits in the decoded register indentifiers

Similar Documents

Publication Publication Date Title
TWI501580B (zh) 資料串流的鑑別
US7036000B2 (en) Valid bit generation and tracking in a pipelined processor
US8933824B1 (en) Hardware decompression of deflate encoded data with multiple blocks
JP2001209538A5 (https=)
JP2006508592A5 (https=)
CN101206861B (zh) 数字音乐作品认证信息的嵌入方法及该作品的认证方法
MY151850A (en) Method for checking of video encoder and decoder state integrity
JP2001209537A5 (https=)
WO2002087087A3 (en) Protocol encoder and decoder
JP2006508414A5 (https=)
KR20090006014A (ko) 버전이 다른 ａｖｓ1-ｐ2 비트스트림을 시그널링하고디코딩하기 위한 방법 및 장치
CN104023266A (zh) 一种android系统的通信编解码组件的使用方法
JP2025016762A5 (https=)
WO2018119611A1 (zh) 多操作系统多媒体数据编解码方法、装置、电子设备和计算机程序产品
CN118535405A (zh) 基于指令机器码的动态指令测试序列生成方法、计算机设备和存储介质
WO2007065115A3 (en) Apparatus and method for decoding a received message with a priori information
CN101360060A (zh) 实现系统间数据交互的处理单元、数据发送/接收方法
WO2003071777A3 (en) Video processing
CN101009836A (zh) 基于双处理器的嵌入式视频播放装置
CN106878290A (zh) 音视频的播放方法及装置
JP3756411B2 (ja) データハザードを検出するシステム
WO2003055247A3 (en) Communications device, method and program for receiving process execution, and computer-readable recording medium having same program recorded thereon
WO2003098431A3 (en) Method and apparatus for decoding instruction sequences
WO2010001411A3 (en) A method and system on chip (soc) for adapting a runtime reconfigurable hardware to decode a video stream
CN100492314C (zh) 基于指令宽度的高效仿真调度的方法和系统