JP2001209537A5 - - Google Patents

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Publication number
JP2001209537A5
JP2001209537A5 JP2001002038A JP2001002038A JP2001209537A5 JP 2001209537 A5 JP2001209537 A5 JP 2001209537A5 JP 2001002038 A JP2001002038 A JP 2001002038A JP 2001002038 A JP2001002038 A JP 2001002038A JP 2001209537 A5 JP2001209537 A5 JP 2001209537A5
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JP
Japan
Prior art keywords
bits
registers
register identifier
decoding
connections
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Application number
JP2001002038A
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English (en)
Japanese (ja)
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JP2001209537A (ja
JP3756409B2 (ja
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Priority claimed from US09/490,392 external-priority patent/US6643762B1/en
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Publication of JP2001209537A publication Critical patent/JP2001209537A/ja
Publication of JP2001209537A5 publication Critical patent/JP2001209537A5/ja
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Publication of JP3756409B2 publication Critical patent/JP3756409B2/ja
Anticipated expiration legal-status Critical
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JP2001002038A 2000-01-24 2001-01-10 データハザード検出システム Expired - Fee Related JP3756409B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/490,392 US6643762B1 (en) 2000-01-24 2000-01-24 Processing system and method utilizing a scoreboard to detect data hazards between instructions of computer programs
US09/490392 2000-01-24

Publications (3)

Publication Number Publication Date
JP2001209537A JP2001209537A (ja) 2001-08-03
JP2001209537A5 true JP2001209537A5 (https=) 2005-06-02
JP3756409B2 JP3756409B2 (ja) 2006-03-15

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ID=23947846

Family Applications (1)

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JP2001002038A Expired - Fee Related JP3756409B2 (ja) 2000-01-24 2001-01-10 データハザード検出システム

Country Status (2)

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US (2) US6643762B1 (https=)
JP (1) JP3756409B2 (https=)

Families Citing this family (15)

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Publication number Priority date Publication date Assignee Title
US7373484B1 (en) * 2004-01-12 2008-05-13 Advanced Micro Devices, Inc. Controlling writes to non-renamed register space in an out-of-order execution microprocessor
US7487337B2 (en) * 2004-09-30 2009-02-03 Intel Corporation Back-end renaming in a continual flow processor pipeline
US7698536B2 (en) * 2005-08-10 2010-04-13 Qualcomm Incorporated Method and system for providing an energy efficient register file
US7370176B2 (en) * 2005-08-16 2008-05-06 International Business Machines Corporation System and method for high frequency stall design
US20090055636A1 (en) * 2007-08-22 2009-02-26 Heisig Stephen J Method for generating and applying a model to predict hardware performance hazards in a machine instruction sequence
US9311085B2 (en) * 2007-12-30 2016-04-12 Intel Corporation Compiler assisted low power and high performance load handling based on load types
TW201101177A (en) * 2009-06-23 2011-01-01 Rdc Semiconductor Co Ltd Microprocessor and data write-in method thereof
US9529596B2 (en) 2011-07-01 2016-12-27 Intel Corporation Method and apparatus for scheduling instructions in a multi-strand out of order processor with instruction synchronization bits and scoreboard bits
US9858077B2 (en) * 2012-06-05 2018-01-02 Qualcomm Incorporated Issuing instructions to execution pipelines based on register-associated preferences, and related instruction processing circuits, processor systems, methods, and computer-readable media
JP6024281B2 (ja) * 2012-08-21 2016-11-16 富士通株式会社 プロセッサ
CN103235716B (zh) * 2013-04-19 2016-03-02 中国科学院自动化研究所 一种用于检测流水线数据相关的装置
US10606591B2 (en) 2017-10-06 2020-03-31 International Business Machines Corporation Handling effective address synonyms in a load-store unit that operates without address translation
US10417002B2 (en) 2017-10-06 2019-09-17 International Business Machines Corporation Hazard detection of out-of-order execution of load and store instructions in processors without using real addresses
US11175924B2 (en) 2017-10-06 2021-11-16 International Business Machines Corporation Load-store unit with partitioned reorder queues with single cam port
EP4276625B1 (en) * 2018-01-29 2025-03-19 Micron Technology, Inc. Memory controller

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4903196A (en) * 1986-05-02 1990-02-20 International Business Machines Corporation Method and apparatus for guaranteeing the logical integrity of data in the general purpose registers of a complex multi-execution unit uniprocessor
US4891753A (en) * 1986-11-26 1990-01-02 Intel Corporation Register scorboarding on a microprocessor chip
WO1993020505A2 (en) * 1992-03-31 1993-10-14 Seiko Epson Corporation Superscalar risc instruction scheduling
US5630149A (en) * 1993-10-18 1997-05-13 Cyrix Corporation Pipelined processor with register renaming hardware to accommodate multiple size registers
US6108769A (en) * 1996-05-17 2000-08-22 Advanced Micro Devices, Inc. Dependency table for reducing dependency checking hardware
US5860017A (en) 1996-06-28 1999-01-12 Intel Corporation Processor and method for speculatively executing instructions from multiple instruction streams indicated by a branch instruction
US5859999A (en) 1996-10-03 1999-01-12 Idea Corporation System for restoring predicate registers via a mask having at least a single bit corresponding to a plurality of registers
US5784588A (en) * 1997-06-20 1998-07-21 Sun Microsystems, Inc. Dependency checking apparatus employing a scoreboard for a pair of register sets having different precisions
US6272520B1 (en) * 1997-12-31 2001-08-07 Intel Corporation Method for detecting thread switch events
US6266766B1 (en) * 1998-04-03 2001-07-24 Intel Corporation Method and apparatus for increasing throughput when accessing registers by using multi-bit scoreboarding with a bypass control unit
EP1004959B1 (en) * 1998-10-06 2018-08-08 Texas Instruments Incorporated Processor with pipeline protection
US6550001B1 (en) * 1998-10-30 2003-04-15 Intel Corporation Method and implementation of statistical detection of read after write and write after write hazards
US6219781B1 (en) * 1998-12-30 2001-04-17 Intel Corporation Method and apparatus for performing register hazard detection
US6304955B1 (en) * 1998-12-30 2001-10-16 Intel Corporation Method and apparatus for performing latency based hazard detection

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