JP2001203563A - Oscillation circuit and automatic frequency control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an oscillation circuit and an automatic frequency control circuit that can reduce jitter and can be used for horizontal deflection of a television receiver. SOLUTION: The automatic frequency control circuit has a capacitor C, a voltage detection circuit 2 that receives a voltage across the capacitor C, provides an output of a 1st voltage detection signal when the voltage across the capacitor C is greater than a predetermined 1st voltage and provides an output of a 2nd voltage detection signal when the voltage across the capacitor C is smaller than a predetermined 2nd voltage, a current changeover circuit 3 that receives the output of the voltage detection circuit 2, discharges the capacitor C with a predetermined 1st current when the output is the 1st voltage detection signal and charges the capacitor C with a predetermined 2nd current when the output is the 2nd voltage detection signal, and a frequency divider circuit 11 that receives an output signal from the voltage detection circuit 2 and provides an output of a signal after frequency division by the decided number of times, and the 1st and 2nd currents are selected to cancel jitter of the frequency of the voltage detection signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an oscillation circuit and an automatic frequency control circuit including the oscillation circuit, and more particularly to an oscillation circuit used for horizontal deflection of a television receiver and an automatic frequency control circuit including the oscillation circuit. It is about.

[0002]

2. Description of the Related Art In a television receiver, a horizontal deflection circuit which functions to deflect an electron beam of a picture tube to the left and right operates in synchronization with a horizontal synchronizing signal separated from a video signal. However, if the separated horizontal sync signal is input to the horizontal deflection circuit as it is, the screen becomes unstable due to the noise included in the horizontal sync signal, so the oscillation is automatically controlled to synchronize with the separated horizontal sync signal. A circuit is separately provided, and the horizontal deflection circuit is operated by this oscillation circuit. As described above, the control for matching the operating frequency of the horizontal deflection circuit with the frequency of the horizontal synchronization signal included in the video signal is referred to as AFC (Automatic Frequency Control).
Automatic frequency control) is called A
Called FC circuit.

FIG. 3 is a diagram showing a conventional oscillation circuit used for an AFC circuit. 3, 1 is a capacitor, 10A is an oscillation circuit, 2 is a voltage detection circuit, 21 is a buffer amplifier, 22 and 23 are comparators, 2
4 and 25 are comparison voltages; 26 is a voltage detection output circuit;
A is a current switching circuit, 31A and 32A are current sources,
Represents a switching circuit.

[0004] The capacitor 1 is charged and discharged by a current source of a current switching circuit 3A, and a charged voltage is monitored by a voltage detection circuit 2.

[0005] The voltage detection circuit 2 monitors the voltage charged in the capacitor 1, and when the charging voltage becomes larger than a certain voltage and when the charging voltage becomes smaller than the certain voltage, the change is detected. Is output to the current switching circuit 3A.

The voltage detection circuit 2 includes a buffer amplifier 21, comparators 22 and 23, a comparison voltage 2
4, 25, and a voltage detection output circuit 26.
The buffer amplifier 21 detects the charging voltage of the capacitor 1 and outputs the detected voltage to the comparators 22 and 23. The buffer amplifier 21 has such an input impedance that charging and discharging of the capacitor 1 performed by its own input is negligible compared to charging and discharging by the current switching circuit 3A. The comparator 22 is a buffer amplifier 2
1 and the output of the comparison voltage 24, the two voltages are compared, and a signal corresponding to the magnitude is output to the voltage detection output circuit 26. The comparator 23 receives the output of the buffer amplifier 21 and the output of the comparison voltage 25, compares the two voltages, and outputs a signal according to the magnitude to the voltage detection output circuit 26. The comparison voltages 24 and 25 output voltages for comparison with the buffer amplifier 21 to the comparators 22 and 23, respectively. The comparison voltages 24 and 25 are
It receives a signal S50 for controlling the oscillation frequency of A, and changes the voltage output to the comparators 22 and 23 according to this signal. Voltage detection output circuit 26 receives the signals from comparators 22 and 23, and outputs signal S10 corresponding to this signal to current switching circuit 3A.

The current switching circuit 3A receives the output signal S10 from the voltage detection circuit 2, and supplies a current for discharging or charging the electric charge stored in the capacitor 1. This current switching circuit 3A specifically includes current sources 31A and 32
A, a switching circuit 33 is provided. Current sources 31A and 3
2A is a current source for passing a constant DC current,
3 is connected. The switching circuit 33 includes the voltage detection circuit 2
And the current source 31A or 3
2A is connected to the capacitor 1.

Next, the conventional oscillation circuit 1 having the above-described configuration will be described.
The operation at 0A will be described. The capacitance 1 has been charged by the current source 31A of the current switching circuit 3A or has been discharged by the current source 32A. Current source 3
Since the currents due to 1A and 32A are DC currents, the voltage on capacitor 1 increases or decreases linearly with time.

The voltage of the capacitor 1 which changes linearly in this manner is input to comparators 22 and 23 via a buffer amplifier 21 and is compared with comparison voltages 24 and 25.
Is compared to These two circuits with comparators 22 and 23 and comparison voltages 24 and 25
The upper and lower limits of the voltage to be charged are determined. In the following description, it is assumed that the buffer amplifier is non-inverted, the comparison voltage 24 determines the upper limit, and the comparison voltage 25 determines the lower limit.

For example, when the output voltage of the buffer amplifier 2 increases with time and exceeds the voltage value of the comparison voltage 24,
The output voltage of the comparator 22 is inverted. The voltage detection output circuit 26 having received the output voltage supplies the switching voltage 33 of the current switching circuit 3A to the comparison voltage 2
A signal indicating that the voltage has exceeded the upper limit voltage defined in FIG. When the output voltage of the buffer amplifier 2 decreases with time and falls below the voltage value of the comparison voltage 25, the output voltage of the comparator 23 is inverted. The voltage detection output circuit 26 receiving the output voltage outputs a signal to the switching circuit 33 of the current switching circuit 3A indicating that the charging voltage of the capacitor 1 has fallen below the lower limit voltage defined by the comparison voltage 25.

The switching circuit 32 receiving the output signal of the voltage detection output circuit 26 connects the current source 31A or 32A to the capacitor 1 according to the output signal. If the output signal of the voltage detection output circuit 26 is a signal indicating that the voltage exceeds the upper limit voltage, the current source 32A is connected to the capacitor 1 to discharge the voltage of the capacitor 1, and the voltage of the capacitor 1 exceeds the predetermined upper limit. Do not exceed. When the output signal of the voltage detection output circuit 26 is a signal indicating that the voltage is lower than the lower limit voltage, the current source 32A is connected to the capacitor 1 to charge the capacitor 1, and the voltage of the capacitor 1 is determined. Do not fall below the lower limit. Therefore, the voltage of the capacitor 1 has a sawtooth waveform that linearly changes with time between the upper limit voltage and the lower limit voltage determined by the comparison voltages 24 and 25.

The oscillation frequency of the sawtooth waveform includes the voltage values of the comparison voltages 24 and 25, the capacitance value of the capacitor 1,
Alternatively, since the oscillation frequency is determined depending on the current values of the current sources 31A and 32A, in order to vary the oscillation frequency in accordance with the control voltage, any one of these may be controlled by voltage. . In the example of FIG.
Although the frequency is controlled by varying the voltage values of 4 and 25 according to the signal S50, the oscillation frequency can be controlled by varying the current values of the current sources 31A and 32A according to the signal S50. .

FIG. 4 shows a conventional AF used for horizontal deflection.
It is a figure showing C circuit. 4, 10A denotes an oscillation circuit, 40 denotes a phase comparison circuit, 50 denotes a low-pass filter, 60 denotes a horizontal deflection circuit, S1 denotes a horizontal synchronization signal, and S1 denotes a horizontal synchronization signal.
2 indicates a horizontal deflection drive signal.

The horizontal synchronizing signal S1 is a horizontal synchronizing signal separated from a video signal by a preceding synchronizing circuit (not shown). The horizontal deflection drive signal S2 is supplied to the horizontal deflection circuit 60.
, A pulse signal extracted from, for example, one winding of a flyback transformer of a horizontal deflection drive circuit for driving a picture tube, the frequency of which is equal to the operating frequency of the horizontal deflection circuit.

The phase comparison circuit 40 has a horizontal synchronizing signal S1.
And a horizontal deflection drive signal S2 to detect the phase difference between the two signals, and pass a low-pass signal containing a DC voltage component corresponding to the advance or delay of the phase of the horizontal deflection drive signal S2 with respect to the horizontal synchronization signal S1. Output to the filter 50.
The low-pass filter 50 receives the output signal of the phase comparison circuit 40, and among the components of each frequency included in the signal,
A signal having a frequency lower than the determined cutoff frequency is output to the oscillation circuit 10A. The oscillation circuit 10A receives the output signal of the low-pass filter 50, and converts the signal whose oscillation frequency is changed according to the amplitude of the output signal into a horizontal deflection circuit 60A.
Output to The horizontal deflection circuit 60 includes the low-pass filter 5
Upon receiving the output signal of 0, the picture tube is driven at a frequency synchronized with the output signal. Then, a horizontal deflection drive signal S2 that matches this operating frequency is output to the phase comparison circuit 40.

Next, the operation of the conventional AFC circuit having the above configuration will be described. Upon receiving the horizontal synchronization signal S1 and the horizontal deflection drive signal, the phase comparison circuit 40 detects a phase difference between the two and outputs a signal including a DC voltage component corresponding to the phase difference. The low-pass filter 50 outputs, to the oscillation circuit 10A, a signal obtained by attenuating a high frequency component that cannot be controlled by the AFC included in the output of the phase comparison circuit 40.
The low-pass filter 50 has a transfer characteristic for compensating the stability of the feedback control of the AFC.

The oscillation circuit 10A receives the output signal of the low-pass filter 50 and changes the oscillation frequency. Specifically, the horizontal synchronization signal S1 and the horizontal deflection drive signal S2
If the phase of the horizontal synchronization signal S1 is advanced, the oscillation frequency is lowered. If the phase of the horizontal deflection drive signal S2 is behind the horizontal synchronization signal S1, the oscillation frequency is increased. The oscillation frequency is controlled by the output signal of the low-pass filter 50 so that the phase difference is reduced. In this way, the operating frequency of the horizontal deflection circuit 60 receiving the output signal of the oscillation circuit 10A is controlled so as to match the horizontal synchronization signal S1.

[0018]

A conventional oscillation circuit 10A
As described above, in an oscillation circuit whose oscillation frequency is determined by the charging voltage of the capacitor 1, if a current due to noise flows through the capacitor 1 and the capacitor 1 is charged, an error in the charging voltage due to the noise current directly becomes an error in the oscillation frequency. .
Noise causing an oscillation frequency error includes, in addition to externally received noise, thermal noise and shot noise generated from elements such as resistors and transistors used in the oscillation circuit. It is difficult to take countermeasures against internal noise generated inside such a circuit, since direct measures such as removing or shielding a noise source like external noise cannot be taken. On the other hand, in a large-screen television receiver which has been increasing recently, there is a problem that even a slight fluctuation (jitter) of the oscillation frequency of the horizontal deflection circuit caused by the internal noise affects the visual sense of the screen.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an oscillation circuit capable of reducing jitter and an automatic frequency control circuit including the oscillation circuit. An object of the present invention is to provide an oscillation circuit used for horizontal deflection and capable of reducing jitter, and an automatic frequency control circuit including the oscillation circuit.

[0020]

In order to achieve the above object, an oscillation circuit according to the present invention receives a capacitor and a charging voltage of the capacitor, and when the charging voltage becomes larger than a first comparison voltage. A voltage detection circuit that outputs a first voltage detection signal, and outputs a second voltage detection signal when the charging voltage becomes lower than the second comparison voltage; and receives an output signal of the voltage detection circuit. When the output signal is a first voltage detection signal, the capacitor discharges the capacitor with a first current, and when the voltage detection signal is a second voltage detection signal, charges the capacitor with a second current. A switching circuit, wherein the first current and the second current are set to have magnitudes that can cancel the effect of jitter occurring on the frequency of the voltage detection signal.

The oscillation circuit according to the present invention has a frequency dividing circuit which receives an output signal of the voltage detecting circuit and outputs a signal having a predetermined dividing ratio with respect to the output signal.

The automatic frequency control circuit of the present invention receives the first and second signals, detects a phase difference between the first and second signals, and controls a frequency according to the phase difference. Receiving a phase comparison circuit that outputs a third signal, a capacitor, and a charging voltage of the capacitor, and outputting a first voltage detection signal when the charging voltage becomes higher than the first comparison voltage; Outputting a second voltage detection signal when the charging voltage becomes lower than the second comparison voltage; receiving the third signal; receiving the first signal in response to the third signal;
A voltage detection circuit that changes the comparison voltage and the second comparison voltage, and an output signal of the voltage detection circuit. When the output signal is a first voltage detection signal, the capacitor is turned on by a first current. Discharging, and when the voltage detection signal is a second voltage detection signal, a current switching circuit for charging the capacitor with a second current, wherein the first current and the second current are The magnitude is set so that the influence of the jitter generated on the frequency of the detection signal can be offset.

The automatic frequency control circuit of the present invention receives the first and second signals, detects the phase difference between the first and second signals, and controls the frequency according to the phase difference. Receiving a phase comparison circuit that outputs a third signal, a capacitor, and a charging voltage of the capacitor, and outputting a first voltage detection signal when the charging voltage becomes higher than the first comparison voltage; A voltage detection circuit that outputs a second voltage detection signal when the charging voltage is lower than the second comparison voltage; and receiving the output signal of the voltage detection circuit, the output signal is the first voltage detection signal. In this case, the capacitor is discharged by a first current, and when the voltage detection signal is a second voltage detection signal, the capacitor is charged by a second current, and the third signal is received by receiving the third signal. Above according to the signal of And a current switching circuit for changing the first current and the second current, wherein the first current and the second current are large enough to cancel the effect of jitter occurring on the frequency of the voltage detection signal. Is set to

The automatic frequency control circuit of the present invention has a frequency dividing circuit which receives an output signal of the voltage detecting circuit and outputs a signal having a predetermined dividing ratio with respect to the output signal.

In the automatic frequency control circuit according to the present invention, the deflection circuit for receiving the output signal of the frequency dividing circuit, generating a magnetic field according to the output signal, and outputting the second signal synchronized with the magnetic field is provided. Have.

According to the oscillation circuit of the present invention, the capacitor is charged or discharged by the current switching circuit. The charging voltage of the capacitor, which is increasing or decreasing due to the charging or discharging, is monitored by the voltage detection circuit.

In the case where the capacitor is charged by the current switching circuit and the voltage of the capacitor increases, when the voltage becomes larger than the first comparison voltage, the voltage detection circuit causes the current switching circuit to add the voltage to the capacitor. First
Is output. The current switching circuit that has received the first voltage detection signal discharges the capacitor with the first current, so that the voltage of the capacitor changes from increasing to decreasing. When the capacitor is discharged by the first current of the current switching circuit and the voltage of the capacitor decreases, the voltage is reduced to the second voltage.
The voltage detection circuit outputs the second voltage detection signal to the current switching circuit. The current switching circuit that receives the second voltage detection signal charges the capacitor with the second current, so that the voltage of the capacitor changes from decreasing to increasing.

As described above, the charging voltage of the capacitor oscillates while repeatedly increasing and decreasing within the range of the upper and lower limits defined by the first and second voltages. The capacitor is also charged and discharged by current due to noise, which causes jitter in the oscillation frequency. The first and second currents are large enough to cancel the influence of jitter on the current due to noise. Therefore, the jitter of the oscillation frequency is reduced.

The voltage detection circuit outputs the voltage detection signal with reduced jitter to the frequency dividing circuit. The frequency dividing circuit having received the output signal of the voltage detecting circuit outputs a signal having a predetermined frequency dividing ratio with respect to the output signal.

According to the automatic frequency control circuit of the present invention, the phase comparison circuit receives the first and second signals,
The phase difference between the first and second signals is detected. And a third for controlling the frequency according to the detected phase difference.
Is output to the voltage detection circuit.

The voltage detection circuit receives the third signal and changes the first comparison voltage and the second comparison voltage according to the third signal.

On the other hand, the charging voltage of the capacitor oscillates while repeatedly increasing and decreasing within the range defined by the first and second comparison voltages, the upper and lower limits. Specifically, in the case where the capacitor is charged by the current switching circuit and the voltage of the capacitor increases, when the voltage becomes larger than the first comparison voltage, the voltage detection circuit is connected to the current switching circuit. To output the first voltage detection signal. The current switching circuit that has received the first voltage detection signal discharges the capacitor with the first current, so that the voltage of the capacitor changes from increasing to decreasing. In a case where the capacitor is discharged by the first current of the current switching circuit and the voltage of the capacitor decreases, when the voltage is smaller than the second comparison voltage, the voltage detection circuit is configured to perform The second voltage detection signal is output to the current switching circuit. The current switching circuit that receives the second voltage detection signal charges the capacitor with the second current, so that the voltage of the capacitor changes from decreasing to increasing.

The capacitor is also charged and discharged by a current due to noise, which causes jitter in the oscillation frequency. The first and second currents cancel the influence of the jitter on the current due to the noise. Since the size is set as large as possible, the jitter of the oscillation frequency is reduced.

The first and second comparison voltages are related to the oscillation frequency of the voltage detection signal.
When the range of the voltage having the first comparison voltage as the upper limit and the second comparison voltage as the lower limit becomes wider, the oscillation frequency becomes lower,
As the voltage range becomes narrower, the oscillation frequency becomes higher. Thus, the frequency of the voltage detection signal is changed by the third signal from the phase comparison circuit. The frequency dividing circuit receiving the voltage detection signal outputs a signal having a frequency dividing ratio determined with respect to the output signal.

The output signal of the frequency dividing circuit is input to the deflecting circuit, and upon receiving the signal, the deflecting circuit generates a magnetic field for deflecting the electron beam at the frequency of the output signal. The deflection circuit outputs the second signal synchronized with the magnetic field to the phase comparison circuit.

For example, when the phase of the second signal is ahead of the phase of the first signal, the phase comparator detecting the phase difference outputs the third signal according to the detected phase difference. The frequency of the voltage detection signal by the voltage detection circuit that has received the third signal changes in a decreasing direction. The frequency of the output signal of the frequency divider receiving the voltage detection signal also decreases, and the frequency of the second signal by the deflection circuit that receives the output signal also decreases. Thereby, the second
Is delayed, and the phase difference between the first and second signals decreases. When the phase of the second signal is behind the phase of the first signal, the phase comparison circuit that detects the phase difference outputs the third signal according to the phase difference. The frequency of the voltage detection signal by the voltage detection circuit receiving the third signal changes in a rising direction. The frequency of the output signal of the frequency dividing circuit receiving the voltage detection signal also increases, and the frequency of the second signal by the deflection circuit receiving the output signal also increases. As a result, the phase of the second signal advances, and the phase difference between the first and second signals decreases. In this way, the operating frequency of the deflection circuit in the automatic frequency control circuit according to the present invention is controlled so as to match the first signal.

According to the automatic frequency control circuit of the present invention, the phase comparison circuit receives the first and second signals,
The phase difference between the first and second signals is detected. And a third for controlling the frequency according to the detected phase difference.
Is output to the current switching circuit.

The current switching circuit receives the third signal and changes the first current and the second current according to the third signal.

On the other hand, the charging voltage of the capacitor oscillates while repeatedly increasing and decreasing within a range where the upper and lower limits are determined by the first and second comparison voltages. Specifically, in the case where the capacitor is charged by the current switching circuit and the voltage of the capacitor increases, when the voltage becomes larger than the first comparison voltage, the voltage detection circuit is connected to the current switching circuit. To output the first voltage detection signal. The current switching circuit that has received the first voltage detection signal discharges the capacitor with the first current, so that the voltage of the capacitor changes from increasing to decreasing. In a case where the capacitor is discharged by the first current of the current switching circuit and the voltage of the capacitor decreases, when the voltage is smaller than the second comparison voltage, the voltage detection circuit is configured to perform The second voltage detection signal is output to the current switching circuit. The current switching circuit that receives the second voltage detection signal charges the capacitor with the second current, so that the voltage of the capacitor changes from decreasing to increasing.

The capacitor is also charged and discharged by the current caused by noise, which causes jitter in the oscillation frequency. The first and second currents offset the influence of the jitter on the current caused by the noise. Since the size is set as large as possible, the jitter of the oscillation frequency is reduced.

The first current and the second current are related to the oscillation frequency of the voltage detection signal. Specifically, the oscillation frequency decreases as the first current and the second current decrease. As the frequency increases, the oscillation frequency increases. Thus, the frequency of the voltage detection signal is changed by the third signal from the phase comparison circuit.
The frequency dividing circuit receiving the voltage detection signal outputs a signal having a frequency dividing ratio determined with respect to the output signal.

The output signal of the frequency dividing circuit is input to the deflecting circuit. Upon receiving the signal, the deflecting circuit generates a magnetic field for deflecting the electron beam at the frequency of the output signal. The deflection circuit outputs the second signal synchronized with the magnetic field to the phase comparison circuit.

For example, when the phase of the second signal is ahead of the phase of the first signal, the phase comparison circuit that detects the phase difference outputs the third signal according to the phase difference. When the current switching circuit receives the third signal, the first or second current decreases, whereby the frequency of the voltage detection signal changes in a decreasing direction. The frequency of the output signal of the frequency divider receiving the voltage detection signal also decreases, and the frequency of the second signal by the deflection circuit that receives the output signal also decreases. Thus, the phase of the second signal is delayed, and the phase difference between the first and second signals decreases.
When the phase of the second signal is behind the phase of the first signal, the phase comparison circuit that detects the phase difference outputs the third signal according to the phase difference. When the current switching circuit receives the third signal, the first or second current increases, whereby the frequency of the voltage detection signal changes in an increasing direction. The frequency of the output signal of the frequency dividing circuit receiving the voltage detection signal also increases, and the frequency of the second signal by the deflection circuit receiving the output signal also increases. Thereby, the phase of the second signal advances, and the first signal
And the phase difference of the second signal is reduced. In this way, the operating frequency of the deflection circuit in the automatic frequency control circuit according to the present invention is controlled so as to match the first signal.

[0044]

FIG. 1 is a diagram showing an embodiment of an oscillation circuit of the present invention used in an AFC circuit. 3 and 1 represent the same contents. In addition, FIG.
In the figure, 10 denotes an oscillation circuit, 11 denotes a frequency dividing circuit, 3 denotes a current switching circuit, and 31 and 32 denote current sources. The operation of the oscillation circuit 10 for receiving the signal S50 for controlling the oscillation frequency and inputting the output signal S10 to the frequency dividing circuit 11 is based on the conventional oscillation circuit 10A used for horizontal deflection shown in FIG.
Is the same as However, the current values of the current sources 31 and 32 of the current switching circuit 3 for charging and discharging the capacitor 1 are the same as the current sources 31A and 32A of the current switching circuit 3A of the conventional oscillation circuit 10A.
It is set to be larger than. In the example of FIG. 1, the frequency is controlled by varying the voltage values of the comparison voltages 24 and 25 according to the signal S50.
The oscillation frequency can be controlled by varying the current values of 1A and 32A according to the signal S50. The frequency dividing circuit 11 receives a signal from the voltage detecting circuit 26 of the oscillating circuit 10, performs frequency dividing for a predetermined number of times, and outputs a signal of the result.

The operation of the oscillation circuit of FIG. 1 will be described. The oscillation circuit 10 receives a signal S50 for controlling the oscillation frequency,
A signal S10 having a frequency corresponding to this signal is input to the frequency dividing circuit 11. However, the current value for charging and discharging the capacitor 1 by the current switching circuit 3 is set to be larger than that of the current switching circuit 3A of the conventional oscillation circuit 10A shown in FIG. 3, so that the time for charging and discharging the capacitor 1 becomes shorter. Thus, the oscillation cycle of the oscillation circuit 10 becomes shorter than the oscillation cycle of the oscillation circuit 10A. The frequency dividing circuit 11 receiving the signal S10 performs an appropriate number of times of frequency division, for example, P, to compensate for the oscillation period shortened due to the above, and outputs the resulting signal S11.

As shown in FIG. 1, the current for charging / discharging the capacitor 1 is increased, and the frequency divider 11
, The jitter of the oscillation frequency due to noise generated inside the oscillation circuit 10 can be reduced. The reason will be described below.

In the following description, the oscillation cycle is T, the capacitance value of the capacitor 1 is C, and the current flowing through the capacitor 1 is i
And This current i is a DC current I from the current source 31 when the capacitor 1 is charged, and a DC current −I from the current source 32 when the capacitor 1 is discharged. Since the magnitudes of the charging current and the discharging current are equal, the voltage waveform of the capacitor 1 becomes a triangular wave in which the charging period and the discharging period are equal. The voltage from the upper limit voltage to the lower limit voltage of the triangular wave, that is, the voltage at which the capacitor is charged or discharged during a half cycle is denoted by V.

Generally, the voltage v charged in the capacitor C by the current i is expressed by the following equation.

[0049]

(Equation 1)

According to the equation (1), when the current i flowing through the capacitor 1 is integrated for a half period (T / 2) from the point of switching between the charge and the discharge, the capacitor 1 is charged or discharged during this period. The voltage V is represented by the following equation.

[0051]

(Equation 2)

The period T is expressed by the following equation from the equation (2).

[0053]

(Equation 3)

Here, a case is considered where the noise current in flows into the capacitor 1 to cause a jitter of ΔT during one cycle. Assume that the time point of the voltage V = 0 is time 0, at which time the capacitor 1 starts charging, ends the discharge at time T + ΔT, and returns to the original voltage V = 0. If this one cycle including the jitter ΔT is integrated by equation (1), the following equation is established.

[0055]

(Equation 4)

[0056]

(Equation 5)

The first term of the equation (5) is 0 because the current i in the ideal state without jitter is integrated in one cycle. The current i of the second term is equal to the DC current −I from the current source 32 if ΔT is sufficiently small. Therefore, the following equation is established.

[0058]

(Equation 6)

Thus, the jitter ΔT is expressed by the following equation.

[0060]

(Equation 7)

From equation (7), it can be seen that the jitter is proportional to the integrated value of the noise current generated in that cycle.

If it is considered that this jitter ΔT is caused by a virtually generated noise voltage vn, then from equation (1), v
n can be defined as:

[0063]

(Equation 8)

From the expressions (7) and (8), the jitter ΔT is expressed by the following expression.

(Equation 9)

In the equation (9), if the jitter is ΔT when the current is increased by P times while the capacitance C is kept as it is, it is expressed by the following equation.

[0066]

(Equation 10)

From this equation, it can be seen that when the current is increased P times, the jitter is reduced to 1 / P. However, the period T becomes 1 / P from the relationship of the equation (3). next,
A case is considered in which a frequency divider circuit 11 for performing P frequency division is provided at the subsequent stage of the oscillator 10 to restore the cycle. Since the jitters ΔT ′ generated in each cycle are uncorrelated with each other, the jitter ΔT after P frequency division becomes ΔP times the jitter ΔT ′, and the following equation is established.

[0068]

[Equation 11]

Comparing the above equation with the equation (9), the jitter is √
It turns out that it becomes 1 / P. Therefore, if the current i is P
In the subsequent stage of the oscillation circuit 10 in which the period T is reduced to 1 / P,
By inserting the frequency dividing circuit 11, the output jitter of the oscillation circuit 10 can be reduced to 1 / P.

Further, if a frequency dividing circuit of P dividing is inserted in the subsequent stage of the oscillating circuit in which the current i is multiplied by Q and the cycle is reduced to 1 / P,
The output jitter of the oscillation circuit is ΔP for Q. Therefore, in this case, if Q is set to be larger than ΔP, the output jitter can be reduced. In order to reduce the period T to 1 / P, the relationship of equation (3) is used. Since the current I is Q times, if the capacitance C and the voltage V are determined so that the product of the capacitance C and the voltage V becomes Q for P, the period T can be reduced to 1 / P.

For example, the jitter when the current I is set to six times, the capacity C is set to one half, and the period T is set to one sixteenth.
T ′ is represented by the following equation from equations (8) and (9).

[0072]

(Equation 12)

From the above equation, the jitter is 6 times smaller than the original magnitude.
It turns out that it becomes 1 /. Then, the jitter of the output obtained by inserting a frequency divider of 16 at the subsequent stage of the oscillator 10 is less than ΔT.

[0074]

(Equation 13)

Therefore, the jitter is reduced by the conventional oscillation circuit 10.
(3) Since the period of the oscillation circuit can be reduced to two thirds compared with A and the period of the oscillation circuit is reduced to one sixteenth.
From the equation, the voltage V is as follows.

[0076]

[Equation 14]

From this equation, it can be seen that the voltage V becomes 3/4. Therefore, in the case of this example, the voltage of the circuit can be reduced in addition to the improvement of the jitter.

As described above, according to the oscillation circuit of the present invention, the frequency dividing circuit for increasing the current flowing through the capacitor 1 of the conventional oscillation circuit shown in FIG. 3 and thereby compensating for the shortened oscillation cycle is provided. By providing it at the subsequent stage, the capacitor 1
Of the oscillation cycle due to the noise current flowing through the circuit can be reduced. In addition, by appropriately setting the current of the capacitor 1, the capacitance C of the capacitor, and the oscillation cycle, not only the jitter can be reduced, but also the amplitude of the oscillation can be reduced, and the voltage of the circuit can be reduced.

Next, an embodiment of the AFC circuit according to the present invention will be described. FIG. 2 is a diagram illustrating an AFC circuit of the present invention used for horizontal deflection. Conventional AF shown in FIG.
The difference from the C circuit is that the oscillation circuit 10A is changed to the oscillation circuit 10 and that the frequency divider 10 is inserted at the subsequent stage of the oscillation circuit 10.

The operation of the AFC circuit according to the present invention having the configuration shown in FIG. 2 will be described. Upon receiving the horizontal synchronization signal S1 and the horizontal deflection drive signal, the phase comparison circuit 40 detects a phase difference between the two and outputs a signal including a DC voltage component corresponding to the phase difference. The low-pass filter 50 outputs to the oscillation circuit 10 a signal obtained by attenuating a high frequency component that cannot be controlled by the AFC included in the output of the phase comparison circuit 40. The low-pass filter 50 has a transfer characteristic for compensating the stability of the feedback control of the AFC.

The oscillation circuit 10 receives the output signal of the low-pass filter 50 and changes the oscillation frequency. The difference from the conventional AFC circuit shown in FIG. 4 is that the current value of the current switching circuit 3 for charging and discharging the capacitor 1 of the oscillation circuit 10 shown in FIG.
Since the current switching circuit 3A of the conventional oscillation circuit 10A is set to be larger than that of the current switching circuit 3A, the frequency of the output signal
This is higher than 0A.

Upon receiving the output of the oscillation circuit 10, the frequency dividing circuit 1
1 is a circuit for converting a signal having a predetermined frequency division ratio into a horizontal deflection circuit 60.
Output to The frequency division ratio is set to a value that compensates for the increase in the frequency of the output signal as compared with that of the oscillation circuit 10A as described above.

The method of controlling the oscillation frequency is the same as that of the conventional AFC circuit shown in FIG. That is, when the phase of the horizontal deflection drive signal S2 is advanced with respect to the horizontal synchronization signal S1, the oscillation frequency is decreased, and when the phase of the horizontal deflection drive signal S2 is delayed with respect to the horizontal synchronization signal S1, the oscillation frequency is increased. The oscillation frequency is controlled by the output signal of the low-pass filter 50 so that the phase difference between the horizontal synchronization signal S1 and the horizontal deflection drive signal S2 is reduced. In this way, the operating frequency of the horizontal deflection circuit 60 that has received the output signal of the frequency dividing circuit 11 is controlled so as to match the horizontal synchronization signal S1.

As described in the embodiment of the oscillation circuit of FIG. 1, the oscillation circuit 10 configured to increase the current for charging / discharging the capacitor 1 and the oscillation circuit of the frequency dividing circuit 11
Oscillation frequency jitter is reduced. Therefore, the AFC circuit according to the present invention including the oscillation circuit 10 and the oscillation circuit having the configuration of the frequency dividing circuit 11 can operate the horizontal deflection circuit 60 with a signal with reduced jitter as compared with the conventional AFC circuit. it can.

[0085]

According to the present invention, the jitter generated at the frequency of the oscillation circuit can be reduced by increasing the current for charging / discharging the capacitor and inserting the frequency dividing circuit at the subsequent stage of the oscillation circuit. Further, by using the oscillation circuit, the deflection circuit can be driven by a signal with reduced jitter.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of an oscillation circuit of the present invention used in an AFC circuit.

FIG. 2 shows an AFC of the present invention used for horizontal deflection.
FIG. 3 illustrates an embodiment of a circuit.

FIG. 3 is a diagram showing a conventional oscillation circuit used for an AFC circuit.

FIG. 4 is a diagram showing a conventional AFC circuit used for horizontal deflection.

[Explanation of symbols]

10 oscillation circuit, 11 frequency divider circuit, 2 voltage detection circuit,
21: buffer amplifier, 22, 23: comparator, 2
4, 25: comparison voltage, 26: voltage detection output circuit, 3: current switching circuit, 31, 32: current source, 33: switching circuit, 4
0: phase comparison circuit, 50: low-pass filter, 60: deflection circuit.

Claims (8)

[Claims] A first voltage detection signal that is output when the charging voltage is higher than a first comparison voltage, the first voltage detection signal being output when the charging voltage is higher than a first comparison voltage; A voltage detection circuit for outputting a second voltage detection signal when the voltage becomes lower than a voltage; receiving the output signal of the voltage detection circuit, if the output signal is a first voltage detection signal, the first current A current switching circuit that discharges the capacitor and charges the capacitor with a second current when the voltage detection signal is a second voltage detection signal, wherein the first current and the second current are An oscillation circuit that is set to a size that can offset the effect of jitter generated on the frequency of the voltage detection signal. 2. Receiving an output signal of the voltage detection circuit,
2. The oscillation circuit according to claim 1, further comprising a frequency dividing circuit that outputs a signal having a frequency dividing ratio determined for the output signal. 3. Receiving the first and second signals, detecting a phase difference between the first and second signals, and outputting a third signal for controlling a frequency according to the phase difference. Receiving a charge voltage of the capacitor, outputting a first voltage detection signal when the charge voltage becomes higher than the first comparison voltage, and detecting the charge voltage in the second comparison circuit; A second voltage detection signal is output when the voltage becomes lower than the voltage, the third signal is received, and the first comparison voltage and the second comparison voltage are changed according to the third signal. A voltage detection circuit, receiving an output signal of the voltage detection circuit, and discharging the capacitor by a first current when the output signal is a first voltage detection signal; In the case of a signal, the second current A current switching circuit for charging a capacitor, wherein the first current and the second current are set to have a magnitude that can cancel the influence of jitter generated on the frequency of the voltage detection signal. circuit. 4. Receiving the first and second signals, detecting a phase difference between the first and second signals, and outputting a third signal for controlling a frequency according to the phase difference. Receiving a charge voltage of the capacitor, outputting a first voltage detection signal when the charge voltage becomes higher than the first comparison voltage, and detecting the charge voltage in the second comparison circuit; A voltage detection circuit for outputting a second voltage detection signal when the voltage becomes lower than a voltage; receiving the output signal of the voltage detection circuit, if the output signal is a first voltage detection signal, the first current Discharging the capacitor, charging the capacitor with a second current if the voltage detection signal is a second voltage detection signal, receiving the third signal, and responding to the third signal in response to the third signal; 1 current and the second current And a current switching circuit for changing the frequency of the voltage detection signal, wherein the first current and the second current are set to have a magnitude capable of canceling the influence of jitter generated in the frequency of the voltage detection signal. . 5. Receiving an output signal of the voltage detection circuit,
4. The automatic frequency control circuit according to claim 3, further comprising a frequency dividing circuit that outputs a signal having a predetermined frequency dividing ratio with respect to the output signal. 6. Receiving an output signal of the voltage detection circuit,
5. The automatic frequency control circuit according to claim 4, further comprising a frequency dividing circuit that outputs a signal having a predetermined frequency dividing ratio with respect to the output signal. 7. The deflecting circuit according to claim 5, further comprising a deflection circuit which receives an output signal of the frequency dividing circuit, generates a magnetic field according to the output signal, and outputs the second signal synchronized with the magnetic field. Automatic frequency control circuit. 8. The deflecting circuit according to claim 6, further comprising: a deflection circuit that receives an output signal of the frequency dividing circuit, generates a magnetic field according to the output signal, and outputs the second signal synchronized with the magnetic field. Automatic frequency control circuit.