JP2001203248A - Defect analysis method using emission microscope and its system, and manufacturing method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a defect analysis method and its system for analyzing defect, based on an emission image that is detected by an emission microscope corresponding to a circuit block in an LSI chip for a semiconductor device where LSI chips such as system LSIs are arranged. SOLUTION: Two processes are included: namely an emission calculation process for examining the arrangement state of emission points, based on an emission image that is detected by the emission microscope for a semiconductor device where LSI chips are arranged, classifying the state into a plurality of emission types, based on the arrangement state of the examined emission points, and calculating the number of occurrence for each classified emission type for each of the LSI chips and further for different types of circuit blocks in the LSI chips; and an analysis process for analyzing defect based on the number of occurrence for each emission type for each circuit block for each LSI chip that has been calculated in the emission calculation process.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention performs a failure analysis on a semiconductor device in which a plurality of different types of circuit blocks, such as a system LSI, are arranged, based on a light emission image picked up by an emission microscope. The present invention relates to a failure analysis method using an emission microscope, a system thereof, and a method of manufacturing a semiconductor device.

[0002]

2. Description of the Related Art Semiconductor device manufacturing includes a wafer processing step of forming a semiconductor device on a so-called silicon substrate,
It comprises an assembling step of separating the semiconductor device from the substrate and performing packaging and the like. Of these, the wafer processing process comprises major processes such as element isolation, element formation, and wiring. These major steps consist of repetition of processes such as film formation, exposure, and etching. Before and after each processing, steps such as cleaning and quality inspection are added as necessary. For this reason, the number of processing steps in the wafer processing step is several hundreds. On the other hand, the processing size of these steps is often 1 micrometer or less, and the processing accuracy is about one-tenth of the processing size, and extremely fine and high-precision processing is performed. Therefore, if any trouble occurs in the processing apparatus, the required processing accuracy cannot be maintained, resulting in a failure. Since hundreds of processes are performed in the semiconductor device manufacturing process as described above, when a defect occurs, it takes a lot of time to find out the process that caused the defect. Since defective products continue to be generated until the cause of the failure is identified and the countermeasures are completed, it is extremely important to shorten the analysis time of the failure cause, and a means to shorten the failure analysis time has been incorporated. There is a demand for establishing a semiconductor manufacturing method.

On the other hand, for memory products such as DRAMs, a so-called fail bit analysis method as disclosed in Japanese Patent Application Laid-Open No. 61-243378 (prior art 1) is known. On the other hand, “Failure analysis technology using emission microscope”, NEC Technical Report Vol. 46 No. 11 /
1993 P40 to P45 (Prior Art 2) describe that a light-emitting portion indicated by an emission microscope is used as a clue to identify a broken portion of an LSI composed of a MOS transistor.

Japanese Patent Application Laid-Open No. 10-4128 (prior art 3) includes, for an image obtained by scanning with an emission microscope, a two-dimensional position and a light emission intensity associated with the two-dimensional position. The light emission information is divided into predetermined unit scan areas and stored in an image memory having a three-dimensional memory space, the stored light emission information is searched, and the unit scan area is stored based on the searched light emission information. A failure analysis of the semiconductor device is performed every time, or a light emission status of each of the plurality of semiconductor devices is collectively displayed on a predetermined wafer based on the light emission information to generate a light emission wafer map. A failure analysis method for a semiconductor device using an emission microscope that performs failure analysis of a plurality of semiconductor devices based on the failure analysis is described.

[0005]

However, the fail bit analysis method described in the prior art 1 can be applied only to the built-in memory unit in a system LSI other than a memory product, and the other logic unit is used. Etc. cannot be applied. Moreover, the above-mentioned prior art 2
And 3 correspond to a circuit block inside the LSI for a semiconductor device in which a plurality of different types of circuit blocks such as a logic unit, a memory unit, and a pad unit such as a system LSI are mixed. No attempt was made to perform a failure analysis based on the light emission modes classified according to the above.

[0006] An object of the present invention is to solve the above problems.
For a semiconductor device (semiconductor substrate) on which an LSI chip having a plurality of different types of circuit blocks, such as a system LSI, is arranged, a light emission image detected by an emission microscope is associated with a circuit block inside the LSI chip. It is an object of the present invention to provide a failure analysis method using an emission microscope and a system for performing the failure analysis based on the failure analysis. Another object of the present invention is to associate a semiconductor device (semiconductor substrate) on which an LSI chip having a plurality of different types of circuit blocks, such as a system LSI, is arranged, with a circuit block inside the LSI chip. To provide a method of manufacturing a semiconductor device capable of performing a failure analysis based on a light emission image detected by an emission microscope and capable of manufacturing with a high yield.

[0007]

In order to achieve the above object, the present invention examines the arrangement of light emitting points on a semiconductor device on which LSI chips are arranged based on a light emission image detected by an emission microscope. , A plurality of emission types (isolated, dense, linear,
And a cycle or a dashed light emission mode), and a light emission calculation step of calculating the number of occurrences of each of the classified light emission types for each of the LSI chips and / or for each of different types of circuit blocks in the LSI chip. A failure analysis using an emission microscope, wherein the failure analysis is performed on the basis of the number of occurrences of each light emission type for each LSI chip and / or each circuit block calculated in the light emission calculation process. Is the way.

The present invention also provides a preparatory process for preparing a database in which a correspondence relationship between each light emission type for each circuit block and an estimated cause of failure is registered in advance for each LSI chip. The arrangement state of the light emitting points is examined based on the emission image detected by the emission microscope with respect to the semiconductor device, and the light emitting points are classified into a plurality of light emission types based on the examined arrangement state of the light emitting points. A light emission calculation step of calculating the number of occurrences for each light emission type for each of the different types of circuit blocks for each of the LSI chips, and an occurrence count for each light emission type of each circuit block for each of the LSI chips calculated in the light emission calculation step An analysis step of searching and outputting a cause of failure corresponding to the database prepared in the preparation step according to the number and outputting the same. A failure analysis method had.

Further, according to the present invention, an arrangement state of light emitting points is examined based on a light emission image detected by an emission microscope for a semiconductor device on which LSI chips are arranged, and based on the examined arrangement state of the light emitting points. And multiple emission types (isolated, dense, linear, and periodic or dashed emission modes)
And a light emission display process of displaying light emission map information indicating the light emission points of each of the light emission types, and performing a failure analysis based on the light emission map information of each type displayed in the light emission display process. And a failure analysis method using an emission microscope.

Further, the present invention is characterized in that in the failure analysis method using the emission microscope, light emission map information for each light emission type in a light emission display process is displayed in LSI chip units. In addition, the present invention relates to LS
Based on the emission image detected by the emission microscope for the semiconductor device on which the I chips are arranged, the arrangement state of the light emitting points is checked for each of the different types of circuit blocks in the LSI chip. A light-emitting display step of classifying the light-emitting points into a plurality of light-emitting types based on the arrangement state of the light-emitting points and displaying light-emitting map information indicating a light-emitting point of each light-emitting type for each of the classified circuit blocks; A failure analysis based on the emission map information for each emission type for each circuit block thus performed, and a failure analysis method using an emission microscope.

Further, the present invention provides an arrangement of light emitting points or a light emitting point for each of different types of circuit blocks in an LSI chip based on a light emitting image detected by an emission microscope for a semiconductor device on which LSI chips are arranged. The light emitting points are classified into a plurality of light emission types based on the checked light emitting point arrangement state or the light emitting point arrangement state for each circuit block, and the light emitting point arrangement state for each of the classified light emission types is determined. Or a light emission display step of displaying light emission map information indicating an arrangement state of light emission points for each light emission type for each circuit block,
A foreign matter display step of inspecting foreign matter including appearance defects on a semiconductor device on which an LSI chip manufactured up to a desired manufacturing process step is arranged, and displaying foreign matter map information indicating an occurrence state of the inspected foreign matter; A failure analysis method using an emission microscope, comprising: an analysis step of performing a failure analysis by comparing the emission map information displayed in the emission display step with the foreign matter map information displayed in the foreign matter display step. It is.

Further, the present invention examines an arrangement state of light emitting points on a semiconductor device on which LSI chips are arranged based on an emission image detected by an emission microscope, and based on the examined arrangement state of the light emitting points. A light emission calculation step of calculating the number of occurrences of each of the classified light emission types for each LSI chip and / or for a different type of circuit block in the LSI chip; Inspection of foreign matter including appearance defects on the semiconductor device on which the LSI chips manufactured up to and including the LSI chip are arranged, and calculation of the number of occurrences of the inspected foreign matter for each of the LSI chips, and calculation in the emission calculation step The number of occurrences of each light emission type for each LSI chip and the number of occurrences of foreign matter for each LSI chip calculated in the foreign matter calculation process are output in association with each other. A failure analysis method using the emission microscope characterized by having an analysis process of performing failure analysis on the basis of the association was. Further, the present invention is characterized in that a semiconductor device is manufactured by performing a failure analysis using the failure analysis method using the emission microscope and taking measures against a failure cause estimated in a production line based on the failure analysis result. Of the semiconductor device.

Further, according to the present invention, an arrangement state of light emitting points is examined on a semiconductor device on which LSI chips are arranged based on an emission image detected by an emission microscope, and based on the examined arrangement state of the light emitting points. A light emission calculation device that classifies the light emission types into a plurality of light emission types, and calculates the number of occurrences for each of the classified light emission types for each LSI chip and / or for each type of circuit block in the LSI chip. A failure analysis system using an emission microscope, comprising: an output device that outputs the calculated number of occurrences for each light emission type for each LSI chip. In addition, the present invention provides a database in which a correspondence relationship between each light emission type of each circuit block for each LSI chip and a presumed cause of failure is registered in advance, and a semiconductor device in which the LSI chips are arranged is configured to emit light. The arrangement state of the light emitting points is checked based on the light emission image detected by the microscope, and the light emitting points are classified into a plurality of light emission types based on the checked arrangement state of the light emission points. For each of the LSI chips, a light emission calculating device that calculates for each of different types of circuit blocks, and for each of the LSI chips calculated by the light emitting calculating device, from the database according to the number of occurrences of each light emitting type for each circuit block. A failure analysis system using an emission microscope, comprising: an output device that searches for and outputs a corresponding failure cause.

Further, the present invention provides an arrangement of light emitting points or an arrangement of light emitting points for each LSI chip or an LSI chip based on a light emission image detected by an emission microscope for a semiconductor device on which LSI chips are arranged. The arrangement state of the light emitting points is checked for each of the different types of circuit blocks, and a plurality of light emitting points are arranged based on the checked arrangement state of the light emitting points, the arrangement state of the light emitting points for each LSI chip, or the arrangement state of the light emitting points for each circuit block. And the light emission map information indicating the light emission points for each light emission type, the light emission points for each light emission type for each LSI chip, or the light emission points for each light emission type for each circuit block is created. A light emitting map information generating device; and a display device for displaying the light emitting map information for each type generated by the light emitting map information generating device. Cushion is failure analysis system using a microscope. Further, the invention is characterized in that a light emission image is detected from a substrate side of the semiconductor device.

As described above, according to the above configuration,
A semiconductor device in which LSIs composed of various circuit blocks, such as a system LSI, are arranged by automatically classifying the arrangement state of light emitting points in LSI chip units or circuit block units in LSI chips based on a basic pattern. Can be subjected to failure analysis.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a failure analysis method using an emission microscope, a system thereof, and a method of manufacturing a semiconductor device according to the present invention will be described with reference to the drawings. First, an embodiment of a light emission mode classification and analysis system using an emission microscope according to the present invention will be described with reference to FIG. The measurement system includes an emission microscope including a tester 1, a stage 2 on which a wafer to be measured (semiconductor device) 3 is mounted, a prober 4, and a camera 5 for taking a light emission image. As described above, the emission microscope is described in “Failure Analysis Technology Using Emission Microscope” NEC Technical Report Vol. 46 No. 11/1993 P40-P4
As described in 5), in the semiconductor device 3,
It detects weak light emitted from a defective location or a location where a load is applied due to the presence of a defect, and outputs the emitted location with high accuracy.

The data processing system comprises a data processing device 6, a data storage device 7, and a data output device 8. In the measurement system, the tester 1 applies a voltage and a signal to the wafer to be measured (semiconductor device) 3 via the probe 5. At that time, the measurement is usually performed in chip units. When a plurality of chips are measured at the same time, a procedure for extracting information for each chip from a measurement result in a later data processing system is required. Here, in order to simplify the description, a case where measurement is performed for each chip 20 will be described. A voltage and a signal are applied to each chip 20, and a light emission image at that time is captured by the camera 5. The data processing device 6 collects the light emission image and the chip position obtained from the stage 2. In addition, the data processing device 6
The light emission image picked up by the camera 5 and the chip position obtained from the stage 2 are stored in the tester 1 and the network 10.
May be collected via Naturally, the data processing device 6
The voltage and the signal applied from the tester 1 to the wafer 3 to be measured via the prober 5 can also be obtained. By the way, the chip position is the coordinates (Xn, Yn) of the chip to be measured based on a preset coordinate system in the wafer to be measured 3 as shown in FIG. Here, Xn and Yn are integers. Wx is the width of the chip 20 in the x direction, Wy
Indicates the width of the chip 20 in the y direction. The coordinates of the light emitting point in the chip 20 are indicated by (Xc, Yc).

When an emission image is obtained, the emission image is sent from the camera 5 to the data processing device 6, and the type, lot number, measurement conditions, measurement date and time, measurement device information, work User information (hereinafter, referred to as measurement information) is sent to the data processing device 6. Data processing device 6
Is stored in the data storage device (storage device) 7 in a format as shown in FIG. 3, for example. Here, the storage location 31 of the light emission image and the measurement information 32 are stored in pairs.

The measurement information 32 of the light emission image is composed of the kind of semiconductor device 3, lot number, measurement condition, measurement date and time, measurement device information, worker information and the like. As the luminescent image storage location 31, the number of measurement chips is repeated, and the chip positions 1 to n and the luminescent image storage locations I1 to In correspond to each other.

Next, an embodiment of the light emission mode classification analysis performed by the data processing device 6 will be described. By the way, in the light emission mode classification analysis performed by the data processing device 6 based on the light emission point information detected from the emission microscope, the place where light is emitted is not limited to a point but may be a widened area. However, in either case, it is simply called a light emitting point.

First, as shown in FIG. 4, the data processing device 6 obtains coordinates (Xc, Yc) of a light-emitting point from the light-emitting images stored in the light-emitting image storage locations I1 to In for each chip 1 to n. By comparing the obtained coordinates of the light emitting point with the design information on the chip, it is determined which area of the memory, logic, pad, etc. the light emitting point has occurred in the chip. The obtained area information is stored in the data storage device 7 together with the coordinates (Xc, Yc) of the light emitting point. That is, the data processing device 6 executes step S
At 41, each chip is stored in the luminescent image storage locations I1 to In.
To n are acquired, and then in step S
42n, for example, information (Wx,
The edge processing is performed based on Wy), and the peripheral portion is cut off. Next, in step S43, the data processing device 6 compares the luminescent image with the reference image composed of the background image having no luminescent point, for example, extracts a difference image, and sets a predetermined threshold value for the extracted difference image. The light emitting point which is a difference is extracted by multiplying and judging, and then, in step S44, the coordinates of the light emitting point which is the difference on the light emitting image are recognized. Next, in step S45, the data processing device 6 converts the coordinates of the light emitting point, which is a difference on the light emitting image, into the coordinates (Xc, Yc) on the real chip. In this way, the coordinates (Xc, Yc) of the light emitting point in the chip are obtained. Then, the data processing device 6 determines the coordinates (Xc, Yc) of the obtained light emitting point in the chip and the design information in the chip 20 (design information relating to the memory area, the logic area, and the pad area). Is determined by determining in which area the light emitting point emits light, and information on the area and the coordinates (X
c, Yc) can be obtained and stored in the data storage device 7.

Next, the classification of the light emitting points performed by the data processing device 6 will be described. That is, as a criterion for classifying the light emitting points in the present invention, attention is paid to the arrangement state of the light emitting points, and the arrangement state of the light emitting points is classified into isolated, dense, dashed, linear, and periodic as shown in FIG. Define. The term “isolated” refers to a single light emitting region having no other light emitting point in the vicinity. In some cases, it is not just a point, but rather broad. Although there are several possible causes of light emission in isolation, it is considered that in a semiconductor device such as a system LSI, gate destruction or oxide film leakage due to crystal defects occurs in isolation.

The term "dense" refers to a case where several light emitting points are gathered in the vicinity. Here, the neighborhood is designated by a parameter having a certain degree of arbitraryness.
What is necessary is just to decide within 1 mm radius from the center of a light emission point.
There are several reasons why the light emitting points are densely packed.
In semiconductor devices such as I, the cause may be that the leakage of the oxide film is spread over a certain range. The broken line shape means that the light emitting points are arranged linearly and intermittently. The period looks like an isolated point at first glance, but when viewed over the entire chip, they are arranged in a straight line at substantially equal intervals. These are cases in which a semiconductor device such as a system LSI has several similar circuits at the branch destination, and when there is an abnormality in wiring before the branch, several circuits at the branch destination are simultaneously operated. It is seen when light is emitted. Here, when the circuits at the branch destinations are arranged at substantially equal intervals, the light emission appears to be periodic, and otherwise, the light emission appears to be a broken line. Therefore, it is not necessary to distinguish between the broken-line light emission and the periodic light emission.

The term "linear" means that the light emitting points are arranged continuously in a straight line. This is observed in a semiconductor device such as a system LSI when the transistors malfunction, such as an abnormal input voltage to a specific transistor row. As described above, the light emitting modes according to the present invention are classified and defined according to the arrangement of light emitting points.

As described above, in the light emitting mode according to the present invention, the light emitting modes classified and defined according to the arrangement of the light emitting points are further changed as shown in FIG. Attention is paid to the memory section, the logic section, and the pad section) to finely classify and define. That is, in the case of a system LSI or the like, a memory area, a logic area, and a pad area exist in the chip 20, and coordinates (Xc, Y) at which a light emitting point is generated based on design information.
It is possible to know which area c) is. By the way, in this case, it is assumed that, even if the light emitting point exists, for example, over both the logic unit and the memory unit, they are not related to each other. As described above, the location (area) where light is emitted is determined by the fact that the manufacturing method and the circuit structure are different in the memory part and the logic part, for example, the manufacturing process is partially different or the wiring interval is different. This is because it differs for each block, that is, for each area where these circuit blocks exist. Therefore, when only a specific circuit block appears in a light emitting region, it can be determined that there is a problem in a manufacturing process (manufacturing process) or circuit structure unique to the circuit block.

Next, the classification of the light emitting points performed by the data processing device 6 based on the above-described definition will be described in more detail with reference to FIG. Note that this classification process is basically
It shall be performed for each chip. First, the data processing device 6
Captures the luminescence images stored in each of the chips 1 to n into the luminescence image storage locations I1 to In (step S71).
As in step S43, a difference image between the captured light-emitting image and a reference image composed of a background image having no light-emitting points prepared in advance is extracted by a difference image extracting circuit (not shown), and the extracted difference image is extracted. An image is determined by a determination circuit (not shown) with a predetermined threshold, and a light emitting point is extracted (step S72). Next, a shape parameter (for example, the aspect ratio of each light emitting point) of each light emitting point is calculated by a shape parameter calculating circuit (not shown) in the data processing device 6 (step S73), and then the calculated shape is calculated. The coordinates of the center of gravity of each light emitting point are calculated based on the parameters (step S
74).

Next, the data processing device 6 determines whether or not there is a light emitting point to be processed for each chip based on the barycentric coordinates of each light emitting point calculated for each chip (step S7).
5). If there is no light emitting point to be processed for each chip, the process is terminated. If there is a light-emitting point to be processed, the data processing device 6 performs the following processing. First, the data processing device 6 selects one of the light-emitting points to be processed and determines whether or not the light-emitting point is arranged in a straight line with the other light-emitting points (step S76). If they are arranged in a straight line, it is determined whether or not they are approximately at equal intervals (step S77). If the intervals are equal, it is determined that the cycle is a cycle, a group identifier having a common cycle is assigned to the light emitting point group of the corresponding cycle, and stored in the data storage device 7 together with the coordinate sequence of the light emitting point group (step S7).
8). If the data processing device 6 is not at equal intervals, the data processing device 6 determines that the data is in a dashed shape, assigns a common dashed group identifier to the corresponding dashed light emitting point group, and assigns the data storage device 7 with a coordinate sequence of the luminescent point group. (Step S7)
9).

Next, the case where it is determined in step S76 that the shape is not linear will be described. First, the data processing device 6 determines whether there is another light emitting point near the specific light emitting point (density) (step S80). If another light-emitting point exists, it is determined that the light-emitting point group is crowded, a dense group identifier is assigned to the light-emitting point group, and stored in the data storage device 7 together with the coordinate sequence of the light-emitting point group (step S81). If it is determined that there is no light emitting point in the vicinity, it is determined whether or not it is linear (step S82). If it is linear, a linear group identifier is assigned to the light emitting point alone and stored in the data storage device 7 together with the coordinate sequence of the light emitting point group (step S).
83). Otherwise, it is recognized as isolated, and the isolated point identifier is assigned to the light emitting point alone and stored in the data storage device 7 together with the coordinate sequence of the light emitting point group (step S8).
4). Then, when the data processing device 6 is classified into any of the modes, the light emitting point to which the group identifier is assigned is excluded from the light emitting points to be processed (step S85), and one light emitting point is selected again, and The processing from S75 is repeated.

As described above, the data processing device 6
Classifies the light-emitting points into four light-emitting modes of period and broken line, dense, linear, and isolated according to the definition shown in FIG. 5 described above. The data is stored in the data storage device 7. In addition,
It is convenient and convenient to assign a series of integer values to the group identifier. As described above, if the semiconductor device 3 such as a system LSI is classified as isolated, it can be analyzed that gate destruction or oxide film leak due to a crystal defect has occurred in isolation. It can be analyzed that the leakage of the oxide film spreads in a certain range, etc., and if it is classified into a period and a broken line, it is likely that there are some similar circuits at the branch destination, and the wiring is connected before the branch. It can be analyzed that there is an abnormality, and if it is classified into a linear shape, it can be analyzed that those transistors are malfunctioning, such as an abnormality in the input voltage to a specific transistor row.

Next, individual recognition algorithms will be described. First, as a method of recognizing the linearity in step S76, a method called Hough transform based on the barycenter coordinates of each light emitting point calculated in step S74 is known. This is already widely known, and the explanation is omitted (Reference: Image recognition theory Makoto Nagao, Corona Publishing Co., Ltd., pp. 72-74). The following algorithm is conceivable for the recognition of the uniformity in step S77. In most cases, the light emitting points arranged in a straight line
Parallel to the Y axis. Here, a light emitting point sequence in the X direction will be described as an example. The same applies to the Y direction.

The coordinates of the barycenter of X of the target n light emitting point sequences calculated in step S74, x (1), x
(2), x (3) ... d (i) = d (i) = x
(I + 1) -x (i) is defined. Where x (1) <x
(2) <x (3) <... <x (n). Then, d
Calculate the standard deviation SG for (i). And SG
/ | X (n) -x (1) |, and if this value is substantially equal to or less than a constant value, it is determined that the intervals are equal. This constant value may be determined to be, for example, 0.001. Next, step S
The determination of the density of 80 will be described. Here, if there is a barycenter coordinate of another light-emitting point within a certain radius from the barycenter coordinate of the focused light-emitting point calculated in step S74,
They are determined to be dense. This radius may be set to, for example, 1 mm.

Next, the data processing device 6 further classifies the luminous points into four types: periodic, broken line, dense, linear, and isolated according to the definition shown in FIG.
A description will be given of how the areas such as the logic section and the pad section are finely classified and stored in the data storage device 7. That is, the area data of the memory unit, the logic unit, and the pad unit in the chip 20 of the semiconductor device 3 is input as design information from the CAD system (not shown) to the tester 1 via the network 10, for example. For example, it is stored in the data storage device 7. Therefore, as described above, in step S46 shown in FIG. 4, by comparing the converted coordinates of the light emitting point on the real chip with the area data stored in the data storage device 7, for example, You can know what happened,
The result can be registered in the data storage device 7.

In step S75 shown in FIG. 7, the coordinates of the center of gravity of each light emitting point calculated in step S74 are compared with, for example, the above-mentioned area data in each chip stored in the data storage device 7, thereby obtaining each light emitting point. In which region is present. Then, the determinations in steps S76 to S84 may be performed for each of the above regions. Here, recognition of linearity, equal spacing, and denseness is not performed over different definition areas. As described above, the region of the light-emitting circuit block can be specified, so that it is possible to determine that there is a problem in the manufacturing process (manufacturing process) or circuit structure unique to the circuit block.

Next, the output of the measurement information, the light emission image, and the light emission mode classification result stored in the data storage device 7 will be described. That is, as shown in FIG. 3, the measurement information 32 such as the type name, lot number, and wafer number of the wafer to be measured, the light emission image 31 corresponding to the chip position, and the light emission mode classification result are sent to the data processing device 6. The data is input and stored in the data storage device 7. Therefore, if you want to know the data processing result of the measured wafer or chip,
By inputting the type name, lot number, wafer number, and the like of the wafer to be measured to the data processing device 6 using an input device 9 including a keyboard, a mouse, a recording medium, and the like, an output device 8 shown in FIGS. 10, and can be output in a format as shown in FIGS.

First, a first embodiment of the output of the light emission mode classification result will be described with reference to FIG. The format according to the first embodiment includes a column 51 indicating a product name, a lot number, and a wafer number, and a column 5 indicating a measurement date, a measurer, a measurement device, and the like.
2, a column 53 indicating measurement conditions, a column 54 indicating a classification name, a column 55 indicating the number of light emission modes on a wafer for each classification, a column 56 indicating a position of each chip in the wafer, and a column 56 for each light emission mode of each chip A column 57 indicating the number of occurrences is provided. That is, the classification name (period and broken line, dense, linear,
The number of occurrences 55 over the wafer to be measured and the number of occurrences 57 for each chip for the four isolated light emission modes) 54 can be displayed and output. Therefore, the operator needs to read the whole wafer to be measured and chip by chip.
It is possible to grasp the number of light emission modes generated for each area.

Specific examples of the output device 8 include a printer, a CRT, and the like.
Since the members 6 and 57 become longer horizontally, a so-called scroll function is provided for easier operation. The format shown in FIG. 8 is merely an example, and some information may be added and displayed, or may be deleted and displayed simply. Although the data processing result is obtained by inputting the type name, lot number, wafer number, etc. of the wafer to be measured into the data processing device 6, it is also possible to automatically output the data processing result after the measurement. Good. Further, as described above, the association between the classification name 61 indicated by the light emission mode for each area and the cause of failure 62 can be stored in the data storage device 7 in advance, so that the output shown in FIG. By outputting the cause of failure 61 corresponding to the class name 61 having a particularly large number of occurrences obtained from the format in the output device 8 as shown in FIG. 9, the cause of failure 61 can be easily grasped. This can be useful for cause analysis.

Next, a second embodiment of the output of the light emission mode classification result will be described with reference to FIG. The second embodiment is a display in which a so-called map display 71 and a light emission mode classification 72 including measurement information 73 are combined. As described above, for each light emitting point, the position (Xn, Yn) of the corresponding chip and the coordinates (Xc, Yc) within the chip are known. Therefore, if the data processing device 6 uses the size (Wx, Wy) of the chip stored in the data storage device 7, the coordinates (Xw, Yw) in the wafer are calculated based on the following expression (Equation 1). It can be easily calculated. The chip size (Wx, Wy) is stored and managed in the data storage device 7 for each product type.

Xw = Xn · Wx + Xc Yw = Yn · Wy + Yc (Equation 1) Then, the data processing device 6 strikes the coordinates (Xw, Yw) calculated for each light emitting point, thereby obtaining the light emitting point on the wafer. A light emission map 71 showing the distribution is created, and C
The information can be displayed on the RT 8 as shown in FIG. FIG. 10 shows an example of the display. An emission map 71 showing the distribution of emission points on the wafer, an emission mode classification result 72 on the wafer, and a measurement condition 73 on the wafer are arranged on an output screen or the like so that they can be referred to each other. When outputting to the CRT 8, if the light emission map 71, the light emission mode classification result 72, and the measurement condition 73 are displayed using separate windows, the information can be displayed / non-displayed, the display position can be moved, and the like as necessary. Therefore, operability is good.

The data stored in the data storage device 7 shown in FIG.
Since the correspondence between the chip and the emission image can be easily obtained from the database shown in FIG. 11, by designating the desired chip, the data processing device 6 converts the emission image 83 of the chip 81 into the CRT 8 as shown in FIG. Can be displayed. Also, at this time, if the light emission mode classification result 82 of only the chip concerned is displayed, only the information of the chip of interest can be narrowed down, so that the operability is good. The data processing device 6 has a mode extracting function by designating a specific light emission mode on the screen shown in FIG. And display it on the CRT 8. As a result, for example, as shown in FIG. 12A, the distribution of isolated point defects in the logic portion on the wafer is almost uniformly distributed on the wafer, whereas the distribution of isolated point defects in the memory portion on the wafer is reduced. If the distribution is concentrated in the peripheral portion of the wafer as shown in FIG. 12B, it is possible to judge that the causes of these defects in the manufacturing process are different, and the manufacturing line manager can separately determine It is possible to formulate measures. Also,
When the light emitting points are concentrated on a specific area of the wafer, it can be determined that the wafer processing has been uneven in the plane. For example, as shown in FIG. 12B, if there are many light-emitting points around the wafer, the data processing device 6 focuses on quality control items such as film thickness and foreign matter density around the wafer, and focuses on the wafer center among these items. It is possible to check an item having a difference from the set and output the checked item as a candidate for the cause of the defect. In addition, to check the items that are different from the wafer center,
The quality control items may be displayed on the CRT 8. The film thickness at the peripheral portion of the wafer may be measured by a film thickness measuring device (not shown), input to the data processing device 6 via the network 10, and stored in the data storage device 7, for example. Further, the density of foreign matter in the peripheral portion of the wafer is inspected by a foreign matter inspection device (not shown).
0 to the data processing device 6 and store it in the data storage device 7. As described above, acquiring information on the area of a defect, such as where the light emitting points are concentrated on the wafer, is effective in taking measures against the defect.

Further, the data processing device 6 checks the number of chips having the respective light emitting points for each of the classified light emitting modes, and outputs the result by using the output device 8, so that the respective light emitting modes are reduced in the yield. You can know the effect. At this time, the data processing device 6
The yield may be calculated for each light emission mode, and the calculation result may be output using the output device 8. As described above, outputting the number of chips having light-emitting points and the yield thereof for each light-emitting mode can provide a guideline for prioritizing measures. Normally, in the light emitting mode, a countermeasure is implemented with priority given to a chip having a larger number of chips having light emitting points (a chip having a lower yield). Further, by the light emission mode extraction function, the data processing device 6
For example, a difference image is extracted by comparing the occurrence distribution of a specific light emission mode obtained by imaging the wafer 3 to be measured before and after the countermeasure with the camera 5, and the comparison result is expressed by, for example, a CR.
By displaying the output at T8, the effectiveness of the countermeasure can be confirmed. Note that the occurrence distribution relating to a specific light emission mode obtained from the measured wafer 3 before and after the countermeasure may be output to the CRT 8 and displayed as it is.

Next, the emission mode classification and analysis method described above and a semiconductor manufacturing method using the system will be described in more detail. When a so-called wafer processing step of a semiconductor wafer is completed, an electrical characteristic test usually called a probe test is performed. Here, a wafer with a low yield is extracted by evaluating the yield in the wafer processing step. Next, the extracted wafer having a low yield is subjected to the above-described emission mode classification and analysis system. As described above, by outputting at least the number of occurrences (or occurrence frequency map data for each light emission mode) in the classification name (light emission mode classified for each area) shown in FIG. Can be determined. At this time, as shown in FIG.
By displaying the cause of failure 62 corresponding to No. 1, it is possible to easily determine the approximate cause of failure.

Further, the data processing device 6 is connected to a visual inspection device (not shown) including a production line management device (not shown) for managing the entire production line and a foreign matter inspection device via, for example, a network 10. A manufacturing process condition or a circuit structure condition is searched using a wafer number, a product name, and a lot number based on the measurement information as a key, and the manufacturing process condition or the circuit structure condition of a circuit block having a light emitting point and a light emitting point do not exist. By comparing the manufacturing process conditions and the circuit structure conditions of the circuit blocks with each other, the differences in the manufacturing process conditions between the circuit blocks and the differences in the circuit structure conditions are output and displayed on a CRT 8, for example, to narrow down the cause of the failure. it can. At this time, it is not always necessary to display the difference, and both may be displayed so that the production line manager can recognize the difference. The circuit structure condition may be an actually measured wiring width, a wiring interval, an insulating film thickness, or the like. Further, it may be measured by processing and observing a cross section after it is almost completed.

Specifically, for example, it is assumed that a wavy light emission mode has frequently occurred in the pad portion. Since the DC current is suspected to be abnormal, the data processing device 6 checks the circuit structure conditions and the manufacturing process conditions related thereto from the visual inspection device including the manufacturing line management device and the foreign material inspection device via the network 10, for example. Obtain and convert those data to C
The production line manager checks it by displaying it on the RT 8 or the like to determine the cause of the defect. For example, there is no place where the space between the circuit patterns has no margin, or there is no foreign matter on the wiring. Then, the production line manager takes countermeasures based on the determined cause of the defect which is the check result. If it is caused by the circuit pattern, correct the mask. If it is caused by foreign matter, a countermeasure such as sweeping is performed on the processing apparatus that has processed the wiring layer. The light emission mode classification and analysis system is applied again to the lot that has been subjected to such measures. Here, if the frequency of appearance of the dashed light-emitting mode in the vicinity of the pad decreases, it can be confirmed that the countermeasure was effective. If the appearance frequency of the light-emitting mode has not decreased, it means that the countermeasure was not effective, and it is necessary to investigate the cause of the failure again.

By classifying the light emitting points into the light emitting modes in this manner, the cause of the failure can be analyzed for each light emitting mode. This makes the cause analysis more efficient. Further, by comparing the appearance frequencies before and after the search for each light emission mode classification, the effectiveness of the countermeasure can be easily confirmed. Here, an embodiment in which a wafer having a low yield is applied to the emission mode classification and analysis system has been described, but there are other methods of sampling the wafer. For example, there is a method of measuring wafers always at the same position in a lot, measuring the total number, or measuring a certain number at random.

Next, another embodiment of the analysis method using the above-described emission mode classification result will be described with reference to FIG. That is, in this embodiment, a foreign matter inspection result inspected by a foreign matter inspection device in a semiconductor manufacturing process (semiconductor manufacturing line) and a visual inspection device (optical visual inspection device or SE
This is a method of collating the appearance inspection result inspected by the external appearance inspection device (including the M appearance inspection device) with the emission mode classification result. In particular,
Since the defective portion does not always emit light, a special device is required for comparing the foreign material or the appearance defect (hereinafter simply referred to as foreign material) with the light emitting portion. As one of them, the data processing device 6 divides the inside of the chip into, for example, a memory section, a logic section, and a pad section, and analyzes the correlation between the number of foreign substances attached to each area and the light emission mode of the corresponding area. The purpose is to output a figure (graph) to the CRT 8 and display it. By the way, the number of foreign substances adhering to each area in a certain manufacturing process is obtained by the data processing device 6 from a foreign material inspection device (not shown) or a visual inspection device (not shown) via, for example, the network 10. Alternatively, the data processing device 6 may be configured to use area data as design information based on a foreign substance inspection result indicated by coordinate data of a foreign substance obtained from the foreign substance inspection apparatus or the appearance inspection apparatus via the network 10, for example. It can be calculated by comparing with. Each correlation diagram shows the number of foreign substances on the horizontal axis and the frequency of occurrence of the mode focusing on the vertical axis. The data processing device 6 arranges the correlation diagram in the vertical direction for each light emission mode with respect to the region defined in the preceding chip in the horizontal direction, and outputs the correlation diagram to the CRT 8 so that the user can look down in a matrix. By using such an output, the causal relationship between the two can be grasped for each macro circuit block. Therefore, it is possible to grasp whether the foreign matter generated in the process causes a defect and what kind of the defect is.

Further, if the data processing device 6 acquires the foreign substance inspection result for each manufacturing process from the foreign substance inspection apparatus or the appearance inspection apparatus via, for example, the network 10, the above analysis can be repeated for each manufacturing process step. Becomes
As a result, the data processing device 6 outputs the analysis result repeated for each manufacturing process step to the CRT 8 or the like and displays it, thereby causing the light emission mode of interest to be determined in which part of which manufacturing process step It is possible to determine whether the foreign matter has occurred. As a result, it is possible to implement a specific defect countermeasure such as giving priority to a countermeasure against foreign matter in the process.

Next, another embodiment of the light emission mode classification and analysis system according to the present invention will be described. That is, in the present embodiment, when a light emission image is acquired by the camera 5, the light emission generated in the lower layer of the measured wafer 3 is observed from the substrate side on the rear surface in order to easily detect the light emission. The reason for observing the emission image from the substrate side on the back side is that the light emitted in the lower layer of the wafer 3 to be measured is blocked by the multilayer wiring layer formed thereon, This is because it becomes difficult to observe the emission image from the front side. Furthermore, if the substrate on the back side is processed and thinned,
The emission image emitted in the lower layer can be easily observed from the back side. However, when the light emission image is observed from the back side of the wafer 3 to be measured, the light emission image is observed in a mirror image inverted state. Therefore, when creating the emission map, the data processing device 6 needs to mirror-invert the coordinate data of the emission point (reverse one of the x direction and the y direction, as shown in FIG. 14). . By doing so, it is possible to collate the distribution of foreign substances attached to the upper surface of the wafer to be measured during the manufacturing process with the distribution of light emitting points measured from the rear surface side. Conversely, even if the coordinate data in the foreign matter distribution is mirror-inverted, it is possible to match the distribution of the light emitting points. However, when a jig or an arm of the manufacturing apparatus is rubbed and foreign matter is generated on the wafer, the position where the foreign matter is attached is related to the arrangement of the jig or the like of the manufacturing apparatus. In such a case, if the coordinate data of the foreign matter is mirror-inverted, it becomes difficult to grasp the correspondence between the position where the foreign matter is attached and the layout of the jigs and arms in the manufacturing apparatus.

Next, a method of performing the emission mode classification in more detail will be described. The method described above is based on the shape of the light emitting point and its position information. Here, a classification scale based on optical information of the light emitting point is further added. The optical information is a light emission intensity or a light emission spectrum detected by a detection optical system such as the camera 5. The luminous intensity includes a peak luminous intensity detected by a pixel at each luminous point, a total luminous intensity which is a sum of luminous intensity of each pixel, and the like. It is also possible to characterize the emission spectrum of each emission point by a peak position, its half-value width, and the like, and refine the classification based on these characteristics. For example, when current leakage is observed at the gate of a transistor in an LSI chip, its emission spectrum becomes a continuous spectrum with a wide width, and there is an abnormality in wiring or the like, so-called intermediate state in which the gate does not clearly drop on or off. If it is in a potential state, the spectrum has a relatively small half-value width, and the above classification can be refined, that is, finely classified.

[0049]

According to the present invention, an LSI composed of various circuit blocks, such as a system LSI,
For semiconductor devices on which chips are arranged, the light emission mode is automatically classified for each LSI chip and / or for each circuit block based on the arrangement state of the light emitting points, so that failure analysis is standardized for various circuit blocks. As a result, the cause of the failure can be estimated, and the effect of the countermeasure can be easily confirmed. Further, according to the present invention, for a semiconductor device in which LSI chips composed of various circuit blocks are arranged, such as a system LSI, a cause analysis of a failure and a countermeasure against the failure are performed for each light emitting mode and for each light emitting mode.
By performing this for each SI chip and / or for each circuit block, it is possible to quickly improve the yield. Also,
By using a graphical user interface for output, work efficiency can be improved.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram showing one embodiment of a light emission mode classification and analysis system using an emission microscope according to the present invention.

FIG. 2 is a diagram showing a coordinate system set for a wafer to be measured.

FIG. 3 is a diagram showing a data management format managed in the data processing device.

FIG. 4 is a diagram showing a coordinate calculation flow of a light emitting point executed in the data processing device.

FIG. 5 is a diagram showing definitions of light emission modes classified based on an arrangement state of light emission points according to the present invention.

FIG. 6 is a diagram showing a definition for each circuit block of a light emission mode classified based on an arrangement state of light emission points according to the present invention.

FIG. 7 is a diagram showing a processing flow for classifying a light emission mode using the light emission mode classification and analysis system according to the present invention.

FIG. 8 is a diagram showing an output example of a light emission mode classification result according to the present invention.

FIG. 9 is a diagram showing a database in which a light emission mode classification for each circuit block and a cause of failure stored in a data storage device are associated with each other.

FIG. 10 is a view showing a screen on which a light emitting wafer map and a light emitting mode classification result according to the present invention are simultaneously displayed.

FIG. 11 is a view showing a screen on which a light emitting chip map and a light emitting mode classification result according to the present invention are simultaneously displayed.

FIG. 12 is a diagram showing an embodiment of an extraction mode map according to the present invention.

FIG. 13 is a correlation diagram showing the correlation between the number of foreign substances and the light emission frequency according to the present invention.

FIG. 14 is a diagram for describing mirror image inversion when observing the back surface from the substrate side of the wafer to be measured according to the present invention.

[Explanation of symbols] 1 ... tester, 2 ... stage, 3 ... wafer to be measured, 4 ... prober, 5 ... camera, 6 ... data processing device, 7 ... data storage device (storage device), 8 ... output device (display device) ), 9: input device, 10: network, 2
0 ... LSI chip, 31 ... Storage location of light emission image, 32 ...
Measurement information, 61: Classification name column, 62: Failure cause list, 71
... Emission wafer map, 72 ... Emission mode classification result, 73
... Measurement information, 81: Light emitting chip map, 82: Light emitting mode classification result.

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Toshiyuki Majima 5-20-1, Kamizuhoncho, Kodaira-shi, Tokyo F-term within Hitachi Semiconductor Co., Ltd. (Reference) 2G011 AA01 AE03 2G032 AA00 AB20 AD01 AD08 AF08 4M106 AA01 BA01 CA16 CA38 CA42 DA15 DB04 DB18 DJ18 DJ20 DJ21 DJ26 9A001 BB05 JJ48 KK16 KK31 LL08

Claims (19)

[Claims] An arrangement state of light emitting points is examined based on a light emission image detected by an emission microscope with respect to a semiconductor device on which an LSI chip is arranged, and a plurality of light emission points are determined based on the examined arrangement state of the light emitting points. A light emission calculation step of calculating the number of occurrences of each light emission type for each of the LSI chips, based on the number of occurrences of each light emission type of each LSI chip calculated in the light emission calculation step. A failure analysis method using an emission microscope. 2. An arrangement state of light emitting points on a semiconductor device on which LSI chips are arranged is detected based on a light emission image detected by an emission microscope, and a plurality of light emitting points are determined based on the arrangement state of the checked light emitting points. A light emission calculation step of calculating the number of occurrences of each of the classified light emission types for each type of circuit block in the LSI chip; and a circuit block in the LSI chip calculated in the light emission calculation step. A failure analysis method for performing failure analysis based on the number of occurrences of each light emission type for each emission type. 3. An arrangement state of light emitting points of a semiconductor device on which LSI chips are arranged is detected based on a light emission image detected by an emission microscope, and a plurality of light emitting points are determined based on the arrangement state of the checked light emitting points. A light emission calculation step of calculating the number of occurrences for each of the light emission types classified for each of the LSI chips, and further for each of the different types of circuit blocks in the LSI chip; A failure analysis method for performing failure analysis based on the number of occurrences of each light emission type for each circuit block for each LSI chip. 4. A preparatory process for preparing a database in which a correspondence relationship between each light emission type for each circuit block for each LSI chip and its estimated cause of failure is registered in advance, and a semiconductor device in which the LSI chips are arranged. The emission state of the light emitting points is examined based on the emission image detected by the emission microscope, and the light emission points are classified into a plurality of light emission types based on the checked arrangement state of the light emission points. A light emission calculating step of calculating the number of occurrences of each type of circuit block for each of the LSI chips, and according to the number of occurrences of each light emission type of each circuit block for each of the LSI chips calculated in the light emission calculation step A failure analysis using an emission microscope, comprising: an analysis step of searching and outputting a cause of failure corresponding to the database from the database prepared in the preparation step. Law. 5. An arrangement state of light emitting points of a semiconductor device on which an LSI chip is arranged is detected based on a light emission image detected by an emission microscope. A light emission display step of displaying light emission map information indicating the light emission points of each of the light emission types, and performing a failure analysis based on the light emission map information of each type displayed in the light emission display step. A failure analysis method using an emission microscope. 6. A failure analysis method using an emission microscope according to claim 5, wherein the light emission map information for each light emission type in the light emission display step is displayed in LSI chip units. 7. An arrangement state of light emitting points for each of different types of circuit blocks in the LSI chip is checked based on a light emission image detected by an emission microscope for a semiconductor device on which the LSI chips are arranged. A light emission display step of classifying the light emission points into a plurality of light emission types based on the arrangement state of the light emission points for each of the circuit blocks, and displaying light emission map information indicating the light emission points for each of the light emission types for each of the classified circuit blocks; An analysis step of performing a failure analysis based on emission map information for each emission type for each circuit block displayed in the emission display process. 8. An arrangement state of light emitting points of a semiconductor device on which LSI chips are arranged is detected based on a light emission image detected by an emission microscope, and a plurality of light emission points are determined based on the checked arrangement state of the light emitting points. A light emitting display step of displaying light emitting map information indicating an arrangement state of light emitting points for each of the classified light emitting types; and a semiconductor device on which LSI chips manufactured up to a desired manufacturing process are arranged. Inspection of foreign matter including defective appearance of the foreign matter, a foreign matter display step of displaying foreign matter map information indicating the state of occurrence of the inspected foreign matter, and light emission map information displayed in the light emission display step and displayed in the foreign matter display step A failure analysis method using an emission microscope, wherein the failure analysis is performed by collating the foreign matter map information with the foreign matter map information. 9. An arrangement state of light emitting points for each of different types of circuit blocks in the LSI chip is examined based on a light emission image detected by an emission microscope for a semiconductor device on which the LSI chips are arranged. A light emitting display process of classifying the light emitting points for each of the circuit blocks into a plurality of light emitting types and displaying light emitting map information indicating an array state of the light emitting points for each of the light emitting types for each of the classified circuit blocks. A foreign matter display step of inspecting foreign matter including a defective appearance on a semiconductor device on which LSI chips manufactured up to a desired manufacturing process step are arranged, and displaying foreign matter map information indicating a state of occurrence of the inspected foreign matter; An analysis step of performing a failure analysis by comparing the emission map information displayed in the emission display step with the foreign matter map information displayed in the foreign matter display step; Failure analysis method using the emission microscope and having a. 10. An arrangement state of light emitting points of a semiconductor device on which LSI chips are arranged is examined based on an emission image detected by an emission microscope, and a plurality of light emission points are determined based on the arrangement state of the examined light emitting points. A light emission calculation process of calculating the number of occurrences of each of the classified light emission types for each of the LSI chips; and a defective appearance on a semiconductor device on which the LSI chips manufactured up to a desired manufacturing process are arranged. A foreign matter calculating step of inspecting foreign matter including the same and calculating the number of inspected foreign matter for each of the LSI chips; the number of occurrences of each light emitting type of each LSI chip calculated in the light emission calculating step; LSI calculated in the calculation process
A failure analysis method using an emission microscope, comprising: outputting the number of foreign substances generated for each chip in association with each other, and performing a failure analysis based on the output association. 11. A semiconductor device on which LSI chips are arranged, an arrangement state of light emitting points is examined based on an emission image detected by an emission microscope, and a plurality of light emission points are determined based on the examined arrangement state of the light emitting points. An emission calculation process of classifying the number of light emission types for each type of circuit block in the LSI chip and an LSI chip manufactured up to a desired manufacturing process are arranged. Foreign matter including appearance defects on the semiconductor device to be inspected, and calculating the number of occurrences of the inspected foreign matter for different types of circuit blocks in the LSI chip; The number of occurrences of each light emission type for each circuit block and the number of occurrences of foreign matter for each circuit block calculated in the foreign matter calculation process are output in association with each other. Failure analysis method using the emission microscope characterized by having an analysis process of performing failure analysis on the basis of only. 12. An arrangement state of light emitting points of a semiconductor device on which an LSI chip is arranged is examined based on an emission image detected by an emission microscope, and a plurality of light emitting points are determined based on the arrangement state of the examined light emitting points. A light emission calculation step of calculating the number of occurrences of each of the light emission types classified for each of the LSI chips and for each of different types of circuit blocks in the LSI chip; A foreign matter calculation process for inspecting foreign matter including appearance defects on the semiconductor device on which the LSI chips arranged are arranged, and calculating the number of occurrences of the inspected foreign matter for each of the different types of circuit blocks for each of the LSI chips; The number of occurrences of each light emission type for each circuit block for each LSI chip calculated in the light emission calculation step and the number of occurrences of foreign matter for each circuit block calculated in the foreign matter calculation step The in association output, failure analysis method using the emission microscope characterized by having an analysis process of performing failure analysis on the basis of the output association. 13. A failure analysis using a failure analysis method using an emission microscope according to any one of claims 1 to 12, and a countermeasure for a failure cause estimated in a production line based on the failure analysis result. And manufacturing the semiconductor device by performing the method. 14. An arrangement state of light emitting points of a semiconductor device on which an LSI chip is arranged is examined based on an emission image detected by an emission microscope, and a plurality of light emitting points are determined based on the arrangement state of the examined light emitting points. A light emission calculating device for calculating the number of occurrences of each light emission type for each of the LSI chips, and outputting the number of occurrences for each light emission type of each LSI chip calculated by the light emission calculation device A failure analysis system using an emission microscope, comprising: 15. An arrangement state of light emitting points of a semiconductor device on which LSI chips are arranged is examined based on an emission image detected by an emission microscope, and a plurality of light emitting points are determined based on the arrangement state of the examined light emitting points. A light emission calculation device for calculating the number of occurrences of each of the light emission types for each of different types of circuit blocks in the LSI chip; and a circuit block in the LSI chip calculated by the light emission calculation device. A failure analysis system using an emission microscope, comprising: an output device that outputs the number of occurrences for each light emission type. 16. An arrangement state of light emitting points of a semiconductor device on which LSI chips are arranged is examined based on an emission image detected by an emission microscope, and a plurality of light emitting points are determined based on the examined arrangement state of the light emitting points. A light emission calculation device for calculating the number of occurrences for each of the light emission types classified for each of the LSI chips and for each of the different types of circuit blocks in the LSI chip; A failure analysis system using an emission microscope, comprising: an output device for outputting the number of occurrences of each light emission type for each circuit block for each LSI chip. 17. A database in which a correspondence relationship between each light emitting type of each circuit block for each LSI chip and a presumed cause of failure is registered in advance, and an emission microscope for a semiconductor device in which the LSI chips are arranged. The arrangement state of the light emitting points is checked based on the light emission image detected by the light emitting element, and the light emitting points are classified into a plurality of light emission types based on the checked arrangement state of the light emission points. A light emission calculation device that calculates for each type of circuit block for each LSI chip; and a database corresponding to the number of occurrences of each light emission type for each circuit block for each LSI chip calculated by the light emission calculation device. A failure analysis system using an emission microscope, comprising: an output device for searching for and outputting a cause of the failure. 18. An arrangement state of light emitting points of a semiconductor device on which LSI chips are arranged is examined based on an emission image detected by an emission microscope, and a plurality of light emitting points are determined based on the arrangement state of the examined light emitting points. An emission map information creating device that creates emission map information indicating emission points for each of the classified emission types, and displays emission map information for each type created by the emission map information creation device A failure analysis system using an emission microscope, comprising: 19. An arrangement state of light emitting points for each of different types of circuit blocks in the LSI chip is checked based on a light emission image detected by an emission microscope for a semiconductor device on which the LSI chips are arranged. A light emission map information creating device that classifies the light emission points into a plurality of light emission types based on the arrangement state of the light emission points for each of the circuit blocks, and creates emission map information indicating the light emission points for each light emission type for each of the classified circuit blocks; A failure analysis system using an emission microscope, comprising: a display device for displaying light emission map information for each light emission type for each circuit block created by the light emission map information creation device.