JP2001203209A - Method for manufacturing semiconductor wafer having epitaxial layer - Google Patents

Method for manufacturing semiconductor wafer having epitaxial layer

Info

Publication number
JP2001203209A
JP2001203209A JP2000331349A JP2000331349A JP2001203209A JP 2001203209 A JP2001203209 A JP 2001203209A JP 2000331349 A JP2000331349 A JP 2000331349A JP 2000331349 A JP2000331349 A JP 2000331349A JP 2001203209 A JP2001203209 A JP 2001203209A
Authority
JP
Japan
Prior art keywords
semiconductor wafer
susceptor
epitaxial layer
temperature
deposition
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000331349A
Other languages
Japanese (ja)
Inventor
Guenther Obermeier
オーバーマイアー ギュンター
Reinhold Wahlich
ヴァーリヒ ラインホルト
Alfred Buchner
ブーフナー アルフレート
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siltronic AG
Original Assignee
Wacker Siltronic AG
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Filing date
Publication date
Application filed by Wacker Siltronic AG filed Critical Wacker Siltronic AG
Publication of JP2001203209A publication Critical patent/JP2001203209A/en
Pending legal-status Critical Current

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Classifications

    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02Epitaxial-layer growth
    • C30B25/10Heating of the reaction chamber or the substrate
    • C30B25/105Heating of the reaction chamber or the substrate by irradiation or electric discharge
    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02Epitaxial-layer growth
    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B33/00After-treatment of single crystals or homogeneous polycrystalline material with defined structure
    • C30B33/02Heat treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

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  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Organic Chemistry (AREA)
  • Metallurgy (AREA)
  • Materials Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Manufacturing & Machinery (AREA)
  • Thermal Sciences (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor wafer which shows an optimized oxygen deposition characteristic in the following heat treatment and is covered with an epitaxial layer in a lamp furnace. SOLUTION: A semiconductor wafer to be mounted entirely to a susceptor is mechnically separated from the susceptor after an epitaxial layer is laminated on the semiconductor wafer, and a heating output is decreased until a cooling speed reaches 20 deg.C/sec or higher.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】後続の熱処理中に最適化され
た酸素析出特性を示すランプ炉内でエピタキシャル層を
エピタキシャル層を被覆した半導体ウェハを製造する方
法に関する。
FIELD OF THE INVENTION The present invention relates to a method for producing a semiconductor wafer having an epitaxial layer coated with an epitaxial layer in a lamp furnace exhibiting optimized oxygen deposition properties during a subsequent heat treatment.

【0002】半導体構成素子が搭載される成長した単結
晶層、即ちいわゆるエピタキシーもしくはエピタキシャ
ル成長層を有する単結晶、例えばシリコン層を有するシ
リコンウェハは、均質材料からなる半導体ウェハに対し
てある一定の利点を有する。例えば、エピタキシャル成
長した表面はポリッシングした表面に比較して、例えば
いわゆるCOP(crystal originated particle)であ
る欠陥密度が低く、このことは一般に完全な半導体構成
素子のより高い収率をもたらす。さらに、エピタキシャ
ル層は、注目に値する酸素含量を有せずかつ異種原子が
ドープされていてもい。
A grown single crystal layer on which semiconductor components are mounted, ie a single crystal with a so-called epitaxy or epitaxial growth layer, for example a silicon wafer with a silicon layer, has certain advantages over semiconductor wafers of homogeneous material. Have. For example, epitaxially grown surfaces have a lower defect density than, for example, so-called COPs (crystal originated particles) compared to polished surfaces, which generally leads to higher yields of complete semiconductor components. Furthermore, the epitaxial layer may have no noticeable oxygen content and may be doped with foreign atoms.

【0003】全ての被覆もしくは堆積プロセス中に、半
導体ウェハはまず加熱源により、好ましくは上方及び下
方加熱源、例えばランプ又はランプバンクにより加熱さ
れ、かつ引き続きソースガス、キャリヤガス及び場合に
よりドーピングガスからなるガス混合物に曝される。被
覆及び堆積は、例えばEP0714998A2に記載さ
れているような堆積室内のランプ炉により行われる。被
覆のために、半導体ウェハは、堆積チャンバの内部にあ
るサセプタのフライス加工部に手動で又は自動的に挿入
される。その際、半導体ウェハは全面的にサセプタに搭
載される、このことは半導体ウェハの均等な加熱を保証
する。さらに、一般にエピタキシャル層が堆積されない
ウェハの背面はソースガスから保護される。従来の技術
によれば、堆積チャンバは単数又は複数の半導体ウェハ
のために構成されている。サセプタの大きい熱量(ther
mische Masse)により、半導体ウェハは被覆後に、たと
え加熱出力をゼロに低下させたとしても、緩慢に冷却さ
れるに過ぎない。堆積プロセスは、1070〜1150
℃の範囲内で実施される。この場合、冷却速度はサセプ
タの大きな熱量に基づき一般に15℃/秒未満である。
このような熱履歴は、後続に熱処理中に、例えば780
℃の温度で3時間及び1000℃の温度で16時間で、
極めて少ない酸素析出を示す。
During the entire coating or deposition process, the semiconductor wafer is first heated by a heating source, preferably by upper and lower heating sources, such as lamps or lamp banks, and subsequently from a source gas, a carrier gas and optionally a doping gas. Exposed to a gas mixture. Coating and deposition are carried out by means of a lamp furnace in a deposition chamber, for example as described in EP 0 714 998 A2. For coating, the semiconductor wafer is manually or automatically inserted into a susceptor milling section inside the deposition chamber. In this case, the semiconductor wafer is completely mounted on the susceptor, which ensures an even heating of the semiconductor wafer. In addition, the backside of the wafer, where no epitaxial layer is typically deposited, is protected from the source gas. According to the prior art, the deposition chamber is configured for one or more semiconductor wafers. Large amount of heat of susceptor (ther
Due to mische masse), the semiconductor wafer is only cooled slowly after coating, even if the heating power is reduced to zero. The deposition process is between 1070 and 1150
It is carried out in the range of ° C. In this case, the cooling rate is generally less than 15 ° C./sec based on the large amount of heat of the susceptor.
Such a thermal history can be obtained during a subsequent heat treatment, for example at 780
3 hours at a temperature of 1000C and 16 hours at a temperature of 1000C.
It shows very little oxygen precipitation.

【0004】WO98/38675には、理想的酸素析
出を有する半導体ウェハ及び該半導体ウェハの製造方法
が記載されている。この場合には、理想的酸素析出と
は、半導体ウェハの表面に近い範囲内のバルクとミニマ
(Minima)において最大を有する酸素析出の濃度プロフ
ィールと解される。
[0004] WO 98/38675 describes a semiconductor wafer with ideal oxygen deposition and a method for manufacturing the semiconductor wafer. In this case, ideal oxygen precipitation is understood as the concentration profile of oxygen precipitation having a maximum in a bulk and a minimum within a range close to the surface of the semiconductor wafer.

【0005】このような酸素析出を有する半導体ウェハ
の製造は、WO98/38675によれば>1175℃
の温度で行われかつ引き続いての冷却速度の制御は好ま
しくは>50℃/秒である。この熱処理は、好ましくは
ランプ炉(Rapid Thermal Annealer, RTA)で実施さ
れる。次いで、例えば780℃の温度で3時間及び10
00℃の温度で16時間の後続熱処理中に、前記の濃度
プロフィールを有する酸素の析出が行われる。
The production of semiconductor wafers with such oxygen precipitates is, according to WO 98/38675,> 1175 ° C.
The control of the cooling rate, which is carried out at a temperature of and is preferably> 50 ° C./sec. This heat treatment is preferably performed in a lamp furnace (Rapid Thermal Annealer, RTA). Then, for example, at a temperature of 780 ° C. for 3 hours and 10 minutes.
During a subsequent heat treatment at a temperature of 00 ° C. for 16 hours, the precipitation of oxygen with the above-mentioned concentration profile takes place.

【0006】[0006]

【発明が解決しようとする課題】本発明の課題は、後続
の熱処理中に最適化された酸素析出特性を示す、ランプ
炉内でエピタキシャル層を堆積した半導体ウェハを製造
する方法を提供することであった。
SUMMARY OF THE INVENTION It is an object of the present invention to provide a method for producing a semiconductor wafer having an epitaxial layer deposited in a lamp furnace, which exhibits optimized oxygen deposition properties during a subsequent heat treatment. there were.

【0007】[0007]

【課題を解決するための手段】前記課題は、後続の熱処
理中に最適化された酸素析出特性を示す、ランプ炉内で
エピタキシャル層を被覆した半導体ウェハを製造する方
法により解決され、該方法は、全面的にサセプタに搭載
する半導体ウェハをエピタキシャル層の堆積後に機械的
にサセプタから分離し、引き続き加熱出力を、>25℃
/秒の冷却速度が生じるまで低下させることを特徴とす
る。
The object is solved by a method for producing a semiconductor wafer coated with an epitaxial layer in a lamp furnace, which exhibits optimized oxygen deposition properties during a subsequent heat treatment, the method comprising: The semiconductor wafer mounted entirely on the susceptor is mechanically separated from the susceptor after the deposition of the epitaxial layer, and the heating power is subsequently increased to> 25 ° C.
/ Second until the cooling rate is reduced.

【0008】本発明によれば、半導体ウェハを>115
0℃に加熱した後に、後続の熱処理中に最適化された酸
素析出特性を示す半導体ウェハを生じる、>25℃/秒
の冷却速度を保証するために、機械的にサセプタから分
離しなければならない。エピタキシャル層の堆積を<1
150℃の温度で実施する場合には、サセプタからの機
械的分離の前又は後に>1150℃への半導体ウェハの
付加的な加熱を行う。この場合、半導体ウェハを<11
50℃の温度に好ましくは1〜60秒、特に好ましくは
5〜25秒間加熱する。
In accordance with the present invention, a semiconductor wafer having a> 115
After heating to 0 ° C., it must be mechanically separated from the susceptor to ensure a cooling rate of> 25 ° C./s, which results in semiconductor wafers exhibiting optimized oxygen deposition properties during subsequent heat treatments . Epitaxial layer deposition <1
If carried out at a temperature of 150 ° C., additional heating of the semiconductor wafer to> 1150 ° C. is performed before or after mechanical separation from the susceptor. In this case, the semiconductor wafer is <11
Heating to a temperature of 50 ° C. is preferably for 1 to 60 seconds, particularly preferably 5 to 25 seconds.

【0009】従って、本発明の課題はまた、後続の熱処
理中に最適化された酸素析出特性を示す、ランプ炉内で
エピタキシャル層を被覆した半導体ウェハを製造する方
法において解決され、該方法は、全面的にサセプタに搭
載する半導体ウェハをエピタキシャル層の堆積後に機械
的にサセプタから分離し、>1150℃の温度に加熱
し、引き続き加熱出力を、>25℃/秒の冷却速度が生
じるまで低下させることを特徴とする。
Accordingly, the object of the present invention is also solved in a method for producing a semiconductor wafer coated with an epitaxial layer in a lamp furnace, which exhibits optimized oxygen deposition properties during a subsequent heat treatment, the method comprising: The semiconductor wafer mounted entirely on the susceptor is mechanically separated from the susceptor after the deposition of the epitaxial layer and heated to a temperature of> 1150 ° C., and the heating power is subsequently reduced until a cooling rate of> 25 ° C./sec occurs. It is characterized by the following.

【0010】本発明の課題はまた、後続の熱処理中に最
適化された酸素析出特性を示す、ランプ炉内でエピタキ
シャル層を被覆した半導体ウェハを製造する方法により
解決され、該方法は、全面的にサセプタに搭載する半導
体ウェハをエピタキシャル層の堆積後に>1150℃の
温度に加熱し、機械的にサセプタから分離し、引き続き
加熱出力を、>25℃/秒の冷却速度が生じるまで低下
させることを特徴とする。
The object of the invention is also solved by a method for producing a semiconductor wafer coated with an epitaxial layer in a lamp furnace, which exhibits optimized oxygen deposition properties during a subsequent heat treatment, the method comprising the steps of: Heating the semiconductor wafer mounted on the susceptor to a temperature of> 1150 ° C. after deposition of the epitaxial layer and mechanically separating it from the susceptor, and subsequently reducing the heating power until a cooling rate of> 25 ° C./sec occurs. Features.

【0011】本発明によれば、サセプタからの半導体ウ
ェハの機械的分離はウェハの急速な加熱及び急速な冷却
を保証する。
According to the present invention, mechanical separation of the semiconductor wafer from the susceptor ensures rapid heating and rapid cooling of the wafer.

【0012】使用されるソースガス、ドーピングガス及
び洗浄ガス、及び堆積プロトコル、即ち処理時間、プロ
セスステップの順序並びにエピタキシャル層の成長中の
温度関係並びに堆積速度は、本発明の対象ではないかつ
当業者には、例えば“Epitaxial Technology, Ed. Jaya
nt, Academic Press Inc. Orlando, Florida; 1986”か
ら公知である。
The source gases, doping and cleaning gases used, and the deposition protocol, ie, processing times, sequence of process steps, and temperature relationships during epitaxial layer growth and deposition rates are not the subject of this invention and will be understood by those skilled in the art. Include, for example, “Epitaxial Technology, Ed. Jaya
nt, Academic Press Inc. Orlando, Florida; 1986 ".

【0013】エピタキシャル被覆を実施する前に、半導
体ウェハをランプ炉内で還元性ガス雰囲気内で1150
〜1300℃の温度で1〜60秒間熱処理することがで
きる。該ガス雰囲気は、好ましくは水素10〜80体積
%を有する好ましくはアルゴン及び水素を含む。熱処理
は半導体ウェハの表面上のCOP密度を低下させ、そう
して結晶欠陥の発生を抑制する。
Prior to performing the epitaxial coating, the semiconductor wafer is placed in a lamp furnace in a reducing gas atmosphere at 1150 mm.
Heat treatment can be performed at a temperature of 1300 ° C. for 1 to 60 seconds. The gaseous atmosphere preferably comprises argon and hydrogen having preferably 10 to 80% by volume of hydrogen. The heat treatment lowers the COP density on the surface of the semiconductor wafer, thereby suppressing the occurrence of crystal defects.

【0014】エピタキシャル被覆の実施後に、半導体ウ
ェハは疎水性表面を有しかつこの形で本発明による方法
で処理することができる。しかし、本発明の範囲内では
強制的に必要ではないが、ウェハ表面を親水性にする、
即ち例えば酸化作用するガス、例えばオゾンで処理する
ことにより薄い酸化物層で被覆することが可能である。
After the epitaxial coating has been carried out, the semiconductor wafer has a hydrophobic surface and can be treated in this way with the method according to the invention. However, while not required within the scope of the present invention, making the wafer surface hydrophilic,
That is, it is possible to cover with a thin oxide layer, for example, by treating with an oxidizing gas, for example, ozone.

【0015】エピタキシャル層の堆積及び/又は酸化処
理後に、なお存在するソースガス、キャリヤガス又は酸
化作用ガスを追出するために、ランプ炉、特に堆積チャ
ンバを不活性洗浄ガス、例えば窒素で洗浄する。次い
で、堆積チャンバを不活性ガス雰囲気下に置く。ガス雰
囲気は、好ましくは、水素、アルゴン、窒素及びこれら
のガスの任意の混合物を包含するガスの群から選択す
る。特に好ましくは、該ガス雰囲気はアルゴン及び水素
10〜70体積%を含む。堆積チャンバの洗浄は、サセ
プタからの機械的分離の前又は後に行う。
After the deposition and / or oxidation treatment of the epitaxial layer, the lamp furnace, in particular the deposition chamber, is cleaned with an inert cleaning gas, for example nitrogen, in order to drive off any source gas, carrier gas or oxidizing gas still present. . Next, the deposition chamber is placed under an inert gas atmosphere. The gas atmosphere is preferably selected from the group of gases including hydrogen, argon, nitrogen and any mixtures of these gases. Particularly preferably, the gas atmosphere comprises 10 to 70% by volume of argon and hydrogen. Cleaning of the deposition chamber occurs before or after mechanical separation from the susceptor.

【0016】サセプタからの半導体ウェハの機械的分離
(>1150℃の温度への加熱前又は後)は、サセプタ
を降下させるか又はサセプタを持ち上げることにより行
う。静止サセプタを使用する場合には、サセプタを持ち
上げることによりウェハを分離する。これは例えばサセ
プタの貫通孔内を半導体ウェハの背面方向に案内される
ピン支持台(Pin-Auflage)により行う。可動サセプタ
の場合には、サセプタを降下させることによりウェハを
サセプタから分離し、一方ウェハ自体はピン支持台上に
静止する。ピン支持台はウェハを汚染しない耐熱性材
料、例えば石英ガラス、酸化アルミニウム、炭化窒素又
はシリコンからなり、好ましくは小さい支持面及び小さ
い熱量を有する。
The mechanical separation of the semiconductor wafer from the susceptor (before or after heating to a temperature of> 1150 ° C.) is performed by lowering the susceptor or raising the susceptor. If a stationary susceptor is used, the wafer is separated by lifting the susceptor. This is performed, for example, by a pin support (Pin-Auflage) guided in the through hole of the susceptor toward the back side of the semiconductor wafer. In the case of a movable susceptor, the wafer is separated from the susceptor by lowering the susceptor, while the wafer itself rests on the pin support. The pin support is made of a heat-resistant material that does not contaminate the wafer, such as quartz glass, aluminum oxide, nitrogen carbide or silicon, and preferably has a small support surface and a small amount of heat.

【0017】特に、エピタキシャル層の堆積を<115
0℃で実施した場合には、ウェハを前記の不活性ガス雰
囲気内でランプを用いて、好ましくは上方及び下方ラン
プ又はランプバンクを用いて>1150℃の温度に少な
くとも1秒間加熱する。この場合、ウェハはサセプタに
載っているか又は既にサセプタから機械的に分離されか
つ例えばピン支持台に載っている。
In particular, the deposition of the epitaxial layer is reduced to <115
If carried out at 0 ° C., the wafer is heated to a temperature of> 1150 ° C. for at least 1 second with a lamp, preferably with an upper and lower lamp or lamp bank, in the above-mentioned inert gas atmosphere. In this case, the wafer rests on the susceptor or is already mechanically separated from the susceptor and rests, for example, on a pin carrier.

【0018】>1150℃の温度でエピタキシャル層を
堆積させた後又は半導体ウェハを>1150℃の温度に
加熱した後に、加熱出力を、半導体ウェハが急速に好ま
しくは950℃、特に好ましくは850℃の温度に冷却
するまで低下させる。エピタキシャル層の堆積又は半導
体ウェハの加熱後の冷却速度は、950℃まで、好まし
くは850℃までの温度範囲内で好ましくは10℃/秒
〜200℃/秒、特に好ましくは20℃/秒〜150℃
/秒及び特に30℃/秒〜100℃/秒である。
After depositing the epitaxial layer at a temperature of> 1150 ° C. or after heating the semiconductor wafer to a temperature of> 1150 ° C., the heating power is rapidly reduced by the semiconductor wafer to preferably 950 ° C., particularly preferably 850 ° C. Lower until cool to temperature. The cooling rate after the deposition of the epitaxial layer or the heating of the semiconductor wafer is preferably in the temperature range up to 950 ° C., preferably up to 850 ° C., preferably from 10 ° C./sec to 200 ° C./sec, particularly preferably from 20 ° C./sec to 150 ° C. ° C
/ Sec and especially 30 ° C / sec to 100 ° C / sec.

【0019】30℃/秒〜100℃/秒の速度は、ラン
プ又はランプバンクを遮断する、即ち加熱出力をゼロに
低下させることにより達成される。>100℃/秒への
冷却速度の上昇は、ランプ炉を不活性ガス、例えば窒
素、アルゴン、ヘリウム又はこれらのガスの混合物で洗
浄することにより達成される。
A speed of 30 ° C./sec to 100 ° C./sec is achieved by shutting off the lamp or lamp bank, ie reducing the heating power to zero. Increasing the cooling rate to> 100 ° C./sec is achieved by flushing the lamp furnace with an inert gas such as nitrogen, argon, helium or a mixture of these gases.

【0020】可動サセプタからの半導体ウェハの機械的
分離は、半導体ウェハの前面及び背面からの空間的分離
を可能にするので、背面を前面とは別のガスで洗浄する
ことができる(図1に示されている)。好ましくは、析
出における変化、特に析出密度を上昇させるために、半
導体ウェハの背面を洗浄する。
Mechanical separation of the semiconductor wafer from the movable susceptor allows spatial separation from the front and back of the semiconductor wafer, so that the back can be cleaned with a different gas than the front (see FIG. 1). It is shown). Preferably, the back side of the semiconductor wafer is cleaned in order to increase the changes in the deposition, in particular the deposition density.

【0021】半導体ウェハが少なくとも800℃の温度
に冷却された後に、該半導体ウェハをランプ炉から自動
的に又は手動で取り出す。このエピタキシャル層が被覆
された半導体ウェハは、後続の熱処理中に最適化された
酸素析出特性を示す。後続の熱処理は、従来の技術に基
づく直立型炉又は水平型炉内で例えば780℃の温度で
3時間及び1000℃の温度で16時間行う。
After the semiconductor wafer has been cooled to a temperature of at least 800 ° C., the semiconductor wafer is automatically or manually removed from the lamp furnace. The semiconductor wafer coated with this epitaxial layer shows optimized oxygen deposition properties during the subsequent heat treatment. The subsequent heat treatment is carried out in a vertical or horizontal furnace according to the prior art, for example at a temperature of 780 ° C. for 3 hours and at a temperature of 1000 ° C. for 16 hours.

【0022】[0022]

【実施例】図1a,b,2a及びbには、半導体ウェハ
がエピタキシャル被覆を実施する間に全面的に搭載され
るサセプタから半導体ウェハを機械的に分離する装置が
2つの好ましい実施例で示されている。さらに、本発明
による方法を実施するために適当である上方チャンバ及
び下方チャンバを有するランプ炉の構造が図式的に示さ
れている。
1a, 1b, 2a and 2b show two preferred embodiments of an apparatus for mechanically separating a semiconductor wafer from a susceptor which is fully mounted during the epitaxial coating of the semiconductor wafer. Have been. Furthermore, the structure of a lamp furnace having an upper chamber and a lower chamber which is suitable for carrying out the method according to the invention is shown schematically.

【0023】図1a及び図2aに示されたエピタキシャ
ル被覆を実施している間に、ランプ炉の堆積チャンバ1
を加熱素子2,3により加熱する。この場合、半導体ウ
ェハ4はサセプタ5に全面的に搭載されている。ソース
ガス、キャリヤガス及び/又はドーピングガスの流入
は、ガス供給導管7及び8を介して行い、ガス排出はガ
ス排出導管9,10を介して行う。ピン支持台11はサ
セプタ内の貫通孔に挿入されている。これらはウェハ4
には接触しない。エピタキシャル被覆の実施後に、好ま
しくは両者のチャンバを洗浄しかつ不活性ガス雰囲気下
に置く。
While performing the epitaxial coating shown in FIGS. 1a and 2a, the deposition chamber 1 of the lamp furnace
Is heated by the heating elements 2 and 3. In this case, the semiconductor wafer 4 is entirely mounted on the susceptor 5. The inflow of the source gas, the carrier gas and / or the doping gas takes place via gas supply conduits 7 and 8, and the gas discharge takes place via gas discharge conduits 9, 10. The pin support 11 is inserted into a through hole in the susceptor. These are wafer 4
Do not touch. After performing the epitaxial coating, preferably both chambers are cleaned and placed under an inert gas atmosphere.

【0024】ウェハを可動サセプタの降下によりサセプ
タから分離し、一方ウェハは静止ピン支持台に載る(図
1bに示されている)。
The wafer is separated from the susceptor by lowering the movable susceptor, while the wafer rests on a stationary pin support (shown in FIG. 1b).

【0025】図2bは、ウェハの持ち上げによる静止サ
セプタからの半導体ウェハの機械的分離を示す。この分
離は、例えばサセプタを貫通する孔内を半導体ウェハの
背面方向に案内されるピン支持台により行う。
FIG. 2b shows the mechanical separation of a semiconductor wafer from a stationary susceptor by lifting the wafer. This separation is performed by, for example, a pin support that is guided in the hole passing through the susceptor toward the rear surface of the semiconductor wafer.

【0026】エピタキシャル層の堆積を<1150℃の
温度で実施する場合には、>1150℃の温度への半導
体ウェハの加熱はサセプタからの機械的分離の前又は後
に行う。
If the deposition of the epitaxial layer is carried out at a temperature of <1150 ° C., the heating of the semiconductor wafer to a temperature of> 1150 ° C. takes place before or after the mechanical separation from the susceptor.

【0027】加熱素子2,3により>1150℃の温度
に少なくとも1秒間加熱した後に、加熱出力を、半導体
ウェハが急速に少なくとも950℃の温度に冷却される
まで低下させる。冷却中には、半導体ウェハは好ましく
はピン支持台に載っている、即ち半導体ウェハはサセプ
タの大きな熱量から分離されている。
After heating by the heating elements 2 and 3 to a temperature of> 1150 ° C. for at least 1 second, the heating power is reduced until the semiconductor wafer is rapidly cooled to a temperature of at least 950 ° C. During cooling, the semiconductor wafer is preferably resting on a pin support, i.e. the semiconductor wafer is separated from the large heat of the susceptor.

【0028】ピン支持台は、有利には可能な限り小さい
支持面を有するので、冷却期間中に支持台からウェハへ
のエネルギー伝達は行われない。最後に、ウェハをラン
プ炉から取り出しかつ後続の熱処理を行うことができ
る。
The pin carrier advantageously has as small a support surface as possible, so that no energy is transferred from the carrier to the wafer during the cooling period. Finally, the wafer can be removed from the lamp furnace and subjected to a subsequent heat treatment.

【0029】図3a及びbは、冷却速度(図3a)及び
温度(図3b)に依存した酸素析出密度を示す。
FIGS. 3a and 3b show the oxygen precipitation density as a function of cooling rate (FIG. 3a) and temperature (FIG. 3b).

【0030】特に図3aは、ランプ炉内で1200℃の
温度に10秒間加熱し、引き続き780℃の温度で3時
間及び1000℃の温度で16時間熱処理した後の冷却
速度に対するエピタキシャル層が被覆された半導体ウェ
ハの酸素析出の密度の依存関係を示す。特に図3bは、
ランプ炉内で及び80℃/秒の冷却速度で10秒間加熱
し、引き続き780℃の温度で3時間及び1000℃の
温度で16時間熱処理した後の温度に対するエピタキシ
ャル層が被覆された半導体ウェハの酸素析出の密度の依
存関係を示す。
In particular, FIG. 3a shows that the epitaxial layer was coated for a cooling rate after heating in a lamp furnace to a temperature of 1200 ° C. for 10 seconds, followed by a heat treatment at a temperature of 780 ° C. for 3 hours and at a temperature of 1000 ° C. for 16 hours. 3 shows the dependence of the density of oxygen precipitation on a semiconductor wafer. In particular, FIG.
Heating in a lamp furnace and at a cooling rate of 80 ° C./second for 10 seconds, followed by a heat treatment at a temperature of 780 ° C. for 3 hours and a temperature of 1000 ° C. for 16 hours, the oxygen of the semiconductor wafer coated with the epitaxial layer with respect to the temperature. 4 shows the dependency of the density of precipitation.

【図面の簡単な説明】[Brief description of the drawings]

【図1】aは本発明による方法を実施する装置の第1実
施例におけるエピタキシャル被覆工程を示す図及びbは
同実施例における熱処理工程を示す図である。
FIG. 1A is a view showing an epitaxial coating step in a first embodiment of an apparatus for performing a method according to the present invention, and FIG. 1B is a view showing a heat treatment step in the embodiment.

【図2】aは本発明による方法を実施する装置の第2実
施例におけるエピタキシャル被覆工程を示す図及びbは
同実施例における熱処理工程を示す図である。
FIG. 2A is a view showing an epitaxial coating step in a second embodiment of the apparatus for performing the method according to the present invention, and FIG. 2B is a view showing a heat treatment step in the embodiment.

【図3】aは冷却速度に対する酸素析出密度の依存関係
を示すグラフ及びbは温度に対する酸素析出密度の依存
関係を示すグラフである。
FIG. 3A is a graph showing the dependency of the oxygen precipitation density on the cooling rate, and FIG. 3B is a graph showing the dependency of the oxygen precipitation density on the temperature.

【符号の説明】[Explanation of symbols]

1 堆積チャンバ、 2 加熱素子、 3 加熱素子、
4 半導体ウェハ、5 サセプタ、 7 ガス供給導
管、 8 ガス供給導管、 9 ガス排出導管、 10
ガス供給装置、 11 ピン支持台
1 deposition chamber, 2 heating element, 3 heating element,
Reference Signs List 4 semiconductor wafer, 5 susceptor, 7 gas supply conduit, 8 gas supply conduit, 9 gas discharge conduit, 10
Gas supply device, 11 pin support

フロントページの続き (72)発明者 ラインホルト ヴァーリヒ ドイツ連邦共和国 ティットモーニング ブルーメンシュトラーセ 10 (72)発明者 アルフレート ブーフナー オーストリア国 ピッシェルスドルフ ヌ ンマー 66Continued on the front page (72) Inventor Reinhold Warich, Germany Tit Morning Blumenstrasse 10 (72) Inventor Alfred Buchner, Austria Pischelsdorf Nummer 66

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 後続の熱処理中に最適化された酸素析出
特性を示す、ランプ炉内でエピタキシャル層を被覆した
半導体ウェハを製造する方法において、全面的にサセプ
タに搭載する半導体ウェハをエピタキシャル層の堆積後
に機械的にサセプタから分離し、引き続き加熱出力を、
>25℃/秒の冷却速度が生じるまで低下させることを
特徴とする、エピタキシャル層を有する半導体ウェハの
製造方法。
1. A method for producing a semiconductor wafer coated with an epitaxial layer in a lamp furnace, which exhibits an oxygen deposition characteristic optimized during a subsequent heat treatment. Mechanically separated from the susceptor after deposition, and subsequently heating output,
A method for producing a semiconductor wafer having an epitaxial layer, wherein the cooling rate is reduced until a cooling rate of> 25 ° C./sec occurs.
【請求項2】 後続の熱処理中に最適化された酸素析出
特性を示す、ランプ炉内でエピタキシャル層を被覆した
半導体ウェハを製造する方法において、全面的にサセプ
タに搭載する半導体ウェハをエピタキシャル層の堆積後
に機械的にサセプタから分離し、>1150℃の温度に
加熱し、引き続き加熱出力を、>25℃/秒の冷却速度
が生じるまで低下させることを特徴とする、エピタキシ
ャル層を有する半導体ウェハの製造方法。
2. A method for producing a semiconductor wafer coated with an epitaxial layer in a lamp furnace, wherein the semiconductor wafer has an oxygen deposition characteristic optimized during a subsequent heat treatment. A semiconductor wafer having an epitaxial layer, characterized in that it is mechanically separated from the susceptor after deposition, heated to a temperature of> 1150 ° C. and subsequently reduces the heating power until a cooling rate of> 25 ° C./s occurs. Production method.
【請求項3】 後続の熱処理中に最適化された酸素析出
特性を示す、ランプ炉内でエピタキシャル層を被覆した
半導体ウェハを製造する方法において、全面的にサセプ
タに搭載する半導体ウェハをエピタキシャル層の堆積後
に>1150℃の温度に加熱し、機械的にサセプタから
分離し、引き続き加熱出力を、>25℃/秒の冷却速度
が生じるまで低下させることを特徴とする、エピタキシ
ャル層を有する半導体ウェハの製造方法。
3. A method for producing a semiconductor wafer coated with an epitaxial layer in a lamp furnace, wherein the semiconductor wafer has an oxygen deposition characteristic optimized during a subsequent heat treatment. Heating the semiconductor wafer after deposition to a temperature of> 1150 ° C., mechanically separating it from the susceptor, and subsequently reducing the heating power until a cooling rate of> 25 ° C./s occurs; Production method.
【請求項4】 半導体ウェハをランプ炉内でエピタキシ
ャル被覆を実施する前に、還元性ガス雰囲気内で115
0〜1300℃の温度で1〜60秒間熱処理することを
特徴とする請求項1から3までのいずれか1項記載の方
法。
4. The method according to claim 1, wherein the semiconductor wafer is subjected to 115.degree.
The method according to any one of claims 1 to 3, wherein the heat treatment is performed at a temperature of 0 to 1300 ° C for 1 to 60 seconds.
【請求項5】 半導体ウェハの機械的分離を静止サセプ
タからウェハの持ち上げ及び可動サセプタからサセプタ
の降下により行うことを特徴とする請求項1から4まで
のいずれか1項記載の方法。
5. The method according to claim 1, wherein the mechanical separation of the semiconductor wafer is performed by lifting the wafer from a stationary susceptor and lowering the susceptor from a movable susceptor.
JP2000331349A 1999-11-02 2000-10-30 Method for manufacturing semiconductor wafer having epitaxial layer Pending JP2001203209A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19952705.9 1999-11-02
DE1999152705 DE19952705A1 (en) 1999-11-02 1999-11-02 Production of a semiconductor wafer with an epitaxial layer comprises placing a wafer on a susceptor and mechanically removing from the susceptor after the epitaxial layer has been deposited

Publications (1)

Publication Number Publication Date
JP2001203209A true JP2001203209A (en) 2001-07-27

Family

ID=7927653

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Country Status (3)

Country Link
JP (1) JP2001203209A (en)
KR (1) KR20010051407A (en)
DE (1) DE19952705A1 (en)

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