JP2001202293A - Fault detection system for external memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a fault detection system for an external memory capable of storing a parity bit without increasing the number of the external memory and capable of storing a parity bit without regard to a storing form in the external memory as for the fault detection system for the external memory provided in outside of a large-scale integrated circuit, etc., for storing data, etc. SOLUTION: A storing area, that is an internal memory, for storing the parity bit in inside of the large-scale integrated circuit is secured and in the case of writing data in the specific address of the external memory, the parity bit is generated from the data and is written at the same address as the address of the external memory in the internal memory.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a large scale integrated circuit and a field programmable gate array (Field Pr
ogrammable GateArray: usually abbreviated as FPGA. The present invention relates to a failure detection method for an external memory that is provided outside and stores data and the like, and in particular, stores parity bits for failure detection without increasing the number of the external memories, And a failure detection method for an external memory capable of storing the parity bit regardless of the storage format.

[0002] The scale of a large-scale integrated circuit or a field-programmable gate array (hereinafter referred to as a large-scale integrated circuit) which performs a main function in a communication device or an information processing device. Becomes larger, the number of data bits required for the large-scale integrated circuit to perform its function increases, the capacity of an external memory provided outside the large-scale integrated circuit increases, and the large-scale integrated circuit can be applied to the external memory. The number of memory elements to be used is increasing.

At the same time, the speed of communication devices and information processing devices has been rapidly increasing, and a high-speed memory such as a static
Static Random Access M
emory: Usually abbreviated as SRAM. ) Is increasing in some cases. Static random access
An increase in the number of applications is unavoidable because the memory capacity of each memory is small, but it is necessary to suppress the increase in the number of applications because the static random access memory has a high unit price.

In addition, while the storage bit width of the static random access memory is about 16 bits at the maximum, the length of data to be stored is increasing. For this reason, the storage format for the static random access memory has been diversified.

Therefore, parity bits for fault detection are stored without increasing the number of static random access memories, and parity bits for fault detection are stored regardless of the storage format. There is a demand for the development of a failure detection method for an external memory that can be used.

[0006]

2. Description of the Related Art FIG. 17 is a diagram showing a conventional external memory failure detection method.

In FIG. 17, 1d is a large-scale integrated circuit,
2 is an external memory.

The large-scale integrated circuit 1d includes therein an address generation unit 11, a data generation / reception unit 12, and a parity bit generation / reception unit 13 (in the figure, it is abbreviated as "parity generation / reception unit. , Etc.), and a timing signal generation unit 14 (abbreviated as “timing generation unit” in the figure; the same applies hereinafter in the figure).

The addresses generated by the address generation unit 11 (abbreviated as "A" in the figure, and may be similarly denoted in the figures hereinafter) are supplied to the external memory 2 in a parallel format. Is done. Note that "A (7-0)" indicates that the address is composed of eight bits from bit 7 which is the most significant bit to bit 0 which is the least significant bit.
The fact that the address is 8 bits is merely an example.

[0010] Between the data generation / reception unit 12 and the data terminal of the external memory 2, data in a parallel format (abbreviated as "D" in the figure, and may be similarly denoted in the following drawings in the same manner). Writing and reading are performed.

A parity bit (abbreviated as "P" in the figure) between the parity bit generation / reception unit 13 and the parity bit terminal of the external memory 2. In the figure, the same applies hereinafter. ) Is written and read.

The timing signal generation unit 14 is connected to the external memory 2
, A chip enable signal (abbreviated as “CE” in the drawing. The drawing may be similarly denoted in the following description) and a read / write control signal ( In the figure, it is abbreviated as “R / W”.
Supply.

FIG. 18 is a diagram showing mapping of an external memory in the configuration of FIG.

Each address of the external memory 2 in FIG.
For example, a parity bit generated from data described later is stored in the most significant bit, and the data is stored in the remaining storage area.

When writing data to the external memory, the parity bit generation / reception unit 13 generates a parity bit in accordance with the writing of the data generated by the data generation / reception unit 12 in FIG. When data is read from the external memory, the data generation / reception unit 12 reads the data and at the same time the parity bit generation / reception unit 13 reads the parity bits from the internal memory, and a parity check unit (not shown) Performs a parity check to detect a failure in the external memory.

[0016]

SUMMARY OF THE INVENTION As described above,
As communication devices and information processing devices become larger and faster,
The number of cases where a static random access memory is applied to an external memory is increasing, and the number of applications is increasing steadily.

Moreover, the length of the stored data may be larger than the bit width of a normal static random access memory. In this case, an area for storing parity bits may not be able to be secured in the storage area of the static random access memory for storing data, and a static random access memory for storing only parity bits may not be available. -The need for additional access memory arises.

In general, since static random access memory has a high unit price, increasing the number of applications for storing only parity bits has a disadvantage.

Further, as the length of data to be stored becomes larger than the bit width of a normal static random access memory, the data storage format is diversified. Need to be matched to this.

The present invention has been made in view of the above problems, and in particular, stores parity bits without increasing the number of static random access memories, and stores parity bits regardless of the data storage format. It is an object of the present invention to provide a failure detection method for an external memory that can perform the failure detection.

[0021]

The first means of the present invention is as follows.
When a storage area for storing parity bits, that is, an internal memory, is reserved inside the large-scale integrated circuit, and when writing data to a specific address of the external memory, a parity bit is generated from the data, and the parity bit is generated. This is a technique for writing to the same address of the internal memory as that of the external memory.

According to the first means of the present invention, the parity bit generated from the data to be written to the external memory is written to the same address in the internal memory as the address of the external memory to which the data is to be written. At the time of reading, if the parity bit is read from the same address in the internal memory as that of the external memory, the normality of the data read from the external memory can be checked.

A second means of the present invention is to secure a storage area for storing parity bits, that is, an internal memory inside a large-scale integrated circuit, and to write data to a plurality of specific addresses in an external memory. A parity bit is generated from the data when writing all the data over the internal memory, and the parity bit is written to an address of the internal memory determined from a plurality of addresses of the external memory.

According to the second means of the present invention, the parity bits generated from the data to be written over a plurality of addresses of the external memory are written to the internal memory at addresses determined from the plurality of addresses of the external memory. When data is read from the memory, the normality of the data read from the external memory can be checked by reading the parity bit from an address of the internal memory determined from a plurality of addresses of the external memory.

A third means of the present invention secures a storage area for storing parity bits, that is, an internal memory, inside a large-scale integrated circuit, and writes data in a partial storage area of a specific address in an external memory. Occasionally, a parity bit is generated from the data to be written to the partial storage area, and the parity bit is determined by an address of the internal memory determined by the address of the external memory and the position of the partial storage area. It is a technology to write to.

According to the third means of the present invention, a parity bit generated from data to be written to the partial storage area of the external memory is determined from the partial storage area of the external memory of the internal memory. Write to the address
When reading data from the external memory,
By reading the parity bit written at the address determined from the partial storage area of the external memory,
The normality of data read from the external memory can be checked.

A fourth means of the present invention is to secure a plurality of bits of storage area for storing parity bits, that is, an internal memory inside a large scale integrated circuit, and to write data to a specific address of an external memory. A parity bit is generated from the data, all parity bits of the internal memory are temporarily read from an address determined from the address of the external memory, and written to a bit position of the external memory determined from the address. In this technique, only the parity bit is updated and written to the address of the internal memory.

According to the fourth aspect of the present invention, when data is read from the external memory, all the parity bits are once read from the address determined from the relevant address in the external memory, and are determined from the relevant address in the external memory. By extracting only the parity bit written in the bit position, the normality of the data read from the external memory can be checked.

A fifth means of the present invention is to secure a multi-bit storage area for storing parity bits, that is, an internal memory, inside a large-scale integrated circuit, and store one data at a plurality of specific addresses of the external memory. When writing, a plurality of parity bits are generated from the same bits of a plurality of addresses of the data, and the plurality of parity bits are written to an address of the internal memory determined from the address of the external memory. is there.

According to the fifth means of the present invention, when reading data from the external memory, if all the parity bits are read from an address of the internal memory determined from a plurality of addresses of the external memory, the data can be read from the external memory. The normality of the read data can be checked.

[0031]

FIG. 1 shows a first embodiment of the present invention, in which one address is stored in one address of an external memory.
This is a configuration in a case where the parity bit is stored in the internal memory at the same address as that of the external memory.

In FIG. 1, 1 is a large-scale integrated circuit, and 2 is an external memory.

The large-scale integrated circuit 1 includes an address generator 11, a data generator / receiver 12, a parity bit generator / receiver 13, a timing signal generator 14, and an internal memory 15 therein.

FIG. 2 shows an external memory in the configuration of FIG.
FIG. 4 is a diagram showing mapping of an internal memory.

Data is stored in all the storage areas of each address of the external memory 2 having the configuration shown in FIG.

On the other hand, the storage area of each address of the internal memory having the configuration shown in FIG. 1 has a 1-bit configuration, and is generated from the data stored in the external memory at the same address as that of the external memory. Parity bits are stored.

Therefore, the addresses generated by the address generator 11 are supplied to the address terminals of the external memory 2 and the internal memory 15 in a parallel manner. Here, “A (7
"-0)" indicates that the address is composed of eight bits, from bit 7 being the most significant bit to bit 0 being the least significant bit. Incidentally, the fact that the address has an 8-bit configuration is merely an example.

Between the data generation / reception unit 12 and the data terminal of the external memory 2, writing and reading of parallel data are performed.

Writing and reading of parity bits are performed between the parity bit generation / reception unit 13 and the data terminals of the internal memory 15.

The timing signal generation unit 14 is connected to the external memory 2
A chip enable signal is supplied to a chip select terminal, and a read / write control signal is supplied to a write enable terminal.

FIG. 3 is a timing chart showing the operation of the configuration of FIG. 1. FIG. 3A is a timing chart when data is written to the external memory, and FIG.
The timing when reading data from external memory
The chart is shown.

Although the address and the data are parallel signals of a plurality of bits, they are described as if they were single bits in the figure. This is the same in all subsequent timing charts.

At the time of writing data to the external memory 2, the address generation unit 11 converts bits 7 to 0
Of the external memory 2 and the internal memory 15
, And data from the data generation / reception unit 12 is transmitted to the external memory 2 and the parity bit generation / reception unit 13.
Supplied to The data supplied to the external memory 2 is written to a specified address. On the other hand, the parity bit generated from the received data by the parity bit generation / reception unit 13 is supplied to the data terminal of the internal memory and written to the designated address.

The timing signal generator 14 is connected to the external memory 2
And the chip enable signal commonly supplied to the internal memory 15 indicates that the memory can be accessed by the logic level "L", so that the logic level is "L" at the time of writing. In addition, the read signal supplied by the timing signal generation unit 14 to the external memory 2 and the internal memory 15 in common.
Since the write control signal indicates that writing is possible when the logic level is "H", the logic level is "H" at the time of writing.

On the other hand, when data is read from the external memory, an address of 8 bits from bit 7 to bit 0 is commonly specified by the address generation unit 11 to the external memory 2 and the internal memory 15. At the same time as the data is read and supplied to the data generation / reception unit 12, the parity bit is read from the specified address in the internal memory and supplied to the parity bit generation / reception unit 13.

The timing signal generator 14 is connected to the external memory 2
And the chip enable signal commonly supplied to the internal memory 15 indicates that the memory is accessible by the logic level "L", so that the logic level is also "L" at the time of reading. In addition, the read signal supplied by the timing signal generation unit 14 to the external memory 2 and the internal memory 15 in common.
The write control signal indicates that reading is possible when the logic level is "L", so the logic level is "L" at the time of reading.

The data received by the data generation / reception unit 12 and the parity bits received by the parity bit generation / reception unit 13 correspond to the parity bits (not shown).
It is supplied to the check unit. In the parity check, a parity bit is generated from the received data, compared with the received parity bit, and the normality of the read data is checked.

That is, according to the configuration of FIG. 1, when data is written to a specific address of the external memory, a parity bit is written to the same address of the internal memory as that of the external memory, and the specific address of the external memory is written. When the data is read from the parity bit, the parity bit is read from the same address in the internal memory as the corresponding address in the external memory, and the normality of the read data can be checked.

According to the configuration shown in FIG. 1, even when there is no room for writing parity bits in the storage area of each address of the external memory, it is not necessary to provide an external memory for storing only parity bits.

In the above, an example has been shown in which the addresses of the external memory 2 and the internal memory 15 are the same. However, the addresses of the external memory 2 and the internal memory 15 need only correspond one-to-one, and are always the same. No need. For example, it is possible to use a part of the internal memory that is not used in the large-scale integrated circuit. In this case, generally, the addresses of the external memory 2 and the internal memory 15 do not match.

FIG. 4 shows a second embodiment of the present invention in which one data is stored in two addresses of an external memory,
This is a configuration when parity bits generated from the data are stored in the internal memory.

In FIG. 4, reference numeral 1a denotes a large-scale integrated circuit;
Is an external memory.

The large-scale integrated circuit 1a includes an address generator 11, a data generator / receiver 12, a parity bit generator / receiver 13, a timing signal generator 14, an internal memory 15, and an OR circuit 16 therein. I have.

FIG. 5 shows an external memory in the configuration of FIG.
FIG. 4 is a diagram showing mapping of an internal memory.

In this case, one data stored over two addresses of the external memory 2 is used
Since the bits are generated, the number of addresses in the internal memory 15 for storing the parity bits may be ２ of the number of addresses in the external memory.

Accordingly, while all bits of the address generated by the address generation unit 11 are supplied to the address terminal of the external memory 2, the internal memory 15 stores the address A (7-0) generated by the address generation unit 11. ), The address A (7-1) excluding the least significant bit may be supplied.

Data writing / reading is performed between the data generation / reception unit 12 and the data terminal of the external memory 2, and the parity bit generation / reception unit 13 and the internal memory 1
The writing and reading of parity bits are performed between the data terminals 5 as in the configuration of FIG.

The timing signal generator 14 supplies a chip enable signal to the chip select terminal of the external memory 2 and the non-inverting input terminal of the OR circuit 16 in common, and the write enable terminal of the external memory 2 and the internal memory A read / write control signal is commonly supplied to the 15 write enable terminals.

Then, A (0) which is the least significant bit of the address generated by the address generator 11 is supplied to the inverting input terminal of the OR circuit 16, and the output of the OR circuit 16 is output to the chip of the internal memory. It is supplied to the select terminal.

FIG. 6 is a timing chart showing the operation of the configuration of FIG. 4. FIG. 6A is a timing chart when data is written to the external memory, and FIG.
The timing when reading data from external memory
The chart is shown.

When writing data to the external memory,
First, the address on the most significant bit side of 8 bits from bit 7 to bit 0 is specified to the external memory 2 by the address generation unit 11, and the data on the most significant bit side is first transmitted from the data generation / reception unit 12 to the external memory 2. It is supplied to the parity bit generation / reception unit 13. The data supplied to the external memory 2 is written to a specified address. on the other hand,
The parity bit generation / reception unit 13 does not generate a parity bit because it has received only the most significant bit data.

Next, the address of the least significant bit of the 8 bits from bit 7 to bit 0 is designated in the external memory 2 by the address generation unit 11 and the data generation / reception unit 12
Is supplied to the external memory 2 and the parity bit generation / reception unit 13. The data supplied to the external memory 2 is written to a specified address. Then, the parity bit generation / reception unit 13 generates a parity bit after receiving all the data.

As described above, when the addresses of the most significant bit and the least significant bit are output, the external memory 2 writes the data of the most significant bit and the data of the least significant bit, respectively. Is at a logic level "L" when the addresses of the most significant bit and the least significant bit are output.

On the other hand, the writing of the parity bit to the internal memory 15 is caused by the parity bit generation /
This is when the receiving unit 13 receives all data and generates parity bits. Therefore, A (0), which is the least significant bit of the address output from the address generator 11, is supplied to the inverting input terminal of the OR circuit 16, and the chip enable signal output from the timing signal generator 14 is ORed. The internal memory 1 is supplied to the non-inverting input terminal of the circuit 16 only at the timing when the address of the least significant bit is output.
The logic level of the chip enable signal No. 5 is set to "L".

Since the different chip enable signals are supplied to the external memory 2 and the internal memory 15 as described above, the read / write control signal is set to the logic level "1" for both the external memory 2 and the internal memory 15. H ".

When data is read from the external memory, the address of the most significant bit and the address of the least significant bit of the 8 bits from bit 7 to bit 0 generated by the address generator 11 are applied to the address terminals of the external memory 2. The data is read from the specified address of the external memory 2 and supplied to the data generation / reception unit 12.

Accordingly, the logic level of the chip enable signal supplied to the external memory 2 is "L" when the address of the most significant bit and the address of the least significant bit are supplied. On the other hand, a 7-bit address from bit 7 to bit 1 is supplied to the internal memory, and the written parity bit is read. At the same timing as when the data of the least significant bit is read from the external memory 2, The logical level of the chip enable signal supplied to the internal memory 15 may be A, which is the least significant bit of the address output from the address generation unit 11 because it may be read.
By inverting (0) and performing a logical sum of the chip enable signal output from the timing signal generator 14, the logical level is set to "L" at the timing when the address of the least significant bit is output.

Since the different chip enable signals are supplied to the external memory 2 and the internal memory 15 as described above, the read / write control signal is set to the logic level "1" for both the external memory 2 and the internal memory 15. L ".

The data received by the data generation / reception unit 12 and the parity bits received by the parity bit generation / reception unit 13 correspond to the parity bits (not shown).
It is supplied to the check unit. In the parity check, a parity bit is generated from the received data, compared with the received parity bit, and the normality of the read data is checked.

That is, according to the configuration of FIG. 4, when one data is written to two addresses of the external memory, a parity bit is written to an address of the internal memory corresponding to the address of the external memory, and a parity bit is written to the external memory. When data is read from a specific address, a parity bit is read from an address of the internal memory corresponding to the address in the external memory, and the read data can be checked for normality.

According to the configuration shown in FIG. 4, even when there is no room to write the parity bit in the storage area of the address of the external memory, there is no need to provide an external memory for storing only the parity bit.

In the above description, a case where one data is written over two addresses of the external memory has been described as an example. However, one data is written over three or more addresses of the external memory.
Even when two pieces of data are written, the technique of the present invention can be applied essentially. However, in this case, the address supplied to the internal memory is obtained by removing the number of bits capable of specifying the three or more addresses from the least significant bit side of the address supplied to the external memory. The logical sum of the signal obtained by decoding the bit and the chip enable signal generated by the timing signal generator is calculated.

FIG. 7 shows a third embodiment of the present invention, in which one address of an external memory is divided and writing and reading are partially performed, and parity and data for data to be partially written and read are divided. This is a configuration in which bits are stored in a 1-bit internal memory.

In FIG. 7, reference numeral 1b denotes a large-scale integrated circuit;
Is an external memory.

The large-scale integrated circuit 1b includes an address generator 11, a data generator / receiver 12, a parity bit generator / receiver 13, a timing signal generator 14a, and an internal memory 15 therein.

FIG. 8 shows an external memory in the configuration of FIG.
FIG. 4 is a diagram showing mapping of an internal memory.

The storage area of each address of the external memory 2 having the configuration shown in FIG. 7 is divided into two, for example, and independent data is stored in the partial storage area.

On the other hand, the storage area of each address of the internal memory having the configuration shown in FIG. 7 has a 1-bit configuration, and the data partially stored in the external memory at the address corresponding to the address of the external memory in the internal memory. Is stored.

Accordingly, while the address generated by the address generator 11 is supplied to the address terminals of the external memory 2 in parallel, the internal memory 15 has the external memory in addition to the address generated by the address generator 11. 2, a bit ("U / L" in the figure, which is designated as "U / L" in the figure, and similarly in the figure, hereinafter) for specifying the upper side and the lower side of one address is supplied to the address terminal.

Data writing / reading in parallel format is performed between the data generating / receiving unit 12 and the data terminal of the external memory 2, and the parity bit is written between the parity bit generating / receiving unit 13 and the data terminal of the internal memory 15. Is performed in the same manner as described above.

The timing signal generator 14a supplies a chip enable signal to a chip select terminal and a read / write control signal to a write enable terminal, and supplies the read / write control signal to the external memory 2 in common to the external memory 2 and the internal memory 15. , A bit designating the upper side and the lower side of one address of the external memory 2.

FIG. 9 is a timing chart showing the operation of the configuration of FIG. 7. FIG. 9A is a timing chart when data is written to the external memory, and FIG.
The timing when reading data from external memory
The chart is shown. Since one address of the external memory is partially accessed, the time of accessing the upper side and the time of accessing the lower side are both described for both writing and reading.

The Up of one address of the external memory 2
The bits for specifying the per side and the lower side specify the lower side with a logical level "L" and the upper side with a logical level "H".

First, the Lo of one address of the external memory is
When writing to the lower side, the logical level of the bit designating the upper side and lower side of one address of the external memory 2 is “L”, the logical level of the chip enable signal is “L”, and the read / write control is performed. The logic level of the signal is "H". At this time, when an address is supplied from the address generation unit 11 to the external memory and data is supplied from the data generation / reception unit 12, the data is written to the lower side of the specified address in the external memory 2. At this time, the parity bit generation / reception unit 13 generates a parity bit from the data. Then, an address obtained by adding a bit “L” designating the upper side and the lower side of one address of the external memory 2 to the address output by the address generation unit 11 is supplied to the internal memory 15, so that the parity bit is Internal memory 15
Is written to.

Next, the Up of one address of the external memory is
When writing to the “per” side, the logical level of the bit designating the upper side and the lower side of one address of the external memory 2 is “H”, the logical level of the chip enable signal is “L”, and the read / write control is performed. The logic level of the signal is "H". At this time, when an address is supplied from the address generation unit 11 to the external memory and data is supplied from the data generation / reception unit 12, the data is written to the upper side of the specified address in the external memory 2. At this time, the parity bit generation / reception unit 13 generates a parity bit from the data. Then, an address obtained by adding a bit “H” designating the upper side and the lower side of one address of the external memory 2 to the address output by the address generation unit 11 is supplied to the internal memory 15, so that the parity bit is Internal memory 15
Is written to.

If the addresses in the above description are equal, the upper address of one address in the external memory 2 is
The address of the internal memory where the parity bit for the data on the side is stored is the address obtained by adding 1 to the address of the internal memory where the parity bit for the data on the lower side of one address of the external memory 2 is stored.

That is, according to the configuration of FIG. 7, when data is partially written to a specific address of the external memory, a parity bit is added to an address of the internal memory corresponding to a partial storage area of the address in the external memory. Is written, and when data is partially read from a specific address of the external memory, the parity bit is read from the address of the internal memory corresponding to the partial storage area of the address in the external memory, and the parity bit is read. The normality of the input data can be checked.

According to the configuration of FIG. 7, there is no need to provide an external memory for storing only parity bits even when there is no room to write parity bits in the storage area of each address of the external memory.

Although the example in which one address of the external memory is divided into two has been described above, the technique of the present invention can be applied to the case where one address of the external memory is divided into three or more. it can. However, in this case, the address supplied to the internal memory is the address supplied to the external memory with the least bits that can specify three or more added, and the signal of the least bits that can specify three or more is transmitted to the external memory. Also supply to memory.

FIG. 10 shows a fourth embodiment of the present invention.
The storage area of one address of the internal memory has a multi-bit configuration, and parity bits generated from data written to a specific address of the external memory store the parity bit of the internal memory.
This is a configuration in a case where data is written to one bit of an address corresponding to the address in the external memory.

In FIG. 10, 1c is a large-scale integrated circuit,
2 is an external memory.

The large-scale integrated circuit 1c includes an address generator 11, a data generator / receiver 12, a parity bit generator / receiver 13, a timing signal generator 14, an internal memory 15, and an access adjustment circuit 17 therein. I have.

FIG. 11 is a diagram showing mapping of the external memory and the internal memory in the configuration of FIG.

One data is stored in the storage area of each address of the external memory 2 having the configuration of FIG.

On the other hand, the storage area of each address of the internal memory having the configuration shown in FIG. 10 has, for example, an 8-bit configuration, and is located at a bit position of the internal memory corresponding to the address of the external memory. , A parity bit generated from data stored at the address of the external memory. Therefore, when the number of addresses of the external memory 2 is n, the number of addresses of the internal memory 15 may be n / 8.

FIG. 13 is a diagram for explaining the designation of the address of the internal memory and the parity bit in the configuration of FIG.

At the top of FIG. 13, the address generation unit 11
The 8-bit address A (7-0) generated by is indicated by a frame, and a specific address A (7-0) is displayed below the box.
Is displayed.

First, from address 0 to address 7 of the external memory, all the 5 most significant bits of address A (7-0) are 0, and the least significant bit 3 of address A (7-0) is 0. The bits change from 0 to 7.

Next, from address 8 to address 15 of the external memory, all the 5 most significant bits of address A (7-0) are 1 and the least significant bit of address A (7-0) is 1. The three bits change from 0 to 7.

Further, from address 16 to address 23 of the external memory, all the 5 most significant bits of address A (7-0) are 2 and the least significant bit of address A (7-0) is 3 The bits change from 0 to 7.

By the above setting, the parity bits generated from the data stored in the address 0 to the address 7 of the external memory 2 are stored in the address 0 of the internal memory, and the parity bit is stored in the address 8 of the external memory 2. 1
5 are stored at address 1 of the internal memory, and the parity bits generated from the data stored at addresses 23 to 23 of the external memory 2 are stored in the internal memory. What is necessary is just to store it in the address 2.

That is, the parity bit generated from the data stored at the specific address of the external memory is the parity bit of the internal memory at the address specified by the five most significant bits of the address of the external memory. May be stored at the bit position specified by the three least significant bits of the address.

Therefore, while all bits of the address output from the address generator 11 are supplied to the address terminal of the external memory 2, only the five most significant bits of the address are supplied to the internal memory 15. I just need.

Also, when writing data to a specific address in the external memory 2, the parity for the data is generated.
In order to write a bit to a specified bit position of a specified address of the internal memory 15, all parity bits once written to the address of the internal memory 15 are read, and only the parity bit at the bit position is updated to update the internal bit. It is necessary to write to the address of the memory 15.

Further, when reading data from a specific address in the external memory 2, it is necessary to read all the parity bits once written to the address in the internal memory 15 and extract only the parity bit at the bit position. is there.

Therefore, the operation of the configuration of FIG. 10 is as follows.

FIG. 12 is a timing chart showing the operation of the configuration of FIG.

First, when writing data to the external memory 2, the logic level of the chip enable signal for the external memory 2 is set to “L” and the logic level of the read / write control signal for the external memory 2 is set to “H”. To make all bits of the address output by the address generation unit 11 into the external memory 2.
, And writes the data output by the data generation / reception unit 12 to the address of the external memory 2. At the same time, a parity bit is generated from the data.

At this time, the access control circuit 17 supplies the internal memory 15 with the five most significant bits of the address output from the address generator 11. Then, the access adjustment circuit 17 sets the logic level of the chip enable signal for the internal memory 15 to “L” and the logic level of the read / write control signal for the internal memory 15 to “L”, and All the parity bits stored in the address are once read, and the parity bit at the position specified by the three least significant bits of the address output by the address generation unit 11 is updated to the generated parity bit. . Next, the access adjustment circuit 17 sets the logic level of the chip enable signal for the internal memory 15 to "L" again, and sets the logic level of the read / write control signal for the internal memory 15 to "H", and the access control circuit 17 is updated. Write all the parity bits to the internal address.

Next, when reading data from the external memory 2, the logic level of the chip enable signal is set to "L",
The logical level of the read / write control signal is set to “L”,
All bits of the address output by the address generation unit 11 are supplied to the external memory 2 and data stored at the address is read.

On the other hand, the access adjustment circuit 17 supplies the internal memory 15 with the five most significant bits of the address output from the address generation unit 11, and sets the logic level of the internal chip enable signal to "L". The logical level of the internal read / write control signal is set to “L”, and all the parity bits stored in the internal address are read. Then, the access adjustment circuit 17 extracts the parity bit at the bit position specified by the three least significant bits of the address output by the address generation unit 11 from the read parity bits, and
The data is transferred to the bit generation / reception unit 13.

That is, according to the configuration of FIG. 10, when data is written to a specific address of the external memory, a parity bit is set at a bit position of the internal memory corresponding to the address of the external memory. When data is written to and read from a specific address in the external memory, the parity bit is read from the bit position in the internal memory corresponding to the address in the address corresponding to the address in the external memory, and is read. The normality of data can be checked.

According to the configuration shown in FIG. 10, there is no need to provide an external memory for storing only parity bits even when there is no room for writing parity bits in the storage area of each address of the external memory.

In the above description, an example in which eight parity bits are stored at one address of the internal memory has been described.
Even if the number of parity bits stored in one address of the internal memory is other than eight, the technique of the present invention can be applied. In this case, the internal memory is supplied with an address obtained by removing the minimum number of bits capable of specifying the bit position of the parity bit stored in one address of the internal memory from the least significant bit of the address supplied to the external memory. The bit position in one address of the internal memory is designated by the bits excluding the above.

FIG. 14 shows a fifth embodiment of the present invention.
This is a configuration in which one data is written over two addresses of the external memory, and a parity bit generated from the same bit of the two addresses is written to the same bit of the corresponding address of the internal memory.

In FIG. 14, 1a is a large-scale integrated circuit,
2 is an external memory.

The large-scale integrated circuit 1a includes an address generation unit 11, a data generation / reception unit 12, a parity bit generation / reception unit 13a, a timing signal generation unit 14, an internal memory 15a, and an OR circuit 16 therein. I have.

FIG. 15 is a diagram showing mapping of the external memory and the internal memory in the configuration of FIG.

In this case, a parity bit is generated from the same bit of one data stored over two addresses of the external memory 2 and stored in the same bit of the internal memory 15 at the address corresponding to the address. , The number of addresses in the internal memory may be の of the number of addresses in the external memory.

Accordingly, while all bits of the address generated by the address generator 11 are supplied to the address terminals of the external memory 2 in parallel, the internal memory 15 stores the address A ( 7-0)
The address A (7-1) excluding the least significant bit may be supplied.

Data writing / reading in parallel format is performed between the data generation / reception unit 12 and the data terminal of the external memory 2, and the parity bit is written between the parity bit generation / reception unit 13 and the data terminal of the internal memory 15. Is performed in the same manner as in the configuration of FIG.

The timing signal generator 14 supplies a chip enable signal to the chip select terminal of the external memory 2 and the non-inverting input terminal of the OR circuit 16 in common, and the write enable terminal of the external memory 2 and the internal memory A read / write control signal is commonly supplied to the 15 write enable terminals.

A (0), which is the least significant bit of the address generated by the address generator 11, is supplied to the inverting input terminal of the OR circuit 16, and the output of the OR circuit 16 is output to the chip of the internal memory. It is supplied to the select terminal.

FIG. 16 is a timing chart showing the operation of the configuration shown in FIG. 14. FIG. 16A is a timing chart when data is written to the external memory.
FIG. 6B shows a timing chart when data is read from the external memory.

At the time of writing, first, the address of the most significant bit of the 8 bits from bit 7 to bit 0 is specified to the external memory 2 by the address generation unit 11, and the data generation / reception unit 12 first specifies the address of the most significant bit. Data is supplied to the external memory 2 and the parity bit generation / reception unit 13. The data supplied to the external memory 2 is written to a specified address. On the other hand, parity bit generation /
The receiving unit 13 does not generate a parity bit at this timing because only the most significant bit data is received.

Next, the address on the least significant bit side of the 8 bits from bit 7 to bit 0 is designated in the external memory 2 by the address generation unit 11, and the data generation / reception unit 12
Is supplied to the external memory 2 and the parity bit generation / reception unit 13. The data supplied to the external memory 2 is written to a specified address. Then, the parity bit generation / reception unit 13 generates a parity bit after receiving all data.

As described above, when the addresses of the most significant bit and the least significant bit are output, the external memory 2 writes the data of the most significant bit and the data of the least significant bit, respectively. Is at a logic level "L" when the addresses of the most significant bit and the least significant bit are output.

On the other hand, the writing of the parity bit to the internal memory 15 is based on the parity bit generation /
This is when the receiving unit 13 receives all data and generates parity bits. Therefore, A (0), which is the least significant bit of the address output from the address generator 11, is supplied to the inverting input terminal of the OR circuit 16, and the chip enable signal output from the timing signal generator 14 is ORed. The internal memory 1 is supplied to the non-inverting input terminal of the circuit 16 only at the timing when the address of the least significant bit is output.
The logic level of the chip enable signal No. 5 is set to "L".

Since the different chip enable signals are supplied to the external memory 2 and the internal memory 15 as described above, the read / write control signal is set to the logic level "1" for both the external memory 2 and the internal memory 15. H ".

At the time of reading, the address of the most significant bit and the address of the least significant bit of the 8 bits from bit 7 to bit 0 generated by the address generator 11 are supplied to the address terminal of the external memory 2. Is read from the designated address and supplied to the data generation / reception unit 12.

Therefore, the logic level of the chip enable signal supplied to the external memory 2 is "L" when the address of the most significant bit and the address of the least significant bit are supplied. On the other hand, a 7-bit address from bit 7 to bit 1 is supplied to the internal memory, and the written parity bit is read. At the same timing as when the data of the least significant bit is read from the external memory 2, The logical level of the chip enable signal supplied to the internal memory 15 may be A, which is the least significant bit of the address output from the address generation unit 11 because it may be read.
By inverting (0) and performing a logical sum of the chip enable signal output from the timing signal generator 14, the logical level is set to "L" at the timing when the address of the least significant bit is output.

Since the different chip enable signals are supplied to the external memory 2 and the internal memory 15 as described above, the read / write control signal is set to the logic level "for both the external memory 2 and the internal memory 15". L ".

The data received by the data generation / reception unit 12 and the parity bits received by the parity bit generation / reception unit 13 correspond to the parity bits (not shown).
It is supplied to the check unit. In the parity check, a parity bit is generated from the received data, compared with the received parity bit, and the normality of the read data is checked.

That is, according to the configuration of FIG. 14, when one data is written to two addresses of the external memory, the parity and the parity are stored in the bit position of the internal memory corresponding to the address of the external memory.
When a bit is written and data is read from a specific address in the external memory, the parity bit is read from the bit position in the internal memory corresponding to the bit in the address corresponding to the address in the external memory, and read. The normality of the input data can be checked.

According to the configuration of FIG. 14, even when there is no room to write the parity bits in the storage area of the address of the external memory, it is not necessary to provide an external memory for storing only the parity bits.

In the above description, an example is described in which eight bits of parity bits generated from the same bit of data stored over two addresses of the external memory are stored at one address of the internal memory. The technique of the present invention can be applied to a case where parity bits generated from the same bit of data stored over three or more addresses are stored in one address of the internal memory in a different number of bits from eight bits. it can. In this case, the second embodiment of the present invention and the one added at the end of the description of the fourth embodiment of the present invention may be combined with each other, and thus the detailed description is omitted.

[0137]

According to the first aspect of the present invention, a parity bit generated from data to be written to an external memory is
Since the data is written to the same address of the external memory where the data is written in the internal memory, if the parity bit is read from the same address of the internal memory as the external memory when reading the data, the data read from the external memory can be read. Can be checked for normality.

According to the second means of the present invention, the parity bits generated from the data to be written over a plurality of addresses of the external memory are written to the internal memory at addresses corresponding to the plurality of addresses of the external memory. When data is read from the external memory, the normality of the data read from the external memory can be checked by reading the parity bits from addresses of the internal memory corresponding to a plurality of addresses of the external memory.

According to the third means of the present invention, the parity bits generated from the data to be written to the partial storage area of the external memory correspond to the partial storage area of the external memory of the internal memory. Since the data is read from the external memory, when the data is read from the external memory, the parity bit written at the address of the internal memory corresponding to the partial storage area of the external memory is read. The health can be checked.

According to the fourth aspect of the present invention, when data is read from the external memory, all the parity bits are temporarily read from the address corresponding to the address in the external memory, and the bit corresponding to the address in the external memory is read. By extracting only the parity bit written at the position, the normality of the data read from the external memory can be checked.

According to the fifth means of the present invention, when data is read from the external memory, if all parity bits are read from the internal memory at addresses corresponding to a plurality of addresses of the external memory, the data is read from the external memory. Data can be checked for normality.

[Brief description of the drawings]

FIG. 1 shows a first embodiment of the present invention.

FIG. 2 is a mapping of an external memory and an internal memory in the configuration of FIG. 1;

FIG. 3 is a timing chart showing the operation of the configuration of FIG.

FIG. 4 shows a second embodiment of the present invention.

FIG. 5 is a mapping of an external memory and an internal memory in the configuration of FIG. 4;

FIG. 6 is a timing chart showing the operation of the configuration of FIG. 4;

FIG. 7 shows a third embodiment of the present invention.

FIG. 8 is a mapping of an external memory and an internal memory in the configuration of FIG. 7;

9 is a timing chart showing the operation of the configuration of FIG.

FIG. 10 shows a fourth embodiment of the present invention.

FIG. 11 is a mapping of an external memory and an internal memory in the configuration of FIG. 10;

12 is a timing chart showing the operation of the configuration of FIG.

13 is a view for explaining designation of an address of an internal memory and a parity bit in the configuration of FIG. 10;

FIG. 14 shows a fifth embodiment of the present invention.

FIG. 15 is a mapping of an external memory and an internal memory in the configuration of FIG. 14;

16 is a timing chart showing the operation of the configuration of FIG.

FIG. 17 shows a conventional external memory failure detection method.

FIG. 18 shows mapping of an external memory in the configuration of FIG. 17;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Large-scale integrated circuit 1a Large-scale integrated circuit 1b Large-scale integrated circuit 1c Large-scale integrated circuit 1d Large-scale integrated circuit 2 External memory 11 Address generation part 12 Data generation / reception part 13 Parity bit generation / reception part 14 Timing signal generation Unit 14a timing signal generation unit 15 internal memory 15a internal memory 16 OR circuit 17 access adjustment circuit

Claims (5)

[Claims] 1. A storage area for storing parity bits, that is, an internal memory is secured inside a large-scale integrated circuit, and when writing data to a specific address of an external memory,
A failure detection method for an external memory, comprising: generating a parity bit from the data; and writing the parity bit to an address of the internal memory determined from the address of the external memory. 2. A storage area for storing parity bits, that is, an internal memory, is secured in a large-scale integrated circuit. When data is written to a plurality of specific addresses of an external memory, when all the data over a plurality of addresses are written. A failure detection method for an external memory, comprising: generating a parity bit from the data; and writing the parity bit to an address of the internal memory determined from a plurality of addresses of the external memory. 3. A storage area for storing parity bits, that is, an internal memory, is secured inside a large-scale integrated circuit, and when data is written to a partial storage area of a specific address of an external memory, the partial storage is performed. Generating a parity bit from data to be written to the area, and writing the parity bit to the internal memory at an address determined by the address of the external memory and the position of the partial storage area. External memory failure detection method. 4. A multi-bit storage area for storing parity bits inside a large-scale integrated circuit, that is, an internal memory is secured, and when data is written to a specific address of an external memory,
Generating a parity bit from the data, once reading all parity bits from an address of the internal memory determined from the address of the external memory, and writing the parity bit to a bit position of the external memory determined by the address A failure detection method for an external memory, characterized in that only the parity bit that has been updated is updated and written to the address of the internal memory. 5. A multi-bit storage area for storing parity bits in a large-scale integrated circuit, that is, an internal memory is secured, and when one data is written to a plurality of specific addresses of an external memory, a plurality of the data are stored. Detecting a plurality of parity bits from the same bit of the address of the external memory, and writing the plurality of parity bits to an address of the internal memory determined from the address of the external memory. method.