JP2001197747A - Ac voltage detection circuit and method, charging circuit and method, chopper charging circuit and method, and electronics and clocking device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To detect power generating conditions at an early stage. SOLUTION: Sub capacitors C1, C2 are selected by a sub capacitor selecting part 7. When an AC power generator AG with the selected sub capacitor C2 generates electromotive voltage so that the potential of an output terminal AG1 may exceed that of the output terminal AG2, a diode d1 is ON and electric charges are stored in the sub capacitor C2. When electromotive voltage is generated on the side of the output terminal AG1, the voltage of the output terminal AG1 becomes the sum of the voltage of the sub capacitor C2 and that between the output terminals AG1, AG2, so that the electromotive voltage is doubled. A power generation detecting part 10 detects the generating conditions based on the doubled voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an AC voltage detecting circuit and method suitable for detecting whether or not an AC voltage having a predetermined amplitude or more is induced in an inductance element connected between input terminals. The present invention relates to a charging circuit and method, a chopper charging circuit and method, an electronic device, and a timing device.

[0002]

2. Description of the Related Art A bridge-type charging circuit is known as a charging circuit for charging an AC voltage generated by a generator to a capacitor or a battery. FIG. 15 is a circuit diagram of a conventional charging circuit. In this charging circuit, the generator AG
COM1, COM2 for comparing the voltage of the output terminals A and B with the voltage of the power supply Vdd, and the output terminals A and B of the generator AG
Comparator COM that compares the voltage of
3, COM4, and a large-capacity capacitor C for storing a charging current are provided. And each comparator CO
The P-channel FETs P1, P2, N1,
ON / OFF of N2 is controlled.

[0003] Here, the voltage of the output terminal A is equal to the ground GND.
When the voltage becomes equal to or less than the voltage of the output terminal AG, the N-channel FET N1 is turned on by the comparator COM3.
1 is grounded. When the voltage of the output terminal B exceeds the voltage of the power supply Vdd, the P-channel FET P2 is turned on by the comparator COM2. In this case, as long as the voltage of the output terminal B does not exceed the voltage of the power supply Vdd, the P-channel FE
Since TP2 is not turned on, current does not flow in the reverse direction of the arrow, and the disadvantage that the capacitor C is discharged does not occur.

Thus, in the conventional charging circuit,
Combining field effect transistors and comparators,
A unidirectional unit that allows a current to flow in one direction under a certain condition is configured so that an AC voltage can be charged efficiently.

In this charging circuit, there is a problem that the electric energy stored in the capacitor C is consumed by the comparator even during the period when the generator AG does not generate power, and the charging efficiency is reduced.

[0006]

The comparator is composed of a field effect transistor, but its transition frequency becomes lower as the current consumption becomes smaller. The operation speed of the comparator is determined according to the transition frequency of the field effect transistor used therein, and the lower the transition frequency, the lower the operation speed. As described above, since it is necessary to use a low-current-consumption type comparator for the power generation detection, even if an electromotive voltage exceeding a certain level is input to the comparator between the output terminals A and B, immediately, Power generation cannot be detected.

Here, it is conceivable to detect the power generation early by lowering the threshold voltage input to the power generation detection comparator. However, when the threshold voltage is lowered, the alternator AG
Malfunctions when noise is induced in the output coil. For this reason, there is a limit in lowering the threshold voltage. This will be specifically described. FIG. 16 shows the relationship between the electromotive voltage VG generated between the output terminals A and B and the threshold voltage VD. In this example, the threshold voltage VG is set so as not to malfunction due to the noise N.
For this reason, there is a problem that the power generation state cannot be detected during the period from time t0 to time t1, even though the electromotive voltage is generated.

Further, in such a chopper type charging circuit, when the electromotive voltage generated between the output terminals A and B is extremely small, the energy stored in the inductance of the output coil is small, so that the conversion into the chopper voltage is performed. Even if the voltage does not rise above the terminal voltage Vdd of the capacitor C, the capacitor C is consumed by the internal resistance of the output coil without charging the capacitor C. Also, output terminals A,
Even if the electromotive voltage generated between B is large, if charging is started and the chopper voltage becomes equal to or lower than the terminal voltage Vdd of the capacitor C, the capacitor C is consumed by the internal resistance of the output coil without being charged. Becomes
It is considered that if the energy stored in the inductance consumed by the internal resistance of the output coil or the like can be charged into the capacitor C, the charging efficiency of the chopper type charging circuit can be further increased.

The present invention has been made in view of the above-described circumstances, and can improve the charging efficiency. In addition, an AC voltage having a predetermined amplitude or more is induced in an inductance element connected between input terminals. It is an object of the present invention to provide an AC voltage detection circuit capable of detecting whether or not the detection has been performed at an early stage, a charging circuit to which the AC voltage detection circuit is applied, a chopper charging circuit, an electronic device, and a timing device.

[0010]

In order to solve the above problems, an AC voltage detecting circuit according to the present invention comprises a first input terminal and a second input terminal.
A first capacitive element connected to the first input terminal, for detecting whether an AC voltage having a predetermined amplitude or more is induced in the inductance element connected to the input terminal; A second capacitive element connected to the second input terminal, and a capacitive element connected to one of the first or second input terminals when an induction of an AC voltage is started in the inductance element. A charging unit that cuts off a charging path including a capacitive element connected to the other input terminal while forming a charging path including the first and second input terminals, and compares each voltage of the first input terminal and the second input terminal with a reference voltage; Detecting means for detecting that an AC voltage is induced in the inductance element according to the comparison result.

According to the present invention, when an AC voltage is generated in the inductance element, a charge is charged in the capacitance element connected to one input terminal. And the phase of the AC voltage is 1
When the voltage at the other input terminal becomes higher than the voltage at one input terminal by advancing by 80 degrees, the voltage at the other input terminal becomes an AC voltage and a voltage charged in the capacitor. Therefore, the voltage of the other input terminal is doubled. For this reason,
The detection unit can perform detection based on the doubled voltage. In this case, even if noise is induced in the inductance element, since the noise is integrated by the capacitance element, the noise hardly causes the detection unit to malfunction.

Further, the AC voltage detecting circuit according to the present invention comprises:
Detecting whether an AC voltage having a predetermined amplitude or more is induced in an inductance element connected between the input terminal and the second input terminal, wherein the connection is made between the first input terminal and a line; A first diode, a first capacitive element and a first switching element connected between the first input terminal and the line, a second diode connected between the second input terminal and the line, The second capacitive element and the second switching element connected between the second input terminal and the line, and the period in which the continuous AC voltage is induced in the inductance element, are the first or the second.
While controlling so that one of the switching elements is turned on and the other is turned off, the first and second switching elements are controlled.
A control unit that controls a switching element connected between the input terminal having a lower terminal voltage and the line immediately before the end of the period among the input terminals to be turned on after the end of the period,
A detecting unit that compares each voltage of the first input terminal and the second input terminal with a reference voltage, and detects that an AC voltage having a predetermined amplitude or more is induced in the inductance element according to the comparison result; It is characterized by having.

Here, the above-mentioned AC power generation detection circuit may be configured to detect a charge of an element of the first or second capacitance element that is being charged when the detection section detects that an AC voltage is induced. It is preferable to include a discharge unit for discharging.

In addition, the discharging unit includes a third switching element connected between the first input terminal and the line, and a fourth switching element connected between the second input terminal and the line.
A switching element, and when the detecting unit detects that an AC voltage having a predetermined amplitude or more is induced, the switching unit corresponds to an element that is turned on among the first or second switching elements. The third or fourth switching element may be turned on.

Next, the charging circuit according to the present invention rectifies the AC voltage induced in the inductance element connected between the first input terminal and the second input terminal, and rectifies the AC voltage induced in the first line and the second line. A first switching element connected between the first line and the first input terminal; and a first switching element connected between the first line and the second input terminal. A second switching element, and a third switching element connected in parallel between the second line and the first input terminal.
A switching element and a first diode; a fourth switching element and a second diode connected in parallel between the second line and the second input terminal; and a serial connection between the second line and the first input terminal. A fifth switching element and a first auxiliary capacitance element, a sixth switching element and a second auxiliary capacitance element connected in series between the second line and the second input terminal, and the first and second storage elements.
A first control unit that controls on / off of the first to fourth switching elements based on each potential of a line and each potential of the first and second input terminals; and the first and second inputs. Comparing each voltage between the terminal and the second line with a reference voltage, and detecting that an AC voltage having a predetermined amplitude or more is induced in the inductance element according to the comparison result, the first control unit A power supply unit for supplying power, and the fifth or sixth switching element corresponding to the input terminal having a lower terminal voltage immediately before the end of the period in which the continuous AC voltage is induced in the inductance element, after the end of the period. And a second control unit for turning on.

[0016] The charging circuit may be configured to charge the element of the first or second capacitive element that is charged at a point in time when it is detected that an AC voltage having a predetermined amplitude or more is induced by the power supply unit. It is preferable to include a discharge unit for discharging the electric power.

Further, the discharging unit is an element which is turned on among the fifth or sixth switching element at the time when it is detected that an AC voltage having a predetermined amplitude or more is induced by the power supply unit. It is preferable to turn on the third or fourth switching element corresponding to.

Next, the chopper-type charging circuit of the present invention performs chopper boosting of an AC voltage induced in an inductance element connected between the first input terminal and the second input terminal in synchronization with a clock signal. Charging a capacitive element connected between a first line and a second line, wherein the first switching element is connected between the first line and the first input terminal; A first control unit that compares the potential of the first input terminal and controls on / off of the first switching element based on the comparison result; and a first control unit that is connected between the first line and the second input terminal. A second switching element, a second controller for comparing the potential of the first line with the potential of the second input terminal, and controlling on / off of the second switching element based on a comparison result;
A third switching element and a first diode connected in parallel between a line and the first input terminal, a potential of the second line and a potential of the first input terminal are compared, and based on a comparison result, the third A third control unit for turning on / off the three switching elements in synchronization with the clock signal; and a fourth control unit connected in parallel between the second line and the second input terminal.
A switching element and a second diode, comparing a potential of the second line with a potential of the second input terminal, and turning on / off the fourth switching element in synchronization with the clock signal based on a comparison result. A fourth control unit, a fifth switching element and a first auxiliary capacitance element connected in series between the second line and the first input terminal, and a serial connection between the second line and the second input terminal. The sixth
A switching element and a second auxiliary capacitance element;
And a detection unit for comparing each voltage between the second input terminal and the second line with a reference voltage, and detecting that an AC voltage having a predetermined amplitude or more is induced in the inductance element according to the comparison result. A power supply unit for supplying power to the first to fourth control units after detecting that an AC voltage having a predetermined amplitude or more is induced by the detection unit; and an AC voltage continuous to the inductance element. And an auxiliary capacitance element selecting unit that turns on the fifth or sixth switching element corresponding to the input terminal having the lower terminal voltage immediately after the end of the period in which the voltage is induced. .

This chopper charging circuit is an element which is charged when the detecting section detects that an AC voltage having a predetermined amplitude or more is induced, of the first or second auxiliary capacitance element. It is preferable to include a discharge unit for discharging the electric charges of the above.

Here, the discharging unit is turned on of the fifth or sixth switching element at the time when the detecting unit detects that an AC voltage having a predetermined amplitude or more is induced. It is desirable that the element be turned on and off in synchronization with the on and off of the third or fourth switching element corresponding to the element.

Further, the above-mentioned chopper charging circuit is charged in the first or second auxiliary capacitance element when the detecting section detects that an AC voltage having a predetermined amplitude or more is induced. It is desirable to have a transfer means for transferring charges to the capacitor.

Here, the transfer means includes a seventh switching element connected between the first line and the first input terminal, and an eighth switching element connected between the first line and the second input terminal. The seventh and eighth switching elements are simultaneously turned on and off for a certain period after the detection unit detects that an AC voltage having a predetermined amplitude or more is induced, and One of the fifth or sixth switching element corresponding to the second capacitor element having no charge stored therein is turned off, and the other switching element is turned on complementarily with the seventh and eighth switching elements. -It is preferable to turn off. More specifically, during the certain period, the other switching element is turned off when the seventh and eighth switching elements are on, and turned on when the seventh and eighth switching elements are off. Just do it.

In addition, the power supply of the chopper charging circuit is
After supplying power to the third and fourth control units, the first
Preferably, power supply to the second control unit is started. Here, after the power supply unit supplies power to the third and fourth control units, on / off control of the third or fourth switching element is started by the third or fourth control unit. Is detected, it is desirable to start power supply to the first and second control units.

In the chopper charging circuit, the first line may be a power supply line, and the second line may be ground, or conversely, the first line may be ground.

In the chopper charging circuit, the current consumption of the detection unit is lower than the current consumption of the third and fourth control units, and the current consumption of the third and fourth control units is reduced by the first and second control units. It is preferable to set lower than the current consumption of the control unit.

Next, an electronic apparatus according to the present invention is characterized in that the above-mentioned chopper charging circuit is built in and operates with electric power supplied from the chopper charging circuit. Next, a timing device of the present invention includes the above-described chopper charging circuit, and a clock circuit that is supplied with power from the chopper charging circuit and measures time. next,
According to the AC voltage detection method of the present invention, the amplitude of the inductance element inserted between the first input terminal to which the first capacitance element is connected and the second input terminal to which the second capacitance element is connected is equal to or greater than a predetermined amplitude. It is premised that whether the AC voltage is induced is detected or not. When the induction of the AC voltage is started in the inductance element, a capacitance connected to one of the first or second input terminals is detected. While forming a charging path including the element, the charging path including the capacitive element connected to the other input terminal is cut off, and each voltage of the first input terminal and the second input terminal is compared with a reference voltage. It is characterized by detecting that an AC voltage is induced in the inductance element according to a result. Next, the AC voltage detecting method according to the present invention includes a first diode connected between the first input terminal and the line, a first capacitor element and a first switching element connected between the first input terminal and the line. A second diode connected between a second input terminal and the line, and a detection circuit including a second capacitance element and a second switching element connected between the second input terminal and the line, Assuming that it is detected whether or not an AC voltage having a predetermined amplitude or more is induced in the inductance element connected between the first input terminal and the second input terminal, a continuous AC voltage is applied to the inductance element. During the period in which the voltage is induced, one of the first and second switching elements is turned on and the other is turned off, and the first and second input terminals are turned off immediately before the end of the period. A switching element connected between the input terminal of the lower voltage line is turned on after completion of the period, the first
Each voltage of the input terminal and the second input terminal is compared with a reference voltage, and it is detected that an AC voltage having a predetermined amplitude or more is induced in the inductance element according to the comparison result. Next, the charging method of the present invention includes:
A first switching element connected between a first line and a first input terminal, a second switching element connected between the first line and a second input terminal, and a second switching element connected between the second line and the first input terminal; A third switching element and a first diode connected in parallel to the second line, a fourth switching element and a second diode connected in parallel between the second line and the second input terminal, and the second line and the first diode. A fifth switching element and a first auxiliary capacitance element connected in series between one input terminal; a sixth switching element and a second storage element connected in series between the second line and the second input terminal;
An AC voltage induced in an inductance element connected between the first input terminal and the second input terminal is rectified using a charging circuit including an auxiliary capacitance element, and
Assuming that a capacitive element connected between a line and the second line is charged, each voltage between the first and second input terminals and the second line is compared with a reference voltage, and according to the comparison result, It is detected that an AC voltage having a predetermined amplitude or more is induced in the inductance element. After this detection, each potential of the first and second lines and each potential of the first and second input terminals are detected. On / off of the first to fourth switching elements based on the above, and the terminal voltage corresponding to the input terminal having the lower terminal voltage immediately before the end of the period in which the continuous AC voltage is induced in the inductance element. The fifth or sixth switching element is turned on after the end of the period. Next, in the chopper charging method according to the present invention, a first switching element connected between a first line and a first input terminal is compared with a potential of the first line and a potential of the first input terminal. A first control unit that controls on / off of the first switching element based on the first switching element, a second switching element connected between the first line and a second input terminal, and a potential of the first line and the second switching element. A second control unit that compares the potentials of the two input terminals and controls on / off of the second switching element based on the comparison result; and a second control unit that is connected in parallel between the second line and the first input terminal. The third switching element and the first diode are compared with the potential of the second line and the potential of the first input terminal, and based on the comparison result, the third switching element is turned on / off in synchronization with the clock signal. No.
A control unit, a fourth switching element and a second diode connected in parallel between the second line and the second input terminal, and comparing the potential of the second line with the potential of the second input terminal; A fourth control unit for turning on / off the fourth switching element in synchronization with the clock signal based on the result; a fifth switching element connected in series between the second line and the first input terminal; The first input terminal using a chopper charging circuit including a first auxiliary capacitance element, a sixth switching element connected in series between the second line and the second input terminal, and a second auxiliary capacitance element; An AC voltage induced in an inductance element connected between the first line and the second input terminal is chopper-boosted in synchronization with the clock signal, and is connected between the first line and the second line. Assuming that a capacitive element is charged, each voltage between the first and second input terminals and the second line is compared with a reference voltage, and an amplitude equal to or more than a predetermined amplitude is determined for the inductance element according to the comparison result. After detecting that an AC voltage has been induced, and after detecting that an AC voltage having a predetermined amplitude or more has been induced, the detection unit supplies power to the first to fourth control units. The fifth or sixth switching element corresponding to the input terminal having the lower terminal voltage is turned on immediately after the end of the period in which the continuous AC voltage is induced in the inductance element immediately before the end of the period.

[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a wristwatch to which a chopper type charging circuit is applied will be described as an embodiment of the present invention.

<1. First Embodiment><1-1: Configuration of First Embodiment> FIG. 1 is a circuit diagram of a chopper-type charging circuit used in a wristwatch according to the present embodiment. The chopper type charging circuit 100 includes an AC generator AG
, A chopper circuit 20 for converting the electromotive voltage of the AC generator AG into a pulse-like chopper voltage, and a main capacitor 30 for charging the chopper voltage obtained by the chopper circuit 20 Approximately. Here, the main capacitor 30 is connected between the high potential side line LH and the low potential side line LL. In the following description, the voltage of the high potential side line LH based on the low potential side line LL is referred to as Vdd. In FIG. 1, reference symbol L denotes an output coil of the AC generator AG, and output terminals AG1 and AG2 are connected to respective input terminals of the chopper type charging circuit 100.

<1-1-1: Power Generation Detection Unit> First, the power generation detection unit 10 will be described. The power generation detection unit 10 compares the voltages of the output terminals AG1 and AG2 of the AC generator AG with a predetermined threshold, and when the voltage exceeds the threshold, the AC generator A
G is determined to be in the power generation state, and is configured by, for example, the circuit shown in FIG.

In FIG. 2, a positive input terminal of a comparator COM5 grounded via a resistor R1 is connected to an output terminal AG1, and a negative input terminal of the comparator COM5 has a reference voltage Vref.
Is supplied. On the other hand, the positive input terminal of the comparator COM6, which is grounded via the resistor R2, is connected to the output terminal AG2, and its negative input terminal is supplied with the reference voltage Vref. In addition, the reference voltage Vref is
The voltage is set to exceed the voltage of the ground GND so that it is possible to detect whether or not G is in a power generation state.

Therefore, when one of the output signals of the comparators COM5 and COM6 becomes high level, it is possible to detect that the power is being generated. For this reason, the OR circuit 11 calculates the logical sum of the two signals and outputs the logical sum to the AC generator AG.
Is output as a signal φAG indicating whether or not is in a power generation state. One input terminal of the NOR circuit 13 has a signal φS generated by an SR latch circuit 6 (see FIG. 1) described later.
Is supplied via an inverting circuit 12, and an output signal φAG of the OR circuit 11 is supplied to the other input terminal. The NOR circuit 13 generates a signal φSL based on these signals.

The signal φSL is supplied to an AG2 detection unit 3 described later.
And when the signal φSL indicates the power generation state (low level), the AG2 detection unit 3 and the AG1 detection unit 4 operate.
It detects whether the voltage of each output terminal AG1, AG2 of the output coil L exceeds a predetermined level. When it is detected that an electromotive voltage exceeding a predetermined level is generated, a portion composed of the NOR circuit NOR3, the timer counter 5, and the SR latch circuit 6 of the chopper circuit 20 is operated until a certain time elapses from the detection. , Activate the signal φS.

Thus, the Vdd detectors 1 and 2 operate, and the main capacitor 30 can be charged.
That is, power supply to each part of the chopper-type charging circuit 100 is sequentially performed with the detection of the power generation state in the power generation detection unit 10 as an opportunity. Accordingly, the shorter the time from when an electromotive voltage is generated between the output terminals AG1 and AG2 of the AC generator AG until the signal φSL is activated, the more effectively the generated electromotive voltage can be used.

<1-1-2: Chopper Circuit> Next, as shown in FIG. 1, the main part of the chopper circuit 20 is that the P-channel FETs P1 and P2 are connected to the output terminals AG1 and AG2 and the high potential side line LH. Are connected to each other between the N-channel FE
TN1 and N2 have a bridge type configuration connected between the output terminals AG1 and AG2 and the low potential side line LL. In this chopper circuit 20, an N-channel FET N
1. N2 is operated as a chopper, and the electromotive voltage of the AC generator AG induced in the output coil L is boosted by the chopper to charge the main capacitor 30.

The output terminal AG1 and the low potential side line L
A diode d1 is inserted between L and L,
The sub-capacitor C1 and the N-channel FET N1 'are connected in series. On the other hand, a diode d2 is connected in parallel between the output terminal AG2 and the low potential side line LL, and the sub-capacitor C2 and the N-channel FET N
2 'are connected in series. Although the diodes d1 and d2 are provided in this example, when the chopper circuit 20 is configured as an integrated circuit, a parasitic diode associated with the N-channel FETs N1 and N2 may be used as the diodes d1 and d2.

Here, the function of the sub-capacitors C1 and C2 will be described with reference to FIGS. FIG.
FIG. 4 is a circuit diagram showing an equivalent circuit of the sub-capacitor C2 and its peripheral configuration when the channel FET N2 'is turned on and the N-channel FET N1' is turned off. FIG. 6 is a timing chart showing a voltage of a terminal AG2.

An electromotive voltage is induced in the output coil L, and FIG.
As shown in (2), if a positive electromotive voltage is generated on the AG2 side from time t1, the sub capacitor C2 is charged by this electromotive voltage. At this time, the diode d1 is turned on, a closed loop is formed in the path of AG2 → C2 → d1 → AG1, and the charging current flows into the sub-capacitor C2. For this reason, the electromotive voltage with the positive electrode on the AG2 side becomes equal to the time t2
After the maximum is reached, the charge charged in the sub-capacitor C2 is not discharged even if it gradually decreases. Therefore, the voltage of the output terminal AG2 does not decrease even after the time t2.

On the other hand, when a positive electromotive voltage is generated on the AG1 side from time t3, the diode d1 is turned off. The voltage at the output terminal AG1 is the sum of the electromotive voltage induced at both ends of the output coil L and the voltage of the sub-capacitor C2. Therefore, after time t3, the voltage at output terminal AG1 is the sum of voltage Vg2 at output terminal AG1 at time t3 and the electromotive voltage, and is boosted as shown in the figure. In other words, the electromotive voltage can be doubled by the diode d1 and the sub-capacitor C2.

Therefore, the above-described power generation detecting section 10 can perform power generation detection based on the electromotive voltage doubled. Therefore, for example, if the reference voltage Vref of the power generation detection unit 10 is set as V1 shown in FIG. 4, the signal φSL is activated after the response time td of the power generation detection unit 10 has elapsed from time t4. can do. On the other hand, if the sub-capacitors C1 and C2 are not provided, the power generation detecting unit 10 detects the power generation state only when the electromotive voltage exceeds V1 after a lapse of time. In other words, the power generation state can be quickly detected by boosting the electromotive voltage twice. As a result,
Conventionally, it is possible to operate the chopper circuit 20 and increase the charging efficiency during a period in which charging is not possible despite generation of an effective electromotive voltage.

FIG. 5 shows a circuit diagram of the Vdd detectors 1 and 2. In FIG. 5, the reference numerals shown in parentheses are V
This corresponds to the dd detection unit 2, and the code outside the parentheses is Vdd
This corresponds to the detection unit 1. As shown in this figure,
The Vdd detection unit 1 (2) includes a comparator COM1 (COM2), switches S1 (S3), and S2 (S4). The positive input terminal of the comparator COM1 (COM2) is connected to the high potential side line LH, and the negative input terminal is connected to the output terminal AG1 (AG2) of the AC generator AG. For this reason,
When the switch S1 (S3) is off and the switch S2 (S4) is on, the power supply voltage Vdd is applied to the output terminal AG1.
When the voltage exceeds (AG2), the signal φP1 (φP2) goes low, and the P-channel FET P1 (P2) turns on. On the other hand, when the power supply voltage Vdd falls below the voltage of the output terminal AG1, the signal φP1 (φP2) goes high and the P-channel FET P1 (P2) turns off. Therefore, the P-channel FET P1 (P2) outputs current only when the voltage of the output terminal AG1 (AG2) exceeds the power supply voltage Vdd.
G1 (AG2) supplies the high potential side line LH.

In consideration of charging efficiency, it is desirable that the P-channel FETs P1 and P2 be turned on as soon as the voltages at the output terminals AG1 and AG2 of the AC generator AG exceed the power supply voltage Vdd. For this reason, the current consumption of the comparators COM1 and COM2 is relatively large, so that high-speed operation can be handled. However, it is not necessary to operate the comparators COM1 and COM2 during the period when the AC generator AG is not generating power or during the period when the electromotive voltage is small even if power is generated, since the comparators COM1 and COM2 cannot be charged. Therefore, in this embodiment,
The switches S1 and S2 are provided inside the Vdd detector 1, and the switches S3 and S4 are provided in the Vdd detector 2, and these are controlled by the signal φS, thereby reducing the current consumption of the comparators COM1 and COM2.

Here, the switch S1 (S3) is between the gate of the P-channel FET P1 (P2) and the power supply Vdd, and the switch S2 (S4) is between the negative power supply terminal of the comparator COM1 (COM2) and the low potential side line LL. It is provided in. Signal φ
When S goes high, switch S1 (S3) turns on,
When the switch S2 (S4) is turned off and the signal φS goes low, the switch S1 (S3) is turned off and the switch S
Switch S1 (S3) so that 2 (S4) is turned on,
S2 (S4) is configured. Therefore, when the signal φS is set to low level, power is supplied to the comparator COM1 (COM2), and according to the comparison result, the P-channel FET P1
ON / OFF of (P2) is controlled. On the other hand, when the signal φS is set to the high level, the power supply to the comparator COM1 (COM2) is cut off, and the P-channel FET P1 (P2) is turned off. That is, whether or not to operate the Vdd detectors 1 and 2 can be controlled by the signal φS,
When not operating, the current consumption of the comparators COM1 and COM2 can be reduced.

Next, the AG2 detector 3 and the AG1 detector 4 are used to compare the voltages of the output terminals AG2 and AG1 with the reference voltages Vref1 and Vref2, respectively. FIG.
FIG. 4 is a circuit diagram of an AG2 detection unit 3 and an AG1 detection unit 4;
In FIG. 6, reference numerals shown in parentheses correspond to the AG1 detection unit 4, and reference numerals outside the parentheses correspond to the AG2 detection unit 3.

As shown in FIG. 6, the AG2 detector 3 (AG
The 1 detection unit 4) includes a comparator COM3 (COM4) and switches S5 (S7) and S6 (S8). The positive input terminal of the comparator COM3 (COM4) is connected to the output terminal AG2 (AG1) of the AC generator AG, and its negative input terminal is supplied with the reference voltage Vref2 (Vref1). Reference voltage Vr
ef2 (Vref1) is set to a voltage slightly higher than the voltage of the ground GND.

When the voltage at the output terminal AG2 (AG1) exceeds the reference voltage Vref2 (Vref1), the signal CN1 (CN2) goes high, and when the voltage at the output terminal AG2 (AG1) falls below the reference voltage Vref2 (Vref1). , The signal CN1 (CN2) becomes low level. In the AG2 detection unit 3 (AG1 detection unit 4), a switch S5 (S7) is provided between the output terminal of the comparator COM3 (COM4) and the low potential side line LL. A switch S6 (S8) is provided between the negative power supply terminal and the low potential side line LL. Switches S5 (S7), S6 (S8)
When the signal φSL becomes high level, the switch S5 (S
7) is turned on, the switch S6 (S8) is turned off, and when the signal φSL goes low, the switch S5 (S7) is turned off and the switch S6 (S8) is turned on. Therefore, when the signal φSL is set to low level, power is supplied to the comparator COM3 (COM4), and the comparison operation is performed. On the other hand, when the signal φSL is set to the high level, the power supply to the comparator COM3 (COM4) is cut off. Therefore, it is possible to control whether or not the AG2 detection unit 3 (AG1 detection unit 4) is operated by the signal φSL, and when not operated, the current consumption of the comparator COM3 (COM4) can be reduced.

Next, a circuit diagram of the sub-capacitor selecting section 7 is shown in FIG. The sub-capacitor selector 7 mainly has the first to third functions. The first function is that the output terminals AG1,
This is a function of identifying one output terminal of the AG2 where the positive electromotive voltage was generated immediately before the end of power generation, and selecting a sub-capacitor connected to the other output terminal in preparation for the next power generation. The second function is to discharge the charge stored in the sub-capacitor C1 or C2 so that the N-channel FET N
1, N1 ', N2, N2'. The third function is to provide an N-channel FE so as to raise the electromotive voltage by chopper.
This function controls TN1 and N2.

First, the configuration relating to the first function will be described. As described above, the output signal CN1 of the AG2 detector 3
Is at a high level when the voltage at the output terminal AG2 exceeds the reference voltage Vref1, while the output signal of the AG1 detection unit 4 is high.
CN2 goes high when the voltage at the output terminal AG1 exceeds the reference voltage Vref2. The signal CN1 is supplied to the clock terminal of the second latch circuit 70, and the signal CN2 is supplied to the clear terminal via the inverter 71. Thus, the output signal 71s of the second latch circuit 70 goes high when an electromotive voltage is generated at the output terminal AG2, and goes low when an electromotive voltage is generated at the output terminal AG1.
That is, it is possible to specify which terminal of the output terminals AG1 and AG2 generates the electromotive voltage based on the logic level of the signal 71s. In the following description, the signal 71s is referred to as an electromotive voltage terminal specifying signal 71s.

Next, the register 72 is composed of, for example, a D flip-flop. When the voltage of the clock terminal changes from the high level to the low level, the register 72 takes in the logic level of the data input terminal and outputs it. Has become. The data input terminal includes an electromotive voltage terminal identification signal 71
s is supplied.

Next, the output signal φSL of the power generation detector 10 is
As described above, the level is low during the power generation period, and is high during the non-power generation period. Here, the rising edge detection circuit ED generates a power generation end signal EDs that goes low for a short time in synchronization with the rising edge of the signal φSL. Since the power generation end signal EDs is supplied to the clock terminal of the register 72, the register 72 stores the logic level of the electromotive voltage terminal specifying signal 71s at the time of the end of power generation. Then, the register 72 outputs this storage state as the power generation terminal selection signal 72s.

The power generation terminal selection signal 72s is output as a signal N1g 'through an AND circuit 73 and an OR circuit 74 to the N-channel FET N1' for selecting the sub-capacitor C1, while the inverter 75, the AND circuit 76 and the OR circuit N to select the sub-capacitor C2 via 77
Output to the channel FET N2 '. As will be described in detail later, at least the signal φSL is in a high level period, that is,
In the state of waiting for the next power generation in the non-power generation state, the signals supplied to the AND circuits 73 and 76 are at the high level, and the signals supplied to the OR circuits 74 and 77 are at the low level. Has become. Therefore, in the state of waiting for the next power generation, the logic level of the signal N1g ′ matches the logic level of the power generation terminal selection signal 72s, and the logic level of the signal N2g ′ is the same as the logic level of the power generation terminal selection signal 72s. It will be.

For example, if a positive electromotive voltage is generated on the output terminal AG2 side immediately before the end of power generation, the electromotive voltage terminal specifying signal 71s becomes a high level indicating the output terminal AG2, and this is stored in the register 72. In a state of waiting for the next power generation, the power generation terminal selection signal 72s becomes high level. Therefore, in the standby state,
The signal N1g 'becomes high level, the N-channel FET N1' is turned on, and the sub-capacitor C1 is selected.
On the other hand, the signal N2g 'becomes low level and the N-channel FET
Since N2 'is turned off, the sub-capacitor C2 is not selected. As a result, the sub-capacitor C1 connected to the output terminal AG1 where the electromotive voltage is generated at the time of the next power generation is selected in the standby state. That is, the sub-capacitor selection unit 7 specifies the output terminal on which the electromotive voltage has occurred immediately before the end of power generation based on the signals CN1 and CN2 specifying the output terminal on which the positive electromotive voltage has occurred, and It is configured to select a sub-capacitor connected to the output terminal (the other output terminal).

According to the first function described above, after the power generation is completed, the sub-capacitor connected to the output terminal on the side where the positive electromotive voltage is generated next can be selected in advance. When the electromotive voltage is generated, the sub capacitor is charged immediately. As a result, boosting using the sub-capacitor can be started by the electromotive voltage generated immediately after the AC generator AG starts power generation, and the power generation detection by the power generation detection unit 10 can be hastened.

Next, the configuration relating to the second function will be described. Signal φN1 is an output signal of OR circuit OR1 shown in FIG. The logic level matches the clock signal CLK1 when the signal CN1 is at a low level (when no positive electromotive voltage is generated at the output terminal AG2), while the logic level is at a high level (when the output terminal AG2 is at the output terminal AG2). It becomes high level when the electromotive voltage of the positive electrode is generated). Also, the signal φN2
Is an output signal of the OR circuit OR2 shown in FIG. The logic level is determined when the signal CN2 is low (output terminal AG
When the positive side electromotive voltage is not generated on the 1 side) and the signal CN2 is at the high level while the clock signal CLK1 matches (when the positive side electromotive voltage is generated on the output terminal AG1 side)
To a high level. If normal chopper boosting is performed, of the N-channel FETs N1 and N2, the N-channel FET connected to the output terminal on the side where the positive electromotive voltage is generated is turned on and off, and the other output terminal is connected to the other output terminal. The connected N-channel FET may be turned on. Therefore, while controlling the N-channel FET N1 using the signal φN1, the N-channel FE is controlled using the signal φN2.
What is necessary is just to control TN2.

By the way, in this example, the sub capacitor C
1. Since the electromotive voltage is boosted using C2, the signal φSL
At the time when the signal changes from the high level to the low level, the electric charge is stored in the selected sub-capacitor. Therefore, while the signal φSL is at the low level and the power is supplied to the AG2 detection unit 3 and the AG1 detection unit 4, the sub-capacitors C1 and C2 are disconnected from the low-potential-side line LL, and the N-channel FETs N1 and N2 are disconnected. When chopper operation is performed, the electric charge remains in the selected sub-capacitor when the power generation ends. Then, since the electric charge remains even when the sub-capacitor is selected next time, the output connected to the sub-capacitor despite the fact that no electromotive voltage is generated between the output terminals of the AC generator AG. The terminal voltage goes high. For this reason, the power generation detection unit 10 erroneously detects the power generation state with a small electromotive voltage.

Therefore, in this example, two reset steps are provided so as to discharge the electric charge accumulated in the sub-capacitor so that malfunction does not occur. The first reset step is provided immediately after the start of chopper boosting. First
In the reset step, during a discharging period for discharging the electric charges charged in the sub-capacitors C1 and C2, the N-channel FET connected to the selected sub-capacitor is turned on / off, and in parallel with the N-channel FET. N-channel FET for driving the connected chopper
Are operated synchronously. Note that, in the first reset step, chopper boosting is not performed.

The second reset step is provided during a period in which chopper boosting is performed. In the second reset step, the chopper driving N-channel FET connected to the output terminal where the electromotive voltage is generated is turned on / off, and the sub-capacitor selecting N-channel FET is connected in parallel to this. Are operated synchronously. By these reset steps, the electric charge charged in the sub-capacitor is reliably discharged.

The timer counter 78 shown in FIG. 7 is used for measuring a discharge period for discharging the electric charges charged in the sub-capacitors C1 and C2. The timer counter 78 is configured to reset the count value when the voltage of the reset terminal goes low, and to generate a ripple carry signal 78s that goes high when the count value reaches a predetermined value. As shown in the figure, the clock terminal of the timer counter 78 has a clock signal CL.
K1 is supplied, and a signal φSL is supplied to the reset terminal thereof through an inverter 79. Therefore, when the signal φSL changes from the high level to the low level (when the power generation state is detected by the power generation detection unit 10), the timer counter 78 starts counting the clock signal CLK1. When the count value reaches a predetermined value, the logic level of the ripple carry signal 78s is changed to a high level.

Next, the first latch circuit 80 converts the signal 80 s which goes high in synchronization with the rise of the ripple carry signal 78 s and goes low in synchronization with the rise of the signal φSL, and a signal 80 s ′ obtained by inverting the signal 80 s ′. Output. The signal 80s' is at a high level during the above-described discharge period, while the signal 80s is a signal at a low level during the discharge period.

Next, the AND circuit 81 outputs the logical product of the signal φSL inverted by the inverter 79 and the clock signal CLK1 as the signal 81s. The logical product is output as a signal 82s. Therefore, the signal 82s becomes the clock signal CLK1 in the discharge period.

Next, the AND circuit 83 outputs the logical product of the signal 80s and the signal φN1 as a signal 83s.
The OR circuit 84 outputs the logical sum of the signal 83s and the signal 82s.
The signal is output to the gate terminal of the N-channel FET N1 as N1g. Therefore, the signal N1g matches the clock signal CLK1 during the discharge period, and matches the signal φN1 during the non-discharge period. The AND circuit 85 outputs the logical product of the signal 80s and the signal φN2 as a signal 85s, and the OR circuit 86 outputs the logical sum of the signal 85s and the signal 82s as a signal N2g to the gate terminal of the N-channel FET N2. I do. Therefore, the signal N2g is the clock signal CLK1 during the discharge period.
And the signal φN2 during the non-discharge period.

Next, the AND circuit 73 outputs the logical product of the signal 82s and the power generation terminal selection signal 72s as the signal 73s, and the OR circuit 74 outputs the signal 83s and the signal 73s.
Is output to the gate terminal of the N-channel FET N1 'as a signal N1g'. Therefore, if the power generation terminal selection signal 72s is at a high level, the signal N1g ′ matches the clock signal CLK1 during the discharge period and matches the signal φN1 during the non-discharge period. That is, if the sub-capacitor C1 is selected and the electric charge is stored therein, the N-channel FET N1 'is turned on / off according to the clock signal CLK1 during the discharging period. On the other hand, during the discharge period, the N-channel FET N1 turns on and off according to the clock signal CLK1. Therefore, when the clock signal CLK1 goes high, the N-channel FET
N1 and N-channel FET N1 'are simultaneously turned on,
The electric charge charged in the sub-capacitor C1 is discharged (first reset step).

Also, during the non-discharge period (chopper operation period), when the clock signal CLK1 becomes high level, the N-channel FET N1 and the N-channel FET N1 'are simultaneously turned on, so that the electric charge charged in the sub-capacitor C1 is discharged. (A second reset step). The same applies to the signal N2g 'corresponding to the sub-capacitor C2. By controlling the N-channel FETs N2 and N2' with the signals N2g and N2g ', respectively, the first reset step and the second reset step are performed. Be executed.

In addition, during the non-power generation period, the signal N1
g coincides with the signal φN1, and the signal N2g coincides with the signal φN2.
TN1 and N2 can be controlled. Therefore, the sub-capacitor selection unit 7 can realize the third function described above.

Next, the NOR circuit NOR1 shown in FIG.
Based on N1 and the signal φN2, it is detected whether or not the voltages of the output terminals AG1 and AG2 have exceeded the reference voltages Vref1 and Vref2. Here, the reference voltages of the AG2 detection unit 3 and the AG1 detection unit 4
Vref1 and Vref2 are, for example, the reference voltage Vr of the power generation detection unit 10.
Set to a smaller value than ef. The reason for setting the reference voltage Vref and the reference voltages Vref1 and Vref2 is as follows.

First, the reference voltage Vref serves as a reference for determining whether or not the power generation state is established. When the power generation state is detected by this determination, the power is sequentially supplied to each part of the chopper circuit 20 in response to this. You. On the other hand, pulse-like noise may be induced in the output coil L of the AC generator AG by electromagnetic waves or the like. With such noise,
If the power generation state is detected and power is supplied to the AG2 detection unit 3 and the AG1 detection unit 4, the power consumed there is wasted, and the charging efficiency is rather reduced.

Therefore, in this embodiment, the reference voltage
Vref is set relatively high so as not to be affected by noise or the like. Even if the reference voltage Vref is set as described above, the electromotive voltage generated by the AC generator AG is doubled by the sub-capacitors C1 and C2 and the diodes d1 and d2 as described above. It is possible to In addition, even if pulse-like electromagnetic noise is mixed in the output coil L, the sub-capacitor C
1, since the integration is performed by C2, the malfunction of the power generation detection is extremely small. On the other hand, the reason why the reference voltages Vref1 and Vref2 are set to relatively low voltage values is that the AG2 detection unit 3 and the AG2 detection unit 4 are turned on after the power generation state is detected. It is. That is, in this embodiment, since the detection accuracy of the power generation state is extremely high, the reference voltage
There is no problem even if Vref1 and Vref2 are set to relatively low voltage values.

Next, the NOR circuit NOR2 shown in FIG.
The logical OR of N and the clock signal CLK is calculated, and the output signal is supplied to the OR circuits OR1 and OR2. Therefore, the signal φ
While N is high level, the clock signal is OR circuit OR
1, No supply to OR2, no chopper operation. In this sense, the NOR circuit NOR2 functions as clock inhibiting means.

Next, the SR latch circuit 6
When the reset signal R goes low, the output signal is set high when the reset terminal R goes low.
An inverted SR flip-flop can be used.
In this example, since the signal φN is supplied to the set terminal S, when the signal φN becomes low level,
The voltages of the output terminals AG1 and AG2 are equal to the reference voltages Vref1 and Vref2.
Is exceeded, the signal is latched by the SR latch circuit 6, and the signal φS goes low. As described above, the Vdd detectors 1 and 2 are operated by being supplied with power when the signal φS is at a low level. 1 and 2 can be operated.

The reason why the power supply is controlled by providing two levels of threshold values in this way is as follows. As in this example, the purpose of the chopper-type charging circuit 100 is to boost a small electromotive voltage, and a voltage slightly higher than the voltage of the ground GND is used as a reference voltage to detect the power generation state of the AC generator AG. Based on the detection result, the AG2 detection unit 3 or A
It is necessary to control power supply to the G1 detection unit 4 and further to the Vdd detection units 1 and 2.

However, when the reference voltage is set to a small value, even if an electromotive voltage is induced between the output terminals AG1 and AG2 due to a disturbance such as a magnetic field, or if the user of the wristwatch slightly moves his arm to boost the voltage, If a small electromotive voltage that cannot be charged occurs, the voltages of the output terminals AG1 and AG2 do not exceed the power supply voltage Vdd, and eventually a charging current cannot be obtained. In such a case, if the current is consumed by supplying power to the comparators COM1 and COM2 which are fast but consume a large amount of current, the charging efficiency is reduced. Therefore, in the present embodiment, the reference voltage Vref and the reference voltages Vref1, Vref2
Is used to monitor the electromotive voltage of the AC generator AG, and control the power supply to each comparator as necessary to reduce current consumption.

In accordance with the above-described power supply control, the current consumption of the comparators COM1 to COM6 is set as follows. COM1, COM2> COM3, COM4> COM5, COM6 The reason why the current consumption of the comparators COM5 and COM6 is set to be the smallest is that they are provided inside the power generation detection unit 10 and always detect the electromotive voltage of the AC generator AG. It is necessary to monitor. Further, the reason why the current consumption of the comparators COM1 and COM2 is set to be the largest is that it is detected that the voltages of the output terminals AG1 and AG2, which are the conditions for charging, exceed the power supply Vdd. Furthermore, the reason why the current consumption of the comparators COM3 and COM4 is set to be smaller than that of the comparators COM1 and COM2 is that the comparators COM3 and COM4 detect the preconditions for charging, and therefore operate in comparison with the comparators COM1 and COM2. This is because the speed may be low. However, the comparators COM3 and COM4 are connected to the output terminal AG.
1. N-channel FETN until AG2 exceeds power supply Vdd
1. Since it is necessary to operate N2, it is necessary to have a response speed that satisfies this.

By setting the current consumption as described above, power can be supplied in order from the one with the smallest current consumption to the one with the largest current consumption, so that the current consumption can be further reduced and the charging efficiency can be improved. Specifically, the total current consumption of the comparators COM1 to COM4 is about 500 nA, while the current consumption of the comparators COM5 and COM6 is about 10 nA. Therefore, the current consumption during standby can be reduced to about 1/50 of that during normal operation.

By the way, the operating speed of the comparator becomes slower as the current consumption becomes smaller. Therefore, when the current consumption is set as described above, even if the AC generator AG changes from the power generation state to the non-power generation state, the operation speed is immediately changed to the non-power generation state. Power generation status cannot be detected. Then, when the AC generator AG further changes from the non-power generation state to the power generation state, a state change is detected after the delay time of the comparators COM5 and COM6 has elapsed.

Therefore, if the AC generator AG repeats the power generation state and the non-power generation state in a short cycle, the period in which the electromotive voltage of the AC generator AG exceeds the power supply voltage Vdd and satisfies the charging condition in the power generation state. Despite this, there is an inconvenience that charging can be performed only in part of the period.

Therefore, in the present embodiment, power supply is continued for a certain period of time after the comparators COM3 and COM4 detect that the voltages at the output terminals AG1 and AG2 have fallen below the reference voltages Vref1 and Vref2. The power supply is stopped after a certain time has elapsed.

Specifically, output signal φN of NOR circuit NOR1
Changes from low level to high level,
The voltages of the output terminals AG1 and AG2 are equal to the reference voltages Vref1 and Vref2.
Is detected, the signal φN is output to the NOR circuit NOR.
2. The signal φR is supplied to the reset terminal R of the timer counter 5 via the NOR3. Here, the timer counter 5
Is configured to count the clock signal CLK, output a ripple carry signal which becomes low when the count value reaches a predetermined value as a signal φR1, and reset the count value to 0 when its reset terminal R becomes low level. Have been.

Therefore, when the signal φN changes from the low level to the high level, the signal φR changes from the low level to the high level, the reset is released, and the timer count 5 starts time measurement. And the signal φ
When the state in which N is at the high level, that is, the non-power generation state continues for a predetermined time and the count value reaches the predetermined value, the signal φR1 becomes low level and the latch means 6 is reset. As described above, when the latch means 6 is reset, the output signal φS
Is set to a high level, so that, for the first time, the signal φS
Becomes high level, and the power supply to the comparators COM1 and COM2 is stopped. When the signal φS is supplied to the power generation detection unit 10, the signal φS is output as the signal φSL via the inverting circuit 12 and the NOR circuit 13, and thereby the comparator CO
Power supply to M3 and COM4 is stopped.

On the other hand, during the measurement by the timer counter 5,
The voltages of the output terminals AG1 and AG2 are equal to the reference voltages Vref1 and Vref2.
, The signal φN goes low, the timer counter 5 is reset again, the latch means 6 is not reset, and the signal φS is maintained at low level. That is, the time measurement by the timer counter 5 is performed retriggerably, and only when the non-power generation state continues for a predetermined time,
The power supply to the comparators COM1 to COM4 is stopped.

<1-1-3: Mechanical Configuration> Next, the configuration of the AC generator AG and its peripheral mechanism will be described. FIG. 8 is a perspective view showing the configuration of the AC generator AG and its peripheral mechanism.
As shown in the figure, the AC generator AG includes a rotor 14 and a stator 15. When the rotor 14 in the form of a bipolar magnetized disk rotates, an electromotive force is generated in an output coil L of the stator 15, and an AC output is generated. Can be taken out. In the figure, reference numeral 13 denotes a rotating weight that performs a turning motion in the wristwatch main body case, and 11 denotes a wheel train mechanism that transmits the rotating motion of the rotating weight 13 to the generator AG. Rotating weight 13
Rotates in accordance with the swing of the arm of the person wearing the wristwatch, so that an electromotive force can be obtained from the AC generator AG.

The AC output from the AC generator AG is rectified by the chopper type charging circuit 100 according to the present embodiment.
It is supplied to the processing device 9. The processing device 9 drives the timepiece device 7 with the electric power discharged from the chopper-type charging circuit 100. The timepiece device 7 includes a crystal oscillator, a counter circuit, and the like. The master clock signal generated by the crystal oscillator is frequency-divided by the counter circuit, and time is measured based on the frequency division result. In this example, the chopper type charging circuit 100 described above is used as a master clock signal or a signal obtained by dividing the master clock signal as a clock signal CLK.
To supply. Therefore, the circuit for generating the clock signal CLK can be shared by the chopper charging circuit 100 and the timepiece device 7. As a result, the circuit configuration can be simplified and the current consumption of the entire wristwatch can be reduced.

<1-2: Operation of First Embodiment> Next, the operation of the present embodiment will be described with reference to the drawings. FIG.
5 is a timing chart of the chopper-type charging circuit 100 according to the present embodiment. In this example, it is assumed that the N-channel FET N2 'connected to the sub-capacitor C2 is in the on state and the N-channel FET N1' connected to the sub-capacitor C1 is in the off state in the non-power generation state. I do. Also, FIGS.
And 20 are chopper type charging circuits 1 according to the present embodiment.
It is a flowchart of 00.

First, at time t10, assuming that the user moves the arm on which the wristwatch is worn, AC generator AG starts generating power. At this time, if an electromotive voltage V2 is generated on the AG2 side as shown in FIG. 9A, the sub-capacitor C2 is charged by this (SP1A to SP3).
A). Therefore, the voltage of the output terminal AG2 is equal to the electromotive voltage V2
It does not decrease even if decreases.

Next, at time t11, when the electromotive voltage V2 on the AG2 side becomes "0" and the electromotive voltage V1 is generated on the AG1 side, the voltage at the output terminal AG1 becomes as shown in FIG. The sum of the voltage Vg2 charged in the sub-capacitor C2 and the electromotive voltage V1 (SP1 → SP2 → S
P30 → SP31). Therefore, immediately after time t11, the voltage of the output terminal AG1 exceeds the reference voltage Vref. Then
The power generation detection unit 10 detects a power generation state (SP5). However, since the low power consumption comparators COM5 and COM6 of the power generation detection unit 10 are used, the signal φSL falls from the high level to the low level as shown in FIG. The elapsed time t12 is reached.

At time t12, the signal φSL goes low, so that power is supplied to the AG2 detection unit 3 and the AG1 detection unit 4, and the voltage of the output terminal AG2 is compared with the reference voltage Vref1 and the output terminal AG2 is output. AG1 voltage is the reference voltage Vr
It is compared with ef2 (SP6). Here, the reference voltage Vref1,
Since Vref2 is set lower than the reference voltage Vref, each output signal CN of the AG2 detection unit 3 and the AG1 detection unit 4
1, CN2 is at a high level as shown in FIGS. 9 (e) and 9 (f).

When the signal φSL goes low, the timer counter 78 of the sub-capacitor unit 7 shown in FIG. 7 counts the rising edge of the clock signal CLK1 (see FIG. 9C) (SP7 to SP11). The timer counter 78 sets the ripple carry signal 78s to the high level when the count value reaches "3". If the ripple carry signal 78s is at the time t as shown in FIG.
When it reaches 13, it becomes high level. Then, the output signal 80s of the first latch circuit 80 becomes, as shown in FIG.
It rises in synchronization with the ripple carry signal 78s and falls in synchronization with the rise of the signal φSL. Here, the symbol tc shown in FIG. 9 (j) is a discharge period, during which the sub-capacitor selector 7 executes the above-described first reset step.

Since the signal 80s 'is the inverse of the signal 80s, the signal 80s' goes high during the discharge period tc (SP12). Therefore, the AND circuit 82
Output signal 82s coincides with the clock signal CLK1 during the period tc. On the other hand, the AND circuit 73,
76 operates as a selection circuit that selects and outputs the output signal 82s according to the logic level of the power generation terminal selection signal 72s. In this example, since the power generation terminal selection signal 72s is at the low level during the discharge period tc, the signal 76s becomes the clock signal CLK1 during the discharge period tc.
While the signal 73s maintains the low level.
In addition, during the discharge period tc, the signal 80s is at a low level, so that the signals 83s and 85s are at a low level. As a result, during this period, the signal N2g ′ matches the clock signal CLK1, while the signal N1g goes low (SP13). Further, since the signals 83s and 85s are at the low level, the signal N1g, which is the logical sum of the signal 83s and the signal 82s, and the signal N2g, which is the logical sum of the signal 85s and the signal 82s, both match the clock signal CLK1. .

As described above, during the discharge period tc, the signal
Since the logical level of N2g 'and the signal N2g match the clock signal CLK1, when the clock signal CLK1 is at the high level, the N-channel FETs N2 and N2' are turned on, and the electric charge charged in the sub-capacitor C2 is discharged. In this example,
Discharge is performed in the periods ta and tb. This allows
When the period tb ends, the potential of the output terminal AG2 becomes substantially equal to the potential of the ground GND.

When the electric charge of the sub-capacitor C2 is discharged, the operation shifts to the chopper operation period. After time t13, a positive electromotive voltage is generated on the AG1 side, and conversely, the potential of the output terminal AG2 is substantially equal to the potential of the ground GND. Therefore, the output signal CN1 of the AG2 detection unit 3 becomes low level, and the output signal φN1 of the OR circuit OR1 matches the clock signal CLK1. The signal N1g 'is generated by the AND circuit 83 and the OR circuit 74 so as to coincide with the signal φN1 when the signal 80s is at the high level (SP14). On the other hand, since the signal 80s is at the high level after the time t13, the signal N1g matches the clock signal CLK1 after the time t13 as shown in FIG. 9 (k).

In this case, since the signal N2g goes high as shown in FIG. 9 (l), the N-channel FET N1 keeps on and off while the N-channel FET N1 keeps on. Thereby, the electromotive voltage of AC generator AG is boosted by the chopper. When the voltage at the output terminal AG1 exceeds the power supply voltage Vdd, the P-channel FET P1 turns on. At this time, a closed loop of AG1 → P1 → main capacitor 30 → GND → N2 → AG2 is formed, and the generated current is stored in the main capacitor 30 (SP15).

Further, after time t13, the signal
The signal N2g matches the signal N2g '(see FIG. 9 (i)), and the signal N1g matches the signal N1g' (see FIG. 9 (h)). For this reason, during the period when each signal is at the high level, even if the electric charges are accumulated in the sub-capacitors C1 and C2, they are discharged.

Next, at time t14, the output terminal AG
When the electromotive voltage V2 having a positive polarity on the second side is generated again, the output signal CN1 of the AG2 detection unit 3 rises. Then, since the second latch circuit 70 latches the high level, the electromotive voltage terminal specifying signal 71s rises from the low level to the high level as shown in FIG. 9 (m) (SP40 → SP40A → SP).
41A). Thereafter, contrary to the above-described case, the N-channel FET N2 repeatedly turns on and off, while the N-channel FET N1 'maintains the on state. Thereby, the electromotive voltage of AC generator AG is boosted by the chopper. When the voltage at the output terminal AG2 exceeds the power supply voltage Vdd, the P-channel FET P2 is turned on. At this time, AG2 → P
A closed loop of 2 → main capacitor 30 → GND → N1 → AG1 is formed, and the generated current is stored in the main capacitor 30 (SP15).

Then, the electromotive voltage V2 decreases, and at time t15
When the voltage at the output terminal AG2 falls below the reference voltage Vref1, the signal CN1 goes low. Timer counter 5
Is reset at time t15, but is not reset thereafter. When the charging end detection time TM elapses from time t15 and reaches time t16, the signal φSL goes high. Then, the rising edge detection circuit ED detects the rising edge of the signal φSL and generates the power generation end signal EDs shown in FIG. 9 (n) (SP21, SP2).
2). Since the register 72 stores the electromotive voltage terminal specifying signal 71s in synchronization with the power generation end signal EDs, the power generation terminal selection signal 72s becomes a high level at time t16 as shown in FIG. 9 (o) (SP24, SP25). ). Thus, the output terminal AG2 that has generated power immediately before the end of the power generation period
Is specified, and after time t16, the n-channel FET N1 'connected to the sub-capacitor C1 is turned on in preparation for the next power generation (SP26).

As described above, according to the chopper-type charging circuit 100 of the first embodiment, the sub-capacitor C1,
Since the electromotive voltage of the alternator AG is doubled using C2, and the power generation detection unit 10 detects the power generation state based on the doubled electromotive voltage, the threshold voltage used for detecting the power generation state is set to the threshold voltage. Even if it is set relatively high, the power generation state can be detected early. Further, even if noise is induced in the output coil L, the noise is integrated by the sub-capacitors C1 and C2, so that malfunction due to noise can be almost eliminated.

The chopper type charging circuit 100 accumulates electric charge in one of the sub-capacitors when the electromotive voltage is doubled, but discharges the electric charge immediately after detecting the power generation state. For this reason, electric charge remains in the sub capacitor,
When the next power generation is performed, the power generation detecting unit 10 does not malfunction.

Further, in the chopper type charging circuit 100,
The power generation state of the alternator AG is detected using the reference voltage Vref, and the comparator COM is output only when the power generation state is detected.
3.Because power is supplied to COM4, the comparator COM
3. The current consumed by COM4 can be reduced. Further, the voltages of the output terminals AG1, AG2 of the AC generator AG are changed to the reference voltages Vref1, Vref2 by the comparators COM3, COM4.
Comparator COM only when it is detected that
1, because COM2 is powered, the comparator COM
1. The current consumed by COM2 can be reduced. Moreover, the current consumption of each comparator is set to “COM1, COM2> COM
Since “3, COM4> COM5, COM6” are set in this order, power is supplied in ascending order of current consumption, so that current consumption can be further reduced.

In addition, if the current consumption of the comparator is reduced, the response speed becomes slow. Therefore, once the power generation state is changed to the non-power generation state, the charging may not be performed. However, in this example, the timer counter 5 measures the time during which the voltages at the output terminals AG1 and AG2 continuously fall below the reference voltages Vref1 and Vref2. Since the power supply is deemed to be stopped, the above-described problem does not occur. Therefore, even if a comparator with low current consumption is used, the non-power generation state can be reliably detected and power supply can be stopped, so that current consumption can be significantly reduced. Further, once power supply to the comparators COM1 and COM2 is started, the comparators continue to be operated at least until the end-of-charge detection time TM set in the timer counter 5 has elapsed.
Since power is supplied to COM1 to COM4, it is possible to charge the battery with good responsiveness even to a small electromotive voltage.

<2. 2. Second Embodiment <2-1: Configuration of Second Embodiment> FIG. 10 is a circuit diagram of a chopper-type charging circuit used in a wristwatch according to the present embodiment. Chopper type charging circuit 100 'of the second embodiment
Has the same configuration except that the chopper circuit 20 'is different from the chopper circuit 20 of the first embodiment shown in FIG. Specifically, in the chopper circuit 20 ', the P-channel FETs P1 and P2 are connected in parallel with the P-channel FETs P1 and P2.
1 ′, P2 ′, and the ON / OFF state of the P-channel FETs P1 ′, P2 ′ in the sub-capacitor selector 7 ′.
The difference is that a signal Pg ′ for controlling the turning off is generated.

As in the first embodiment, in the chopper circuit 20 ', the output terminals AG1, AG2 are formed by using the sub-capacitors C1, C2 and the diodes d1, d2.
The electromotive voltage generated between the two is doubled. However, the chopper circuit 20 of the first embodiment includes sub-capacitors C1 and C2
However, in the chopper circuit 20 ′, the charge stored in the sub-capacitors C1 and C2 is transferred to the main capacitor 30 to further increase the charging efficiency. As will be described later in detail, the chopper circuit 20 ′ uses the signal Pg ′ to transfer P
The channel FETs P1 'and P2' are turned on and off simultaneously.
In parallel with this, N-channel FETs N1 'and N2'
One of the N-channel FETs connected to a sub-capacitor (eg, C1) having no charge stored therein
(E.g., N1 ') is turned off while the other N-channel FET (e.g., N2') is turned off by P-channel FETs P1 ', P2'.
The voltage stored in the sub-capacitor (for example, C2) is chopper-boosted by turning on and off in a complementary manner. More specifically, P-channel FETs P1 ', P2'
Are turned on and off at the same time, when the P-channel FETs P1 'and P2' are on, the other N-channel FET is turned off while the P-channel FET P
When 1 'and P2' are off, the other N channel FE
T is turned on.

FIG. 11 is a circuit diagram of the sub-capacitor selector 7 'for generating the signal Pg'. This sub-capacitor unit 7 'is provided with a signal CN1 and a signal C instead of the timer counter 78.
A point using the NAND circuit 87 for calculating the logical product of N2, a point outputting the output signal of the AND circuit 82 as the signal Pg ′, and a deletion of the OR circuits 84 and 85 and the AND circuit 83
The sub-capacitor selection unit 7 of the first embodiment shown in FIG. 7 is different from the sub-capacitor selection unit 7 shown in FIG. It is configured.

<2-2: Operation of the Second Embodiment>
The operation of the chopper-type charging circuit 100 'according to the second embodiment will be described. FIG. 12 is a timing chart of the chopper-type charging circuit 100 'according to the present embodiment. In this example, in the non-power generation state (before time t10)
, The N-channel FET N2 'connected to the sub-capacitor C2 is in the ON state, and the sub-capacitor C1
Is turned off. Here, the chopper type charging circuit 10
The flow chart of 0 ′ is the same as the flow charts shown in FIGS.
21 and 22 are the same except that 0 is replaced by SPA, SPB, and SPC. FIGS. 21 and 22 show flowcharts including different processes (SPA to SPC), and flowcharts after SP15 share FIGS. 19 and 20. .

First, at time t10, assuming that the user moves the arm on which the wristwatch is worn, AC generator AG starts power generation. At this time, if an electromotive voltage V2 is generated on the AG2 side as shown in FIG.
A closed loop of 2 → N2 ′ → GND → d1 → AG1 is formed, thereby charging the sub-capacitor C2 (SP1A ~
SP3A). Therefore, the voltage of the output terminal AG2 does not decrease even if the electromotive voltage V2 decreases due to the charging voltage of the sub-capacitor C2.

Next, at time t11, when the electromotive voltage V2 on the AG2 side becomes "0" and the electromotive voltage V1 is generated on the AG1 side, the voltage at the output terminal AG1 becomes as shown in FIG. Voltage Vg2 charged in sub-capacitor C2
And the electromotive voltage V2 (SP1 → SP2 →
SP30 → SP31). Therefore, immediately after time t11, the voltage of the output terminal AG1 exceeds the reference voltage Vref. Then, the power generation detection unit 10 detects the power generation state (SP5).
However, since low power consumption is used for the comparators COM5 and COM6 of the power generation detection unit 10, the signal φSL falls from the high level to the low level as shown in FIG. Is the time t12 when the response time td has elapsed.

At time t12, the signal φSL goes low, so that power is supplied to the AG2 detection unit 3 and the AG1 detection unit 4, the voltage at the output terminal AG2 is compared with the reference voltage Vref2, and the output terminal AG2 is compared with the reference voltage Vref2. AG1 voltage and reference voltage Vr
ef1 is compared (SP6). Here, the reference voltage Vref
1. Since Vref2 is set lower than the reference voltage Vref, each output signal CN of the AG2 detection unit 3 and the AG1 detection unit 4
1 and CN2 are at a high level as shown in FIGS. 12 (e) and 12 (f).

The NAND circuit 87 of the sub-capacitor selector 7 'shown in FIG. 11 inverts the logical product of the signal CN1 and the signal CN2 to generate an output signal 87s (see FIG. 12 (j)). Therefore, the signal 87s indicates that the voltage of the output terminal AG1 is equal to the reference voltage.
When the voltage exceeds Vref1 and the voltage of the output terminal AG2 exceeds the reference voltage Vref2, the level becomes low. Since an AC voltage is induced in the output coil L, if the voltage is not boosted by the sub-capacitors C1 and C2, the voltages at the output terminals AG1 and AG2 will not exceed the reference voltages Vref1 and Vref2 at the same time. . In other words, since one of the sub-capacitors C1 and C2 is charged, the output signal 87s becomes low level.

Here, the signal Pg 'is generated by the NAND circuit 81' and the AND circuit 82. As shown in FIG. 12 (g), the clock signal Pg 'is generated during the low level period of the signal 87s.
This is a signal obtained by inverting CLK1. As a result, the P-channel FETs P1 ′ and P2 ′ are turned on in the periods ta and tb, so that the voltages of the output terminals AG1 and AG2 match the power supply voltage Vdd in the periods ta and tb. In these periods, a closed loop of AG1 → P1 ′ → Vdd → P2 ′ → AG2 is formed, so that energy is stored in the output coil L.

The signals N1g and N2g are obtained by gating the signals φN1 and φN2 with the signal 80s. Signal 80s
Is at a low level before time t16 as shown in FIG. 12 (k), so that the signals N1g and N2g are
As shown in (m), before time t16, it is at the low level. Therefore, while the signal 87s is at the low level, the N-channel FETs N1 and N2 are off. In addition, signal N1
g ′ is, as shown in FIG.
16, while the signal N2g ′ is
As shown in FIG. 12 (i), the level becomes low in the periods ta and tb, and becomes high in the periods te and tf.

Therefore, in the periods te and tf, the P-channel FETs P1 'and P2' are turned off and the N-channel FET N2 'is turned on. Energy is released and the chopper is boosted (SPA,
SPB). At this time, when a closed loop of AG1 → P1 → main capacitor 30 → GND → N2 ′ → C2 → AG2 is formed, the charge stored in the sub capacitor C2 is transferred to the main capacitor 30 (SPC). In this example, charge transfer is performed in a period from time t13 to time t14 and in a period from time t15 to time t16. Along with this charge transfer, the voltage across the sub-capacitor C2 decreases.

Eventually, the voltage of the output terminal AG2 becomes the reference voltage
When the voltage falls below Vref1 (time t16 in this example), the signal CN1
Falls, and in synchronization with this, the signal 80 s goes high. As described above, the signals N1g and N2g are the signals φN1 and
Since φN2 is gated by signal 80s,
After time t16, the signals N1g and N2g match the signals φN1 and φN2, respectively. Accordingly, during the period from time t16 to time t17, the signal N1g causes the N-channel FET N1
Repeatedly turns on and off, while the signal N2g keeps the N-channel FET N2 on. On the contrary,
Since the signal N2g 'maintains the high level, the N-channel FE
While TN2 'is on, signal N1g' matches signal N1g, so that N-channel FET N1 'is N-channel FET N
On / off is repeated in synchronization with 1 (SPB). In other words, during the period from time t16 to time t17, the signal Ng1 ′ and the signal Ng1 are synchronized, and the signal Ng2 ′ and the signal Ng2 ′ are synchronized.
g2 will be synchronized.

First, the N-channel FET N1 repeats ON / OFF, while the N-channel FET N2 maintains the ON state. Therefore, during the period when the N-channel FETs N1 and N2 are simultaneously turned on, energy is accumulated in the output coil L, and the chopper is boosted during the period when the N-channel FET N1 is turned off.

At time t16, when the voltage at the output terminal AG2 matches the reference voltage Vref2, the sub-capacitor C2 stores the electric charge corresponding to the reference voltage Vref2, but the N-channel FET N2 'is the N-channel FET N2. On and off are repeated in synchronization with the clock, so during the period when they are simultaneously turned on, C2 → N2 → GND → N2 '
→ A closed loop of C2 is formed, and electric charges are discharged. That is, when the electromotive voltage of the AC generator AG is boosted by the chopper, the sub-capacitor is discharged by forming a closed loop including the charged sub-capacitor in synchronization with the chopper cycle. This allows
After the end of the continuous electromotive voltage from time t10 to time t19, the next time an AC voltage is generated in the output coil L, the charge of the sub-capacitor is "0". The operation can be started from the same state every time.

Next, during a period from time t17 to time t18, an electromotive voltage is generated again at the output terminal AG2. At time t17, since the voltage of the output terminal AG2 exceeds the reference voltage Vref1, the signal CN1 rises from a low level to a high level. The electromotive voltage terminal specifying signal 71s is the signal CN
Second latch circuit 70 that latches at the rising edge of 1
, The electromotive voltage terminal specifying signal 71s
Goes high at time t17 as shown in FIG.

Also, during this period, the signal N1g goes high and the N-channel FET N1 is turned on, so that the output terminal AG1 is connected to the low potential side line LL via the N-channel FET N1. Also, during this period, since the signal N2g matches the clock signal CLK1,
The N-channel FET N2 is repeatedly turned on and off (SPB). When the N-channel FETs N2 and N1 are simultaneously turned on, a closed loop of AG2 → N2 → GND → N1 → AG1 is formed, and energy is accumulated in the output coil L. On the other hand, when the N-channel FET N2 is turned on while the N-channel FET N2 is turned off, the energy stored in the output coil L is released, so that the chopper is boosted. Thereby, when the voltage of the output terminal AG2 exceeds the power supply voltage Vdd, AG2 → the main capacitor 30 →
A closed loop of GND → N1 → AG1 is formed, and a charging current flows into the main capacitor 30 (SPC).

Next, at time t18, the output terminal AG
When the voltage of No. 2 becomes lower than the reference voltage Vref1, the signal CN1 becomes low level. At this time, the voltage of the output terminal AG1 is the reference voltage
Since it is lower than Vref2, the signal CN2 is also at the low level. When these conditions are satisfied, the timer counter 5
Starts measuring the clock signal CLK. And time t
When the charge end detection time TM elapses from 18 and reaches time t19, the SR latch 6 is reset, and the signal φS goes high. The signal φSL changes the signal φS to the power generation detection unit 10.
At the time t19, the signal φSL rises from the low level to the high level. Then, the rising edge detection circuit ED detects the rising edge of the signal φSL and changes the logic level of the power generation end signal EDs to a low level as shown in FIG.
22). Then, the register 72 updates the storage state in synchronization with the power generation end signal EDs (SP23 to SP27). In this example, since the electromotive voltage terminal specifying signal 71s is at the high level after the time t17, the storage state (the signal 72s) of the register 72 becomes “H” at the time t19 as shown in FIG. Be updated.

That is, which of the output terminals AG1 and AG2 has the positive electromotive voltage generated immediately before the end of the continuous AC voltage generation period is stored. Then, a sub-capacitor is selected based on the storage state. In this example, immediately before the termination, a positive electromotive voltage is generated on the output terminal AG2 side, so that the sub-capacitor C1 connected to the low-voltage output terminal AG1 is selected (SP26). Specifically, at time t19, the signal N1g 'becomes high level, and the N-channel FET N1
Is turned on. As a result, selection of the sub-capacitor is performed in preparation for the next power generation.

As described above, according to the chopper-type charging circuit 100 'of the second embodiment, similarly to the first embodiment, the AC generator AG uses the sub-capacitors C1 and C2.
The power generation detection unit 10 detects the power generation state based on the doubled boosted electromotive voltage.
Even if the threshold voltage used for detecting the power generation state is set relatively high, the power generation state can be detected early. In addition, when the electromotive voltage is doubled, charge is accumulated in one of the sub-capacitors. Immediately after detecting the power generation state, the chopper is boosted and the charge accumulated in the one sub-capacitor is transferred to the main capacitor 30. Therefore, the charging efficiency can be further improved.

As described above, according to the present embodiment, the chopper-type charging circuit 100 ′ having a high charging efficiency can be provided since the charging start timing can be advanced while the current consumption of the control system is significantly reduced. Can be. Further, in a wristwatch which is required to be light and small, the AC generator AG provided therein must be small. Therefore, the electromotive voltage generated in the AC generator AG is small, and the rectification efficiency is not good. Therefore, the above-mentioned chopper type charging circuit 1
It is extremely useful to apply a watch with good charging efficiency such as 00 'to a wristwatch. In particular, in the above-described chopper-type charging circuit 100, during the period when the user does not wear the wristwatch on the wrist, the comparator that consumes the least current is used.
Only COM5 and COM6 are powered to monitor the state of power generation, so the current consumed during that time is very small. For this reason, even when the user has not used the wristwatch for a long period of time, it is possible to greatly reduce the situation in which the watch stops and the time is not known when the user wants to use the watch.

<4. Modifications> The present invention is not limited to the above-described embodiment. For example, various modifications described below are possible. (1) In each of the above-described embodiments, a wristwatch is described as an example of the electronic device using the chopper-type charging circuits 100 and 100 ′. However, the present invention is not limited to this. Blood pressure monitors, mobile phones,
It can be applied to pagers, pedometers, etc. In short, the present invention may be applied to any electronic device that consumes power, particularly any portable electronic device. In such an electronic device, the electronic circuit and the mechanical system built therein can be continuously operated without a battery, so that the electronic device can be used at any time, and a troublesome battery can be used. No need for replacement. Further, there is no problem associated with the disposal of the battery.

Note that the battery may also be used as the above-mentioned chopper-type charging circuits 100 and 100 '. In this case, if the electronic device is not carried around for a long time, the electronic device is immediately operated by the power from the battery. After that, the user can carry the electronic device and operate the electronic device with the generated power.

(2) In each of the above embodiments, as an example of the switch means, the P-channel FETs P1, P2,
Although the N-channel FETs N1 and N2 are illustrated, a PNP transistor may be used instead of the P-channel FETs P1 and P2, and an NPN bipolar transistor may be used instead of the N-channel FETs N1 and N2. However, in these bipolar transistors, the saturation voltage between the emitter and the collector is usually about 0.3 V. Therefore, when the electromotive voltage of the AC generator AG is small, as in the above-described embodiment, It is desirable to use an FET for the power supply. (3) In each of the above embodiments, the comparator COM1
To COM4, each logic circuit may be configured using an FET, and the entire chopper-type charging circuits 100 and 100 'may be built in a one-chip IC.

(4) In each of the embodiments described above, the chopper operation is performed by switching the N-channel FETs N1 and N2 on the low potential side line LL side in synchronization with the clock signal CLK1, but the comparators COM1 to COM4 and The logic circuit and the like are configured to be upside down, and the power supply Vdd side P
The channel FETs P1 and P2 may be configured to switch. In this case, since the relationship between the power supply Vdd and the low potential side line LL is reversed, the resistors R1 and R2 shown in FIG. 2 are connected to the power supply Vdd, and the reference voltage Vref is applied to the power supply Vdd. Further, the reference voltages Vref1 and Vref2 are given to the power supply Vdd. That is, each reference voltage is applied to the line to which the switching FET is connected. In short, when the chopper operation is performed between the two lines, the voltages of the output terminals AG1 and AG2 of the AC generator AG are compared with the two thresholds, and the power is supplied to the comparator according to the comparison result to reduce the current consumption. Any one may be used.

(5) In each of the above-described embodiments, the chopper circuit for performing full-wave rectification has been described as an example. However, the present invention is not limited to this, and may be applied to a bridge-type charging circuit shown in FIG. Of course, it can also be applied.
In this case, the diodes d1 and d2, the sub-capacitors C1 and C2, the N-channel FETs N1 'and N2' shown in FIG.
The power generation detection unit 10 may be added to control the power supply to the comparators COM1 to COM4.

(6) In each of the above-described embodiments, the power generation detection unit 10 has the output terminals AG1 and AG1 of the AC generator AG.
Although the voltage of AG2 is constantly monitored, the present invention is not limited to this.
1. The voltage of AG2 may be monitored. Further, the charge termination detection time TM is appropriately set, and each output terminal A
The power generation state may be monitored based on one of the voltages G1 and AG2. For example, when the charging end detection time TM is set to 30 ms, and the generated power is compared between the case where the power generation state is monitored based on the voltage of one output terminal and the case where the power generation state is monitored based on both output terminals, Both are almost the same. Therefore, by appropriately setting the charging end detection time TM, it is possible to detect the power generation state based on the voltage of one output terminal. In this case, one of the comparators COM5 and COM6 can be reduced, so that the current consumption during standby can be further reduced. Specifically, the current consumption during standby can be reduced to approximately 5.5 nA.
It can be reduced to about 1/100 of the normal operation. In a conventional rectifier circuit using a Schottky diode, since there is a leakage current of about 20 nA per element,
Compared with this, the current consumption can be reduced.

(7) The chopper-type charging circuit according to each of the above-described embodiments may be applied to an electronically controlled mechanical timepiece having a mainspring-type generator. FIG. 13 is a perspective view showing the mechanical structure of the electronically controlled mechanical timepiece. In this watch,
The mainspring 110 is connected to a crown (not shown), and mechanical energy is accumulated in the mainspring 110 by winding the crown. A speed increasing gear train 120 is provided between the mainspring 110 and the rotor 131 of the generator 130. The speed increasing wheel train 120 is a minute hand 1
It is composed of a second wheel 121, a third wheel 122 to which 24 is fixed, a fourth wheel 123 to which the second hand 125 is fixed, and the like. Then, the movement of the mainspring 110 is transmitted to the rotor 131 of the generator 130 by the speed increasing train train 120, so that power generation is performed. Here, the generator 130 also acts as an electromagnetic brake,
The pointer fixed to 20 is rotated at a constant speed. In this sense, the generator 130 also functions as a governor.

FIG. 14 is a block diagram showing an electrical configuration of the electronically controlled mechanical timepiece. In the figure, the chopper circuit 200 includes a generator 130 and a rectifier circuit 140. The electromotive voltage of the generator 130 is rectified by the rectifier circuit 140 and the capacitor 150 is charged. The capacitor 150 supplies power to the chopper circuit 200, the speed control circuit 170, and the oscillation circuit 160. The oscillation circuit 160 generates the clock signal CLK using the crystal oscillator 161. In the speed control circuit 170, when the detection circuit 102 detects the power generation frequency of the generator 130, the control circuit 103
The rectifier circuit 140 is controlled so that the electromagnetic brake is adjusted so that the rotation cycle of the rotor 131 matches the cycle of the clock signal CLK and the rotation speed of the rotor 131 is constant.
In this case, the rectifier circuit 140 is controlled by a control signal generated based on the clock signal CLK.

Here, the rotation of the generator 130 is controlled by turning on and off the both ends of the coil of the generator 130 with a switch capable of short-circuiting and choppering. This switch is, for example, the N-channel F in the above-described embodiment.
ETN1 and N2 are equivalent. When the switch is turned on by this chopper, a short brake is applied to the generator 130 and electric energy is accumulated in the coil of the generator 130. On the other hand, when the switch is turned off, the generator 1
30 operates to release the electric energy stored in the coil and generate an electromotive voltage. At this time, since the electric voltage at the time when the switch is turned off is added to the electromotive voltage, the value can be increased. For this reason, when the generator 130 is controlled by the chopper, the decrease in the generated power during braking can be compensated for by the increase in the electromotive voltage when the switch is turned off, and the braking torque can be increased while maintaining the generated power at or above a certain level. Electronically controlled mechanical timepieces can be configured. In such an electronically controlled mechanical timepiece, the power supply method and the power supply stop method of the chopper circuit described in the above embodiment may be applied. In this case, the charging efficiency can be further improved, and an electronically controlled mechanical timepiece having a longer duration can be provided.

(8) In each of the embodiments described above, the case where the electromotive force of the AC generator is charged has been described. However, the present invention is not limited to this, and the case where an AC voltage such as a commercial AC power supply or an electromagnetic wave is charged. Can also be widely applied. Further, as a method of inputting power, a method of inputting contactlessly, such as inputting induced electromotive force via a coil, may be applied. In this case, the chopper type charging circuit includes the output coil L
Instead, a reactance element may be provided. When power is supplied from an external device, an electromagnetic wave may be input to the reactance element to generate an electromotive voltage between terminals of the reactance element. (9) In the above-described chopper-type charging circuit, the N-channel FETs N2 and N1 are simultaneously turned on to form a closed loop and store energy in the output coil L. However, the present invention is not limited to this. However, the closed loop may be formed by short-circuiting both ends of the power generation coil, or a closed loop may be formed via a diode, a resistor, or the like.

[0127]

As described above, according to the present invention, it is detected whether or not an AC voltage having a predetermined amplitude or more is generated based on a voltage obtained by double-boosting an AC voltage generated between input terminals. As a result, the AC voltage can be detected early without being affected by noise.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a chopper-type charging circuit used in a wristwatch according to a first embodiment.

FIG. 2 is a circuit diagram of a power generation detection unit of the chopper type charging circuit.

FIG. 3 In the chopper type charging circuit, an N-channel FET N2 ′ is turned on while an N-channel FE is turned on.
Sub-capacitor C when TN1 'is turned off
FIG. 2 is a circuit diagram showing an equivalent circuit of a peripheral device 1 and its peripheral configuration.

FIG. 4 is a timing chart showing respective voltages of an output terminal AG1 and an output terminal AG2 in the equivalent circuit of FIG. 3;

FIG. 5 is a circuit diagram showing a configuration of a Vdd detection unit of the chopper-type charging circuit.

FIG. 6 is a circuit diagram showing a configuration of an AG2 detection circuit of the chopper type charging cycle.

FIG. 7 is a circuit diagram of a sub-capacitor selection unit of the chopper-type charging circuit.

FIG. 8 is a perspective view showing a configuration of an AC generator AG of the same embodiment and a peripheral mechanism thereof.

FIG. 9 is a timing chart showing the operation of the chopper-type charging circuit.

FIG. 10 is a circuit diagram of a chopper-type charging circuit according to a second embodiment.

FIG. 11 is a circuit diagram of a sub-capacitor selection unit of the chopper-type charging circuit.

FIG. 12 is a timing chart showing the operation of the chopper-type charging circuit.

FIG. 13 is a perspective view showing a mechanical structure of an electronically controlled mechanical timepiece according to a modification.

FIG. 14 is a block diagram showing an electrical configuration of an electronically controlled mechanical timepiece according to a modification.

FIG. 15 is a circuit diagram showing a configuration of a conventional charging circuit.

FIG. 16 shows an electromotive voltage VG and a threshold voltage V of a conventional charging circuit.
FIG. 9 is a waveform diagram showing the relationship of D.

FIG. 17 is a flowchart illustrating an operation of the chopper-type charging circuit according to the first embodiment.

FIG. 18 is a flowchart continued from FIG. 17;

FIG. 19 is a flowchart continued from FIG. 17;

FIG. 20 is a continuation of the flowchart in FIG. 17;

FIG. 21 is a flowchart showing an operation of the chopper-type charging circuit according to the second embodiment.

FIG. 22 is a flowchart continued from FIG. 21.

[Explanation of symbols]

7, 7 ': sub-capacitor selection unit (control unit) 10: power generation detection unit (detection means, detection unit) 20: chopper circuit 30: large-capacity capacitor 100: chopper-type charging circuit point AG: alternating current Generators AG1, AG2 ... output terminals (first input terminal, second input terminal) L ... output coils (inductance elements) C1, C2 ... sub-capacitors (first capacitance element, second capacitance element) d1, d2: Diode (first diode, second diode) LL: Low potential side line (line, second line) LH: High potential side line (first line) N1, N2: N-channel FET N1 ' N2 '... N-channel FET P1, P2 ... P-channel FET

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference) 2F084 AA00 BB01 BB09 CC03 GG02 GG04 JJ05 JJ07 5H006 AA04 BB00 CA02 CA12 CA13 CB01 CB07 CC02 DA04 DB01 DC05 HA08 5H410 BB04 CC03 DD02 EA11 EA35 EA38 EB25 EB15 EB15 EB15 EB15 EB15 EB15 EB15 EB15

Claims (23)

[Claims] 1. An AC voltage detection circuit for detecting whether an AC voltage having a predetermined amplitude or more is induced in an inductance element connected between a first input terminal and a second input terminal. A first capacitive element connected to one input terminal; a second capacitive element connected to the second input terminal; and when the induction of an AC voltage is started in the inductance element, the first or second input terminal. While forming a charging path including a capacitive element connected to one of the input terminals,
Charging means for interrupting a charging path including a capacitive element connected to the other input terminal; comparing each voltage of the first input terminal and the second input terminal with a reference voltage; And a detecting means for detecting that an AC voltage is induced in the AC voltage detecting circuit. 2. An AC voltage detection circuit for detecting whether or not an AC voltage having a predetermined amplitude or more is induced in an inductance element connected between a first input terminal and a second input terminal. A first diode connected between one input terminal and the line, a first capacitance element and a first switching element connected between the first input terminal and the line, and a connection between the second input terminal and the line A second diode, a second capacitance element and a second switching element connected between the second input terminal and the line, and a period in which a continuous AC voltage is induced in the inductance element. Alternatively, control is performed such that one of the second switching elements is turned on and the other is turned off, and one of the first and second input terminals is turned off immediately before the end of the period. A control unit configured to control a switching element connected between the input terminal having a lower voltage and the line to be turned on after the end of the period; And a detecting unit for detecting that an AC voltage having a predetermined amplitude or more is induced in the inductance element according to the comparison result. 3. A discharge unit that discharges a charge of an element that is charged when the detection unit detects that an AC voltage is induced by the detection unit in the first or second capacitance element. The AC voltage detection circuit according to claim 2, wherein 4. The discharge unit includes a third switching element connected between the first input terminal and the line, and a fourth switching element connected between the second input terminal and the line. When the detecting section detects that an AC voltage having a predetermined amplitude or more is induced, the third or fourth switching element corresponding to the ON element of the first or second switching element is detected. The AC voltage detection circuit according to claim 3, wherein the switching element is turned on. 5. An AC voltage induced in an inductance element connected between a first input terminal and a second input terminal is rectified to charge a capacitance element connected between the first line and the second line. A first charging circuit connected between the first line and the first input terminal.
A switching element; a second element connected between the first line and the second input terminal;
A switching element, a third switching element and a first diode connected in parallel between the second line and the first input terminal, and a fourth element connected in parallel between the second line and the second input terminal. A switching element and a second diode; a fifth switching element and a first auxiliary capacitance element connected in series between the second line and the first input terminal; and a series between the second line and the second input terminal. A sixth switching element and a second auxiliary capacitance element connected to the first and second input terminals;
A first control unit for controlling on / off of a switching element; comparing each voltage between the first and second input terminals and the second line with a reference voltage; and determining in advance the inductance element according to a comparison result. Detecting that an AC voltage having an amplitude greater than or equal to the predetermined amplitude is induced, a power supply unit for supplying power to the first control unit, and a terminal voltage immediately before the end of a period during which a continuous AC voltage is induced in the inductance element. A second control unit that turns on the fifth or sixth switching element corresponding to the input terminal having a lower voltage after the end of the period. 6. Discharging the charge of the charged element of the first or second capacitive element when it is detected that an AC voltage having a predetermined amplitude or more is induced by the power supply unit. The charging circuit according to claim 5, further comprising a discharging unit. 7. The fifth switching element or the sixth switching element which is turned on at the time when it is detected that an AC voltage having a predetermined amplitude or more is induced by the power supply unit. The charging circuit according to claim 6, wherein the third or fourth switching element corresponding to (c) is turned on. 8. An AC voltage induced in an inductance element connected between a first input terminal and a second input terminal is chopper-boosted in synchronization with a clock signal, and is connected between the first line and the second line. A chopper charging circuit for charging a capacitive element to be connected, wherein a first line connected between the first line and the first input terminal is provided.
A switching element, a first control unit configured to compare a potential of the first line with a potential of the first input terminal, and control on / off of the first switching element based on a comparison result; A second terminal connected between the second input terminals;
A switching element, a second control unit configured to compare a potential of the first line with a potential of the second input terminal, and control on / off of the second switching element based on a comparison result; A third switching element and a first diode connected in parallel between the first input terminals, a potential of the second line and a potential of the first input terminal, and a third switching element based on a comparison result. A third control unit for turning on / off an element in synchronization with the clock signal; a fourth switching element and a second diode connected in parallel between the second line and the second input terminal; and the second line And a fourth control unit that turns on and off the fourth switching element in synchronization with the clock signal based on the comparison result. A fifth switching element and a first auxiliary capacitance element connected in series between a line and the first input terminal; a sixth switching element and a second connection element connected in series between the second line and the second input terminal; An auxiliary capacitance element, comparing each voltage between the first and second input terminals and the second line with a reference voltage, and inducing an AC voltage having a predetermined amplitude or more to the inductance element according to the comparison result. A power supply unit for supplying power to the first to fourth control units after the detection unit detects that an AC voltage having a predetermined amplitude or more is induced, Immediately before the end of the period in which the continuous AC voltage is induced in the inductance element, the fifth or sixth switching element corresponding to the input terminal having the lower terminal voltage is turned on after the end of the period. Chopper charging circuit, characterized in that an auxiliary capacitor element selection unit for. 9. Discharging an electric charge of an element of the first or second auxiliary capacitance element that is charged at the time when the detection unit detects that an AC voltage having a predetermined amplitude or more is induced. The chopper charging circuit according to claim 8, further comprising a discharging unit that performs charging. 10. The fifth or sixth switching element which is turned on at the time when the detecting section detects that an AC voltage having a predetermined amplitude or more is induced by the detecting section. 10. The chopper charging circuit according to claim 9, wherein the chopper charging circuit is turned on / off in synchronization with turning on / off of the third or fourth switching element corresponding to the element. 11. The electric charge stored in the first or second auxiliary capacitance element is transferred to the capacitance element when the detection unit detects that an AC voltage having a predetermined amplitude or more is induced. 9. The chopper charging circuit according to claim 8, further comprising a transfer unit that performs the transfer. 12. The transfer means includes a seventh switching element connected between the first line and the first input terminal, and an eighth switching element connected between the first line and the second input terminal. The seventh and the eighth switching elements are simultaneously turned on and off for a certain period after the detection unit detects that an AC voltage having a predetermined amplitude or more is induced, and One of the fifth or sixth switching element corresponding to the second capacitor element having no charge stored therein is turned off, and the other switching element is turned on complementarily with the seventh and eighth switching elements. The chopper charging circuit according to claim 11, wherein the chopper charging circuit is turned off. 13. The power supply unit according to claim 8, wherein the power supply unit starts supplying power to the first and second control units after supplying power to the third and fourth control units. Chopper charging circuit. 14. The power supply unit, after supplying power to the third and fourth control units, turns on / off the third or fourth switching element by the third or fourth control unit.
14. The chopper charging circuit according to claim 13, wherein upon detecting that the off control has been started, power supply to the first and second control units is started. 15. The first line is a power line,
9. The chopper charging circuit according to claim 8, wherein the second line is a ground. 16. The chopper charging circuit according to claim 8, wherein the first line is a ground, and the second line is a power supply line. 17. The current consumption of the detection unit is lower than the current consumption of the third and fourth control units, and the current consumption of the third and fourth control units is reduced by the current consumption of the first and second control units. 9. The chopper charging circuit according to claim 8, wherein the setting is made lower than the above. 18. An electronic device comprising the chopper charging circuit according to claim 8 and being operated by electric power supplied from the chopper charging circuit. 19. A timing device comprising: the chopper charging circuit according to claim 8; and a clock circuit that is supplied with power from the chopper charging circuit and measures time. 20. An AC voltage having a predetermined amplitude or more is applied to an inductance element inserted between a first input terminal to which the first capacitance element is connected and a second input terminal to which the second capacitance element is connected. In the AC voltage detection method for detecting whether or not the induction is performed, when the induction of the AC voltage is started in the inductance element, the method includes a capacitance element connected to one of the first or second input terminals. While forming a charging path,
A charging path including a capacitive element connected to the other input terminal is cut off, each voltage of the first input terminal and the second input terminal is compared with a reference voltage, and an AC voltage is applied to the inductance element according to a comparison result. AC voltage detection method characterized by detecting that a voltage is induced. 21. A first diode connected between a first input terminal and a line, a first capacitance element and a first switching element connected between the first input terminal and the line, a second input terminal, A second diode connected between lines, and a detection circuit including a second input terminal and a second capacitive element and a second switching element connected between the lines; An AC voltage detection method for detecting whether or not an AC voltage having a predetermined amplitude or more is induced in an inductance element connected between two input terminals, wherein a continuous AC voltage is induced in the inductance element. During one period, one of the first and second switching elements is turned on and the other is turned off, and the terminal voltage of the first and second input terminals is shortly before the end of the period. A switching element connected between one of the input terminals and the line is turned on after the end of the period, and each voltage of the first input terminal and the second input terminal is compared with a reference voltage. An AC voltage detecting method for detecting that an AC voltage having a predetermined amplitude or more is induced in an inductance element. 22. A first switching element connected between a first line and a first input terminal; a second switching element connected between the first line and a second input terminal; A third terminal connected in parallel between the first input terminals;
A switching element and a first diode; a fourth switching element and a second diode connected in parallel between the second line and the second input terminal; and a serial connection between the second line and the first input terminal. A charging circuit including a fifth switching element and a first auxiliary capacitance element, and a sixth switching element and a second auxiliary capacitance element connected in series between the second line and the second input terminal. Rectifying an AC voltage induced in an inductance element connected between the first input terminal and the second input terminal to charge a capacitance element connected between the first line and the second line. A charging method for comparing each voltage between the first and second input terminals and the second line with a reference voltage, and determining a predetermined voltage for the inductance element according to a comparison result. Detects that the width or of the AC voltage is induced, after the detection, and the potentials of the first and second lines,
On / off of the first to fourth switching elements is controlled based on each potential of the first and second input terminals, and immediately before the end of a period in which a continuous AC voltage is induced in the inductance element. A charging method, wherein the fifth or sixth switching element corresponding to the input terminal having a lower terminal voltage is turned on after the end of the period. 23. A first switching element connected between a first line and a first input terminal, a potential of the first line and a potential of the first input terminal are compared, and the first switching element is connected based on a comparison result. First to control ON / OFF of the switching element
A control unit, a second switching element connected between the first line and the second input terminal, and comparing the potential of the first line with the potential of the second input terminal; A second control unit that controls on / off of a switching element; a third switching element and a first diode connected in parallel between the second line and the first input terminal; a potential of the second line; Comparing the potential of the first input terminal and turning on / off the third switching element in synchronization with the clock signal based on the comparison result;
A control unit, a fourth switching element and a second diode connected in parallel between the second line and the second input terminal, and comparing the potential of the second line with the potential of the second input terminal; A fourth control unit for turning on / off the fourth switching element in synchronization with the clock signal based on the result; a fifth switching element connected in series between the second line and the first input terminal; The first input terminal using a chopper charging circuit including a first auxiliary capacitance element, a sixth switching element connected in series between the second line and the second input terminal, and a second auxiliary capacitance element; An AC voltage induced in an inductance element connected between the first line and the second input terminal is chopper-boosted in synchronization with the clock signal, and is connected between the first line and the second line. A chopper charging method for charging a capacitance element, comprising: comparing each voltage between the first and second input terminals and the second line with a reference voltage; and determining a predetermined amplitude for the inductance element according to a comparison result. After detecting that the AC voltage is induced, the detecting unit detects that an AC voltage having a predetermined amplitude or more is induced, and then supplies power to the first to fourth control units. Immediately before the end of a period in which a continuous AC voltage is induced in the inductance element, the fifth or sixth switching element corresponding to the input terminal having the lower terminal voltage is turned on after the end of the period. Chopper charging method.