JP2001196553A - Semiconductor storage and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor storage that has a layered capacitor, where the capacitance of a capacitor is increased without having to increase the height of a storage node. SOLUTION: A storage node plug 13 projects from the surface of a silicon nitride film 11 in an opening part OP1, storage nodes 14 are provided so that the projecting is covered, and two storage nodes 14 are electrically connected to source and drain regions 71 and 73, respectively. The storage nodes 14 are provided, so that the inner surface of the opening part OP1 is also covered. A dielectric film 15 is provided with the storage nodes 14 being covered. A self plate 16 is provided so that the dielectric film 15 is covered. The storage nodes 14 are provided merely in the opening part OP1, and adjacent storage nodes are isolated electrically from one another.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly, to a semiconductor memory device having an increased capacitance of a capacitor and a method of manufacturing the same.

[0002]

2. Description of the Related Art Semiconductor memory devices, especially dynamic RA
In M (DRAM), as the degree of integration and capacity increase, the memory cell 3
Dimensions are being developed. This structure for three-dimensional memory cells is eliminated as the DRAM generation progresses,
It is being integrated into stacked capacitors and trench capacitors.

[0003] In contrast to a trench capacitor in which a groove is provided in a silicon substrate and the capacitance of the capacitor is to be ensured by its depth, a stacked capacitor is provided so that capacitors are stacked on a silicon substrate. However, the height of the capacitor is intended to secure the capacitance of the capacitor. Typical examples include a thick film stacked capacitor and a cylindrical capacitor. Among these stacked capacitor cells, the configuration of a thick film stacked capacitor will be described with reference to FIG. Note that FIG. 18 is a partial cross-sectional view of the memory cell portion MR of the semiconductor memory device and a peripheral circuit portion PR such as a sense amplifier and a decoder provided around the memory cell portion MR.

In FIG. 18, a field oxide film 52 is selectively provided in a silicon substrate 1, and a gate oxide film 51 is provided on a silicon substrate which is not covered with the field oxide film 52. A gate electrode 61 is selectively provided on the film 51. A transfer gate 62 is provided above the field oxide film 52. In the surface of the silicon substrate 1 on both sides of the gate electrode 61, source / drain regions 71 and 72 are provided in the memory cell portion MR, and source / drain layers 91 and 92 are provided in the peripheral circuit portion PR. I have. On the main surface of the silicon substrate 1, interlayer insulating films 3, 4, and 8 are sequentially stacked.

In the memory cell portion MR, a contact hole 82 penetrating through the interlayer insulating film 3 and the gate oxide film 51 is provided so as to reach the source / drain region 71, and a conductor layer 83 is buried in the contact hole 82. Bit line 81 connected to conductor layer 83 is provided on interlayer insulating film 3, and bit line 81 is electrically connected to source / drain region 71.

A contact hole 32 penetrating through the interlayer insulating films 4 and 3 and the gate oxide film 51 is provided so as to reach the source / drain region 72, and a conductor layer 33 is buried in the contact hole 32. Interlayer insulating film 4
A storage node 34 connected to the conductor layer 33 is provided above. Then, a dielectric film 35 is provided so as to cover the storage node 34, and an opposite electrode (referred to as a cell plate) 36 for the storage node 34 is provided so as to cover the dielectric film 35.
C. Here, the storage node 34
It has a thickness of 500 nm to 1000 nm, and is the origin of the “thick film”.

An interlayer insulating film 8 is provided on interlayer insulating film 4 so as to cover stacked capacitor SC, and a wiring layer 39 is provided on interlayer insulating film 8. Wiring layer 3
9 is disposed at a step portion of the interlayer insulating film 8, and the wiring layer 39 is formed in a conductor layer 37 buried in a contact hole 37 penetrating the interlayer insulating film 8 and reaching the cell plate 36. It is connected to the.

In the peripheral circuit portion PR, a contact hole 41 penetrating through the interlayer insulating films 8, 4, and 3 and the gate oxide film 51 is provided so as to reach the source / drain regions 91 and 92. A conductor layer 42 is buried in the conductor layer 4 on the interlayer insulating film 8.
2 is provided.

[0009]

The problem here is the presence of a step in the memory cell section MR and the peripheral circuit section PR. Since the stacked capacitor SC is provided on the interlayer insulating film 4 in the memory cell portion MR, the height of the outermost surface of the interlayer insulating film 8 when the stacked capacitor SC is covered with the interlayer insulating film 8 and flattened Is a peripheral circuit unit PR
Is higher than the height of the outermost surface of the interlayer insulating film 8 in FIG.
The height difference is substantially equal to the height of the stacked capacitor SC. As the height of the stacked capacitor SC increases, the height difference between the memory cell unit MR and the peripheral circuit unit PR increases.

As the integration and capacity of the semiconductor memory device increase, the capacitance of the capacitor must be increased. To achieve this, the height of the stacked capacitor SC as shown in FIG. However, if the height of the stacked capacitor SC is increased, the height difference between the memory cell portion MR and the peripheral circuit portion PR becomes large, and if the size exceeds the focus margin in photolithography, Wiring arrangement by plate making becomes extremely difficult.

When the height difference becomes large, the wiring layer 39
It is difficult to dispose the wire at the stepped portion, and wiring failure such as disconnection is likely to occur. Therefore, it is essential to reduce the height difference as much as possible. Such a problem also applies to a cylindrical capacitor.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and it is an object of the present invention to provide a semiconductor memory device having a stacked capacitor in which the capacitance of a capacitor is increased without increasing the height of a storage node. With the goal.

[0013]

According to a first aspect of the present invention, there is provided a semiconductor memory device comprising: a lower electrode provided on a base layer formed on a semiconductor substrate; A semiconductor memory device having a stacked capacitor including a dielectric film provided and an upper electrode provided so as to cover the dielectric film, wherein one end of the lower electrode has the semiconductor substrate. The other end side is electrically connected to the semiconductor substrate by a conductor plug disposed through the underlayer so as to protrude above the underlayer,
The lower electrode is provided so as to cover a protruding portion of the plug, and has the covering portion as a protruding portion.

According to a second aspect of the present invention, in the semiconductor memory device, the stacked capacitor is provided so as to penetrate an insulating film provided on the underlayer, and a surface of the underlayer becomes a bottom surface. The plug protrudes from the bottom surface, and the lower electrode is disposed so as to cover the bottom surface and the wall surface of the opening.

According to a third aspect of the present invention, in the semiconductor memory device, the plug is provided such that a height of a protruding portion thereof is lower than a height of a wall surface of the opening.

5. The semiconductor memory device according to claim 4, wherein said lower electrode has said protruding portion and forms a central portion of said lower electrode, and an edge portion of said bottom lower electrode. And a side wall lower electrode extending in a direction perpendicular to the main surface of the underlayer.

According to a fifth aspect of the present invention, in the semiconductor memory device, the plug is provided such that the height of the protruding portion is lower than the height of the side wall lower electrode.

According to a sixth aspect of the present invention, in the method of manufacturing a semiconductor memory device, the lower electrode is provided on the base layer formed on the semiconductor substrate, and the lower electrode is provided so as to cover the lower electrode. A method for manufacturing a semiconductor memory device having a stacked capacitor including a dielectric film and an upper electrode provided so as to cover the dielectric film, wherein the underlayer is prepared, and (A) forming an insulating film, (b) forming a contact hole penetrating the base layer and the insulating film and reaching the semiconductor substrate, and filling the contact hole, one end of which is (C) forming a conductor plug so as to be electrically connected to the semiconductor substrate; and selectively removing the insulating film, the surface of the underlayer serves as a bottom surface, and the other end of the plug serves as the bottom surface. The opening protruding from Forming step (d), covering the bottom electrode, the wall surface of the opening and the protruding portion of the plug with the conductor layer, and covering the lower portion with the protruding portion covering the protruding portion of the plug. Forming process
(e).

The method of manufacturing a semiconductor memory device according to claim 7, wherein the step (c) includes a step of etching the plug until the other end is recessed in the contact hole. I have.

The method of manufacturing a semiconductor memory device according to claim 8, wherein the step (a) comprises the step of preparing the underlayer whose uppermost layer is a silicon nitride film; Forming a silicon oxide film, wherein the step (d) includes a step of removing the insulating film by etching, and using the silicon nitride film as an etching stopper when removing the insulating film. .

According to a ninth aspect of the present invention, in the method of manufacturing a semiconductor memory device, the lower electrode is provided on the base layer formed on the semiconductor substrate, and the lower electrode is provided so as to cover the lower electrode. A method for manufacturing a semiconductor memory device having a stacked capacitor including a dielectric film and an upper electrode provided so as to cover the dielectric film, wherein the underlayer is prepared, and Step (a) of forming a first insulating film
Forming a contact hole that penetrates the base layer and the first insulating film and reaches the semiconductor substrate.
(b), a step of burying the contact hole and forming a conductor plug so that one end thereof is electrically connected to the semiconductor substrate, and (c) a step of completely covering the first insulating film. Removing (d) exposing the base layer to expose the other end side of the plug from the bottom surface; and covering the projecting portion of the plug with the covering portion serving as a projecting portion. (E) forming a layer, and after covering the first conductor layer with a second insulating film, a predetermined portion of the first conductor layer centered on the protrusion, and Selectively removing the second insulating film and the first conductor layer so that a second insulating film remains, and forming a bottom lower electrode constituting a central portion of the lower electrode; At least the bottom lower electrode and the second insulating film remaining on the bottom lower electrode. After the second conductive layer is formed, the second conductive layer is removed by anisotropic etching, and the second conductive layer is left on the bottom lower electrode and the side surface of the second insulating film remaining thereon. (G) forming a side wall lower electrode which is provided so as to surround an end surface of the bottom lower electrode and extends in a direction perpendicular to the main surface of the underlayer.

11. The method of manufacturing a semiconductor memory device according to claim 10, wherein in the step (f), the thickness of the second insulating film is equal to or greater than the thickness of the first insulating film. Contains.

12. The method of manufacturing a semiconductor memory device according to claim 11, wherein the step (a) comprises the step of preparing the underlayer whose uppermost layer is a silicon nitride film; Forming a silicon oxide film, wherein the step (d) includes a step of removing the first insulating film by etching, and when removing the first insulating film, etching the silicon nitride film with an etching stopper. Used as
The step (f) includes a step of removing the second insulating film and the first conductor layer by etching;
In removing the insulating film and the first conductor layer, the silicon nitride film is used as an etching stopper.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS <A. First Embodiment><A-1. Device Configuration> FIG. 1 is a sectional view illustrating a configuration of a memory cell portion of a semiconductor memory device 100 according to a first embodiment of the present invention.

In FIG. 1, a field oxide film 52 is selectively provided in a silicon substrate 1, and a gate oxide film 51 is provided on a silicon substrate which is not covered with the field oxide film 52. Gate electrodes 61 and 61A are selectively provided on film 51. A transfer gate 6 is formed on the field oxide film 52.
2 are provided. The source / drain layers 71 are provided on the surface of the silicon substrate 1 on both sides of the gate electrode 61.
Source and drain layers 72 and 73 are provided in the surface of the silicon substrate 1 on both sides of the gate electrode 61A. On the main surface of the silicon substrate 1, interlayer insulating films 3 and 4 each composed of a silicon oxide film are sequentially laminated, and a silicon nitride film 11 is provided on the interlayer insulating film 4; TEOS (tetra ethyl
An interlayer insulating film 5 composed of an orthosilicate oxide film is provided.

On the silicon nitride film 11, a storage node 14 is formed in the two openings OP1 of the interlayer insulating film 5.
(Lower electrode), dielectric film 1 composed of silicon oxide film
Capacitor SC provided with cell plate 16 (upper electrode) made of silicon and doped polysilicon
1 is provided.

In the interlayer insulating film 3, the source
A contact hole 82 penetrating the interlayer insulating film 3 and the gate oxide film 51 is provided so as to reach the drain region 72, a conductor layer 83 is buried in the contact hole 82, and a conductor layer 83 is formed on the interlayer insulating film 3. A bit line 81 connected to 83 is provided, and the bit line 81 and the source / drain region 72 are electrically connected.

The source / drain regions 71 and 7
3, two contact holes 12 penetrating through the silicon nitride film 11, the interlayer insulating films 4, 3 and the gate oxide film 51 are provided.
Each of the conductors 2 is buried in the plug 2 to form a plug. This is called a storage node plug 13.

Each storage node plug 13
Protrudes from the surface of silicon nitride film 11 in opening OP1, storage nodes 14 are provided to cover the protruding portions, respectively, and two storage nodes 14 are connected to source / drain regions 71 and 7, respectively.
3 is electrically connected.

Storage node 14 is provided so as to cover the inner surface of opening OP 1, dielectric film 15 is provided so as to cover storage node 14, and cell plate 16 is provided so as to cover dielectric film 15. Has been established. Note that the storage nodes 14 are provided only in the openings OP1, and the adjacent storage nodes 14 are electrically separated from each other. Note that the structure of the stacked capacitor SC1 is a structure called an interior cylindrical type (interior type).

<A-2. Manufacturing Method> Next, a method of manufacturing the semiconductor memory device 100 will be described with reference to FIGS.

First, as shown in FIG.
A field oxide film 52 is selectively formed thereon, and a gate oxide film 51 is formed on a silicon substrate not covered with the field oxide film 52. Then, gate electrodes 61 and 61A are selectively formed on the gate oxide film 51. At this time, a transfer gate 62 is formed on the field oxide film 2 in the same step as the gate electrode 61.

Using the gate electrodes 61 and 61A as a mask, impurity ions are implanted to selectively form the source / drain regions 71, 72 and 73.

Next, a TEOS oxide film is formed over the entire surface by, for example, a CVD method, and is flattened to form an interlayer insulating film 3 having a thickness of about 500 nm.

Next, a contact hole 82 is formed to reach the source / drain region 72 through the interlayer insulating film 3 and the gate oxide film 51 so as to reach the source / drain region 72. As the bit line forming conductor layer is formed over the entire surface of the interlayer insulating film 3, the bit line forming conductor layer, for example, doped polysilicon doped with impurities at a high concentration is also provided in the contact hole 82. And a conductor layer 83 is formed. Then, the bit line 81 is formed through the steps of photolithography and etching.

Thereafter, a TEOS oxide film is formed over the entire surface of the interlayer insulating film 3 by, for example, the CVD method, and is flattened to form an interlayer insulating film 4 having a thickness of about 200 nm.

Then, a silicon nitride film 11 having a thickness of about 50 nm is formed on the interlayer insulating film 4 by, for example, a CVD method.
Forming a TEOS oxide film of about 00 nm to form an interlayer insulating film 5
And

Next, in the step shown in FIG. 3, a contact hole 12 penetrating through interlayer insulating film 5, silicon nitride film 11, interlayer insulating films 4 and 3, and gate oxide film 51 and reaching source / drain regions 71 and 73 is formed. Form. Then, a doped polysilicon layer 131 into which impurities are introduced at a high concentration is formed on the interlayer insulating film 5 by, for example, a CVD method, and the doped polysilicon layer 131 is embedded in the contact hole 12. Note that doped amorphous silicon may be used instead of doped polysilicon.

Next, in the step shown in FIG. 4, the doped polysilicon layer 131 on the interlayer insulating film 5 is removed by etching, and the doped polysilicon layer 131 in the contact hole 12 is also etched to a predetermined level. A storage node plug 13 having a height is formed. The doped polysilicon layer 131 in the contact hole 12
May not be etched.

Next, in the step shown in FIG. 5, an opening O for forming the stacked capacitor SC1 (FIG. 1) is formed.
A resist mask RM1 having an opening pattern for forming P1 is formed on interlayer insulating film 5, and interlayer insulating film 5 is selectively removed by etching to form opening OP1 having silicon nitride film 11 exposed at the bottom. Form.

The etching conditions are set such that the etching selectivity of the interlayer insulating film 5 (TEOS oxide film) to the silicon nitride film 11 is 10 or more.
The silicon nitride film 11 is used as an etching stopper.

In this etching, the storage node plug 13 is not etched, but projects vertically from the surface of the silicon nitride film 11, that is, the bottom of the opening OP1.

Next, in the step shown in FIG. 6, impurities are covered so as to cover the interlayer insulating film 5, the inner wall surface of the opening OP1, and the surface of the protruding storage node plug 13, and the covering portion becomes a protruding portion. Thickness 20- introduced at high concentration
A doped polysilicon layer 141 of about 50 nm is formed. Note that doped amorphous silicon may be used instead of doped polysilicon.

Subsequently, in the step shown in FIG. 7, the doped polysilicon layer 141 formed on the interlayer insulating film 5 is removed, and the doped polysilicon layer 1 is formed only in the opening OP1.
The storage node 14 is formed leaving 41. In addition,
Removal of the doped polysilicon layer 141 is performed by CMP (Chem).
removal by mechanical mechanical polishing) and opening O
A method in which an insulator is buried in P1 and the doped polysilicon layer 141 on the interlayer insulating film 5 is removed by etching.

Thereafter, a silicon oxide film is formed to a thickness of about 10 nm, for example, to cover the storage node 14 to form a dielectric film 15, and a high concentration of impurities is introduced to cover the dielectric film 15. By forming a doped polysilicon layer having a thickness of about 100 to 150 nm to form the cell plate 16, the configuration of the semiconductor memory device 100 shown in FIG. 1 is obtained.

<A-3. Operation and Effect> In the semiconductor memory device 100 described above, the storage node plug 13 connected to the source / drain region projects from the surface of the silicon nitride film 11 forming the bottom surface of the opening OP1 for forming the stacked capacitor SC1. Since the storage node 14 is formed so as to cover the protruding portion and the covering portion becomes a protruding portion, the surface area of the storage node 14 increases due to the presence of the protruding portion, and the capacitance of the stacked capacitor SC1 increases. Increase. as a result,
It is no longer necessary to increase the height of the storage node to increase the capacitance, reduce the height difference between the memory cell section and the peripheral circuit section, and prevent wiring from exceeding the focus margin in photolithography. The arrangement can be facilitated, and even if the wiring layer is arranged in the stepped portion, it is possible to suppress the occurrence of wiring failure such as disconnection.

The storage node plug 13 is formed separately from the storage node 14 and its height can be set arbitrarily. Therefore, according to the height of the protruding portion of the storage node plug 13, the stacked capacitor SC1
Can be set arbitrarily, and the storage node plug 13 can be prevented from being structurally fragile due to an excessively high protruding portion.

<B. Second Embodiment><B-1. Device Configuration> FIG. 8 is a sectional view illustrating a configuration of a memory cell portion of a semiconductor memory device 200 according to a second embodiment of the present invention.

In FIG. 8, the same components as those of semiconductor memory device 100 described with reference to FIG. 1 are denoted by the same reference numerals, and redundant description will be omitted.

In FIG. 8, source / drain regions 71
And 73, two contact holes 22 penetrating through the silicon nitride film 11, the interlayer insulating films 4, 3 and the gate oxide film 51 are arranged, and a conductor is embedded in each of the two contact holes 22. It looks like a plug. This is called a storage node plug 23.

Each storage node plug 23
Are provided with two bottom storage nodes 24 (bottom lower electrodes) that protrude from the main surface of the silicon nitride film 11 and cover the protruding portions and extend to the main surface of the silicon nitride film 11. The two bottom storage nodes 24 are electrically connected to the source / drain regions 71 and 73, respectively.

Around the bottom storage node 24, a side wall storage node 25 (side wall lower electrode) that is in close contact with the end surface of the bottom storage node 24 and extends in a direction perpendicular to the main surface of the silicon nitride film 11.
Is provided, and the storage node SN (lower electrode) is formed by the bottom storage node 24 and the side wall storage node 25.
Is composed. Note that adjacent sidewall storage nodes 25 are electrically separated.

A dielectric film 26 is provided so as to cover bottom storage node 24 and side wall storage node 25, and a cell plate 27 (upper electrode) is provided so as to cover dielectric film 26. The stacked capacitor SC2 is formed by the node 24, the side wall storage node 25, the dielectric film 26 and the cell plate 27.
Is configured.

Incidentally, the structure of the stacked capacitor SC2 is a structure called an exterior type.

<B-2. Manufacturing Method> Next, a method of manufacturing the semiconductor memory device 200 will be described with reference to FIGS.

The structure below the silicon nitride film 11 is the same as that of the semiconductor memory device 20 described with reference to FIG.
Since it is formed in the same step as 0, the description is omitted.

First, as shown in FIG. 9, a silicon nitride film 11 having a thickness of about 50 nm is formed on the interlayer insulating film 4 by, for example, a CVD method, and a TEOS film having a thickness of about 1000 to 2000 nm is further formed on the silicon nitride film 11. An insulating film is formed by forming an oxide film.

Next, a contact hole 22 penetrating through the insulating film 6, the silicon nitride film 11, the interlayer insulating films 4 and 3, and the gate oxide film 51 to reach the source / drain regions 71 and 73 is formed. Then, a doped polysilicon layer 231 in which impurities are introduced at a high concentration is formed on the interlayer insulating film 5 by, for example, a CVD method, and the doped polysilicon layer 231 is embedded in the contact hole 22. Note that doped amorphous silicon may be used instead of doped polysilicon.

Next, in a step shown in FIG. 10, the doped polysilicon layer 231 on the insulating film 6 is removed by etching to leave the doped polysilicon layer 231 in the contact hole 22 and the storage polysilicon layer 231 is removed. 23.

Next, in the step shown in FIG. 11, the insulating film 6 is removed by etching to expose the silicon nitride film 11 entirely.

In this etching, etching conditions are set such that the etching selectivity of the insulating film 6 (TEOS oxide film) to the silicon nitride film 11 becomes 10 or more, and the silicon nitride film 11 is used as an etching stopper.

In this etching, the storage node plug 23 is not etched, but protrudes from the surface of the silicon nitride film 11 by the thickness of the insulating film 6.

Next, in the step shown in FIG. 12, the insulating layer 6 and the surface of the protruding storage node plug 23 are covered, and the thickness of the impurity-doped layer 50 is increased to 50% so that the covering portion becomes a protruding portion. A doped polysilicon layer 241 of about 100 nm is formed. Note that doped amorphous silicon may be used instead of doped polysilicon.

Subsequently, in the step shown in FIG. 13, TEOS is so formed as to entirely cover the doped polysilicon layer 241.
An oxide film is formed and planarized to a thickness of 1000 to 20.
An insulating film 171 of about 00 nm is formed.

Next, in a step shown in FIG. 14, a resist mask RM2 having an opening pattern for defining the size of the bottom storage node 24 is formed on the insulating film 171, and the insulating film 171 and the doped polysilicon layer are etched by etching. 241 is selectively removed to form a bottom storage node 24.

In this etching, the etching selectivity of the insulating film 171 (TEOS oxide film) and the doped polysilicon layer 241 to the silicon nitride film 11 is 1 respectively.
The etching conditions are set so as to be 0 or more, and the silicon nitride film 11 is used as an etching stopper. The insulating film 171 and the doped polysilicon layer 241
May be removed in a separate etching step.

The insulating film 171 remains on the bottom storage node 24, and the side wall storage node 25 (FIG. 8)
(See FIG. 1) is formed as a storage node core 17 functioning as a core material.

Subsequently, after the resist mask RM2 on the storage node core 17 is removed, in the step shown in FIG.
20 to 50 n thick with high concentration of impurities introduced by the method
An about m doped polysilicon layer 251 is formed. The doped polysilicon layer 251 is formed on the storage node core 17.
It is also formed on the side and top. Note that doped amorphous silicon may be used instead of doped polysilicon.

Next, in the step shown in FIG. 16, the doped polysilicon layer 251 is selectively removed by anisotropic etching such as ion-assisted etching. In this case, the doped polysilicon layer 251 on the storage node core 17 and the silicon nitride film 11 is removed, but the side wall storage node 2
Remains as 5.

Next, the storage node core 17 is removed by isotropic etching such as wet etching, and FIG.
As shown in FIG. 7, a dielectric film 26 is formed by forming, for example, a silicon oxide film to a thickness of about 10 nm so as to cover the bottom storage node 24 and the side wall storage node 25. Note that the storage node core 17 may be removed by dry etching.

Thereafter, a doped polysilicon layer having a thickness of about 100 to 150 nm in which impurities are introduced at a high concentration so as to cover the dielectric film 26 is formed to form the cell plate 27, thereby forming the semiconductor memory shown in FIG. The configuration of the device 200 is obtained.

In the above description, the protruding storage node plug 23 is
1 and further covered by the insulating film 171, the height of the protrusion of the bottom storage node 24 is lower than that of the side wall storage node 25. However, depending on how the insulating film 171 is formed, Although the height of the protruding portion of the storage node 24 can be made the same as that of the side wall storage node 25, considering the strength of the storage node plug 23, a lower height is advantageous in strength.

<B-3. Operation and Effect> In the semiconductor memory device 200 described above, the storage node plug 23 connected to the source / drain region protrudes from the surface of the silicon nitride film 11 and covers the protruding portion, and the covering portion becomes a protruding portion. The bottom storage node 24 is formed as described above, the surface area of storage node SN including sidewall storage node 25 increases due to the presence of the protrusion, and stacked capacitor SC2 is formed.
Increase in capacitance. As a result, it is not necessary to increase the height of the storage node in order to increase the capacitance, and the height difference between the memory cell portion and the peripheral circuit portion is reduced,
In addition to preventing a state in which the focus margin is exceeded in photolithography, wiring can be easily arranged, and even if a wiring layer is provided in a step portion, occurrence of wiring failure such as disconnection can be suppressed.

The storage node plug 23 is formed separately from the bottom storage node, and its height can be set arbitrarily.
Depending on the height of the protruding portion of the stacked capacitor SC
2 can be arbitrarily set, and the storage node plug 23 can be prevented from being structurally fragile due to an excessively high protruding portion.

[0075]

According to the semiconductor memory device of the first aspect of the present invention, the plug for electrically connecting the lower electrode of the stacked capacitor and the semiconductor substrate protrudes above the underlayer, and the protruding portion protrudes. Since the lower electrode covers the portion and the lower electrode has a protrusion, the surface area of the lower electrode increases, and the capacitance of the stacked capacitor increases. As a result, it is not necessary to increase the height of the stacked capacitor in order to increase the capacitance, the height difference between the portion having the stacked capacitor and the portion not having the stacked capacitor in the semiconductor memory device is reduced, and the focus margin in photolithography is reduced. Is prevented, and, for example, wiring can be easily arranged, and even if a wiring layer is provided in a step portion, occurrence of wiring failure such as disconnection can be suppressed.

According to the semiconductor memory device of the present invention, the lower electrode covers the bottom surface of the opening and the wall surface of the opening provided in the insulating film provided on the base layer. In the arranged stacked capacitor called a hollow cylindrical type, since it has a projection formed by covering the plug, the surface area of the lower electrode is smaller than that of a general hollow cylindrical stacked capacitor. Will increase.

According to the semiconductor memory device of the third aspect of the present invention, when arranging a plurality of stacked capacitors, the connection between the adjacent lower electrodes is broken, that is, the insulating film formed in the manufacturing process It is necessary to remove the lower electrode material on the main surface of the plug, but since the height of the protruding portion of the plug is lower than the height of the wall surface of the opening, the protruding portion of the lower electrode is also removed in the above operation. Is prevented.

According to the semiconductor memory device of the fourth aspect of the present invention, the bottom lower electrode constituting the central portion of the lower electrode and the edge portion of the bottom lower electrode are provided so as to surround the lower portion. In a stacked capacitor called a residual cylindrical type having a sidewall lower electrode extending in a direction perpendicular to the surface, since the bottom lower electrode has a protrusion formed by covering the plug, The surface area of the lower electrode is increased as compared with a general remaining cylindrical stacked capacitor.

According to the semiconductor memory device of the fifth aspect of the present invention, since the height of the protruding portion of the plug is lower than the height of the side wall lower electrode, it is possible to prevent the structure from becoming weak.

According to the method of manufacturing a semiconductor memory device according to the sixth aspect of the present invention, the lower electrode is formed on the bottom surface of the opening provided in the insulating film provided on the base layer and on the wall surface of the opening. In a stacked capacitor called a hollow cylindrical type which is disposed so as to cover together, a structure in which the lower electrode has a projection formed by covering the plug, the surface area of the lower electrode increases, and the stacked capacitor Can be obtained. Also, the plug and the lower electrode are formed separately, and the height of the plug can be set arbitrarily, so that the capacitance of the stacked capacitor can be set arbitrarily according to the height of the protruding portion of the plug. In addition, it is possible to prevent the protruding portion of the plug from becoming too high and becoming structurally weak.

According to the method of manufacturing a semiconductor memory device according to claim 7 of the present invention, it is possible to obtain a semiconductor memory device in which the height of the protruding portion of the plug is lower than the height of the wall surface of the opening. it can.

According to the method of manufacturing a semiconductor memory device of the present invention, since the silicon nitride film is used as an etching stopper in forming the opening, over-etching can be prevented.

According to the method of manufacturing a semiconductor memory device according to the ninth aspect of the present invention, the bottom lower electrode constituting the central portion of the lower electrode and the end surface of the bottom lower electrode are disposed so as to surround the bottom surface. In a stacked capacitor called a residual cylindrical type having a sidewall lower electrode extending in a direction perpendicular to the main surface, the bottom lower electrode has a protrusion having a configuration formed by covering a plug, A semiconductor memory device in which the surface area of the electrode increases and the capacitance of the stacked capacitor increases can be obtained. Also, the plug and the lower electrode are formed separately, and the height of the plug can be set arbitrarily.
The capacitance of the stacked capacitor can be arbitrarily set, and the protruding portion of the plug can be prevented from becoming too high to be structurally weak.

According to the method for manufacturing a semiconductor memory device according to the tenth aspect of the present invention, it is possible to obtain a semiconductor memory device in which the height of the protruding portion of the plug is lower than the height of the sidewall lower electrode. .

According to the method of manufacturing a semiconductor memory device of the present invention, when removing the first insulating film, and removing the second insulating film and the first conductor layer, the silicon nitride film is used as an etching stopper. , It can prevent over-etching.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration of a semiconductor memory device according to a first embodiment of the present invention;

FIG. 2 is a diagram illustrating a manufacturing process of the semiconductor memory device according to the first embodiment of the present invention;

FIG. 3 is a diagram illustrating a manufacturing process of the semiconductor memory device according to the first embodiment of the present invention;

FIG. 4 is a diagram illustrating a manufacturing process of the semiconductor memory device according to the first embodiment of the present invention;

FIG. 5 is a diagram illustrating a manufacturing process of the semiconductor memory device according to the first embodiment of the present invention;

FIG. 6 is a diagram illustrating a manufacturing process of the semiconductor memory device according to the first embodiment of the present invention;

FIG. 7 is a diagram illustrating a manufacturing process of the semiconductor memory device according to the first embodiment of the present invention;

FIG. 8 is a diagram illustrating a configuration of a semiconductor memory device according to a second embodiment of the present invention;

FIG. 9 is a diagram illustrating a manufacturing process of the semiconductor memory device according to the second embodiment of the present invention;

FIG. 10 is a diagram illustrating a manufacturing process of the semiconductor memory device according to the second embodiment of the present invention;

FIG. 11 is a diagram illustrating a manufacturing process of the semiconductor memory device according to the second embodiment of the present invention;

FIG. 12 is a diagram illustrating a manufacturing process of the semiconductor memory device according to the second embodiment of the present invention;

FIG. 13 is a diagram illustrating a manufacturing process of the semiconductor memory device according to the second embodiment of the present invention;

FIG. 14 is a diagram illustrating a manufacturing process of the semiconductor memory device according to the second embodiment of the present invention;

FIG. 15 is a diagram illustrating a manufacturing process of the semiconductor memory device according to the second embodiment of the present invention;

FIG. 16 is a diagram illustrating a manufacturing process of the semiconductor memory device according to the second embodiment of the present invention;

FIG. 17 is a diagram illustrating a manufacturing process of the semiconductor memory device according to the second embodiment of the present invention;

FIG. 18 is a diagram illustrating a configuration of a conventional semiconductor memory device.

[Explanation of symbols]

5 interlayer insulating film, 6,171 insulating film, 17 storage node core, 13, 23 storage node plug, 1
4, SN storage node, 15, 26 dielectric film,
16, 27 cell plate, 24 bottom storage node, 25 sidewall storage node, 241 doped polysilicon layer, SC1, S2 stacked capacitor, OP1, OP2 opening.

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Yoji Nakada 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Inside Mitsubishi Electric Corporation (72) Inventor Yoshihiro Nagai 2-3-2 Marunouchi, Chiyoda-ku, Tokyo (72) Inventor Akinori Kinugasa 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Mitsui Electric Corporation (72) Inventor Shigenori Kido 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Inside Rishi Electric Co., Ltd. (72) Inventor Ken Kishida 4-42-8 Higashi Arioka, Itami-shi, Hyogo Eltec Co., Ltd. (72) Inventor Jiro Matsufusa 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Mitsubishi Electric stock In-house F term (reference) 5F083 AD25 AD31 AD48 AD49 AD56 JA33 JA56 MA06 MA17 MA20 PR06 PR09 PR39 PR40

Claims (11)

[Claims] A lower electrode disposed on a base layer formed on a semiconductor substrate; a dielectric film disposed to cover the lower electrode; and a dielectric film disposed to cover the dielectric film. A semiconductor memory device having a stacked capacitor including an upper electrode provided, wherein the lower electrode has one end connected to the semiconductor substrate and the other end protruding above the base layer. The lower electrode is electrically connected to the semiconductor substrate by a conductor plug disposed through the ground layer, and the lower electrode is disposed so as to cover a protruding portion of the plug, and has the covering portion as a protruding portion. , Semiconductor storage devices. 2. The stacked capacitor penetrates an insulating film provided on the base layer, is provided in an opening provided such that a surface of the base layer is a bottom surface, and the plug is The semiconductor memory device according to claim 1, wherein the lower electrode protrudes from the bottom surface, and the lower electrode is provided so as to cover the bottom surface and a wall surface of the opening. 3. The semiconductor memory device according to claim 2, wherein said plug is provided such that a height of a protruding portion thereof is lower than a height of a wall surface of said opening. 4. The lower electrode, comprising: a bottom lower electrode having the protruding portion and constituting a central portion of the lower electrode; and a bottom electrode surrounding an edge of the bottom lower electrode; 2. The semiconductor memory device according to claim 1, further comprising: a sidewall lower electrode extending in a direction perpendicular to a plane. 5. The semiconductor memory device according to claim 4, wherein said plug is provided such that a height of a protruding portion thereof is lower than a height of said side wall lower electrode. 6. A lower electrode disposed on a base layer formed on a semiconductor substrate, a dielectric film disposed to cover the lower electrode, and a dielectric film disposed to cover the dielectric film. A method of manufacturing a semiconductor memory device having a stacked capacitor with a formed upper electrode, comprising: (a) preparing the underlayer and forming an insulating film on the underlayer; Forming a contact hole penetrating the underlayer and the insulating film and reaching the semiconductor substrate; and (c) filling the contact hole so that one end thereof is electrically connected to the semiconductor substrate. (D) selectively removing the insulating film to form an opening protruding from the bottom surface, with the surface of the underlayer serving as a bottom surface and the other end side of the plug protruding from the bottom surface; e) above and below the bottom surface by the conductor layer; Forming the lower electrode that covers the wall surface of the opening and the protruding portion of the plug, and the covering portion that covers the protruding portion of the plug is a protruding portion. 7. The method according to claim 6, wherein the step (c) includes a step of etching the plug until the other end is located in the contact hole. 8. The step (a) includes a step of preparing the underlayer whose uppermost layer is a silicon nitride film, and a step of forming the insulating film by a silicon oxide film. 8. The method according to claim 7, further comprising the step of removing the insulating film by etching, wherein the step of removing the insulating film uses the silicon nitride film as an etching stopper. 9. A lower electrode provided on a base layer formed on a semiconductor substrate; a dielectric film provided so as to cover the lower electrode; and a dielectric film provided so as to cover the dielectric film. A method of manufacturing a semiconductor memory device having a stacked capacitor with a formed upper electrode, comprising: (a) preparing the underlayer and forming a first insulating film on the underlayer; b) forming a contact hole penetrating the base layer and the first insulating film and reaching the semiconductor substrate; and (c) filling the contact hole, one end of which is electrically connected to the semiconductor substrate. Forming a conductor plug to be connected; and (d) removing the first insulating film entirely, exposing the underlayer, and projecting the other end of the plug from the bottom surface. (E) cover the protruding portion of the plug, Forming a first conductor layer in which the covering portion has become a projecting portion; and (f) covering the first conductor layer with a second insulating film, and then projecting the projecting portion of the first conductor layer. The second insulating film and the first conductor layer are selectively removed so that a predetermined portion centered on the portion and the second insulating film thereon remain, and a central portion of the lower electrode is removed. (G) forming a second conductor layer so as to cover at least the bottom lower electrode and the second insulating film remaining thereon, and then performing anisotropic etching Removing the second conductor layer, leaving the second conductor layer on a side surface of the bottom lower electrode and the second insulating film remaining thereon, and surrounding the end surface of the bottom lower electrode; Forming a side wall lower electrode extending in a direction perpendicular to the main surface of the underlayer; Comprising, a method of manufacturing a semiconductor memory device. 10. The method of manufacturing a semiconductor memory device according to claim 9, wherein said step (f) includes a step of making the thickness of said second insulating film equal to or greater than the thickness of said first insulating film. 11. The step (a) includes a step of preparing the underlayer whose uppermost layer is a silicon nitride film, and a step of forming the insulating film of a silicon oxide film. ) Includes a step of removing the first insulating film by etching. In removing the first insulating film, the silicon nitride film is used as an etching stopper. The step (f) includes: 11. The method according to claim 10, further comprising a step of removing an insulating film and the first conductor layer by etching, wherein the silicon nitride film is used as an etching stopper when removing the second insulating film and the first conductor layer. Manufacturing method of a semiconductor memory device.