JP2001196527A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can improve the mounting density of a circuit element, while the circuit elements is provided near the base end of the bump electrode of a semiconductor chip in the semiconductor device of a chip-on-chip structure. SOLUTION: In the semiconductor device, main faces 11 and 12 of a first semiconductor chip 1 and a second semiconductor chip 2 are bonded face to face, electrode 12 and 15 formed in the main faces 11 and 12 face each other and are conducted and the plural semiconductor chips 1 and 2 are resin- packaged by packaging resin 5. For relieving pressure due to the contraction of packaging resin 5, when the plural semiconductor chips 1 and 2 are resin- packaged, at least one face 22 of one semiconductor chip 2 is exposed to the outside of the packaging resin 5.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a so-called chip-on-chip structure in which a plurality of semiconductor chips are stacked.

[0002]

2. Description of the Related Art Conventionally, when a desired semiconductor device is manufactured using a semiconductor chip, the overall size of the semiconductor device is reduced by increasing the mounting density of circuit elements incorporated in the semiconductor chip. . In recent years, a semiconductor device having a structure in which a plurality of semiconductor chips are stacked in the thickness direction, that is, a structure called a so-called chip-on-chip (hereinafter, referred to as “COC”) has been proposed.

FIG. 10 is a diagram showing an example of a semiconductor device to which the above-mentioned COC structure is applied. In this semiconductor device, a plurality (for example, two) of semiconductor chips 51 and 52 are mounted on a substantially flat die pad 53 in a state of being vertically stacked. The above two semiconductor chips 51 and 52
Are bonded with their main surfaces 54, 55 facing each other, and the bump electrodes 56, 57 formed on the main surfaces 54, 55 are electrically connected to each other via an anisotropic conductive adhesive 58. ing. In the semiconductor chips 51 and 52, circuit elements and the like are usually incorporated inside the main surfaces 54 and 55.

A pad-like electrode 59 formed on the main surface 54 of the semiconductor chip 51 is connected to a lead frame 60 via a wire W. The two semiconductor chips 51 and 52, the plurality of wires W, the die pad 53, and the like are sealed with a packaging resin 61 using, for example, a transfer molding method.

When the semiconductor chips 51, 52 and the like are sealed with the packaging resin 61,
When the packaging resin 61 is cured, it shrinks, and the semiconductor chips 51, 52 and the like may receive a pressing force due to the shrinkage from the periphery thereof. Therefore, the bump electrodes 5 provided on the main surfaces 54 and 55 are
6 and 57 are pushed to the semiconductor chips 51 and 52 side, and there is a possibility that a circuit element (not shown) provided near the base end side of the bump electrodes 56 and 57 may be damaged or broken. Therefore, in the semiconductor chips 51 and 52,
Circuit elements are not provided near the base ends of the bump electrodes 56 and 57 to protect the circuit elements and wiring patterns.

[0006]

However, as described above, if the circuit elements are not provided near the base ends of the bump electrodes 56 and 57, the arrangement of the circuit elements in the semiconductor chips 51 and 52 and the wiring pattern In some cases, there is a restriction in the routing of the information. That is, since a circuit element cannot be basically formed in the area where the bump electrodes 56 and 57 are arranged, it is necessary to select another area to form a circuit element, and the degree of freedom in circuit design is limited. Will be done.
This has been one of the problems in increasing the mounting density of circuit elements.

[0007]

DISCLOSURE OF THE INVENTION The present invention has been conceived in view of the above circumstances, and in a COC structure semiconductor device, a circuit element is provided near a base end of a bump electrode of a semiconductor chip while providing a circuit element. It is an object to provide a semiconductor device which can increase the mounting density of elements.

In order to solve the above problems, the present invention takes the following technical measures.

According to the semiconductor device provided by the present invention, the main surfaces of the first semiconductor chip and the second semiconductor chip are bonded to each other so as to face each other, and the electrodes formed on the main surfaces are provided. A semiconductor device in which a plurality of semiconductor chips are resin-packaged with a packaging resin, the pressing force due to shrinkage of the packaging resin when the plurality of semiconductor chips are packaged with the resin is reduced. Therefore, at least one side of the semiconductor chip is exposed to the outside of the packaging resin.

According to the present invention, in this semiconductor device,
Among the first and second semiconductor chips whose main surfaces face each other and are bonded to each other, at least one of the semiconductor chips is packaged with the packaging resin such that one surface of the semiconductor chip is exposed to the outside of the packaging resin. Therefore, when both semiconductor chips are packaged in a resin, even if the packaging resin is cured and shrunk, the pressing force due to the shrinkage on the semiconductor chip is reduced, and the bump electrodes are moved to the semiconductor chip side as in the conventional case. Pushing can be avoided. Therefore, the circuit element can be provided also near the base end side of the bump electrode of the semiconductor chip, so that the degree of freedom in circuit design is not limited and the mounting density of the circuit element can be increased. Therefore, the size of the semiconductor device can be further reduced.

According to a preferred embodiment of the present invention,
A heat radiator is provided on one surface of one semiconductor chip. According to this configuration, the heat generated from the semiconductor chip can be efficiently released to the outside by the heat radiating plate provided on one surface of the one semiconductor chip, so that the heat dissipation of the semiconductor device can be improved, and thus the electronic device can be improved. The operation of the circuit can be stabilized. Further, even if the heat radiating plate is provided on one surface of the semiconductor chip, the heat radiating plate is exposed to the outside, so that the pressing force due to shrinkage of the resin when the semiconductor chip is packaged with the resin can be reduced.

According to another preferred embodiment of the present invention, a circuit element is incorporated in a semiconductor chip near a base end of an electrode. As described above, one surface of at least one semiconductor chip is exposed to the outside of the packaging resin, and the pressing force due to the shrinkage of the packaging resin is reduced. It becomes possible to incorporate circuit elements. Therefore, the circuit element can operate satisfactorily without damage or the like, so that a highly reliable semiconductor device can be provided.

Other features and advantages of the present invention will become more apparent from the detailed description given below with reference to the accompanying drawings.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be specifically described below with reference to the accompanying drawings.

FIG. 1 is a sectional view showing an example of a semiconductor device according to the present invention. This semiconductor device employs a COC structure in which a plurality of semiconductor chips are superimposed, and includes a first semiconductor chip 1 and a second semiconductor chip 2.
And a die pad 3 for mounting both semiconductor chips 1 and 2, a plurality of lead frames 4, and a packaging resin 5.

The first semiconductor chip 1 and the second semiconductor chip 2 are configured as, for example, an LSI chip or another IC chip. A desired electronic circuit is integrated on one surface of a silicon chip and integrated. It was formed in a typical way. Hereinafter, the surfaces of the first semiconductor chip 1 and the second semiconductor chip 2 on which the electronic circuits are integrated are referred to as main surfaces 11 and 12, respectively.

On the main surface 11 of the first semiconductor chip 1, a plurality of bump electrodes 13 formed in a projecting shape and a plurality of pad electrodes 14 formed in a flatter shape are provided. . On the other hand, a plurality of projecting bump electrodes 15 corresponding to the plurality of bump electrodes 13 of the first semiconductor chip 1 are provided on the main surface 12 of the second semiconductor chip 2.

The plurality of bump electrodes 13 and 15 are formed, for example, as gold bump electrodes in order to improve their conductive connectivity. Similarly, the surface of each of the plurality of pad-shaped electrodes 14 is a gold electrode in order to improve the conductive connection with a wire such as a gold wire (described later). Specifically, pad-shaped electrode 14 is formed by, for example, applying gold plating to the surface of a flat aluminum electrode formed on main surface 11 of first semiconductor chip 1.

The first semiconductor chip 1 has a main surface 1
The upper surface of the die pad 3 is bonded to the upper surface of the die pad 3 with an adhesive or the like.
The second semiconductor chip 2 has a size smaller than that of the first semiconductor chip 1 and is stacked on the first semiconductor chip 1 with the back surface 22 facing upward. Specifically, the main surface 12 of the second semiconductor chip 2 is in contact with the main surface 11 of the first semiconductor chip 1 and the anisotropic conductive adhesive 23.
Is glued through. The anisotropic conductive adhesive 23
Instead, an anisotropic conductive film or the like may be applied.

As shown in FIG. 2, the anisotropic conductive adhesive 23 is a material in which conductive particles 23a such as metal particles are dispersed and contained in, for example, a thermosetting epoxy resin as an insulating material. Therefore, if the semiconductor chip 1 and the semiconductor chip 1 are present only between the main surfaces 11 and 12, the semiconductor chips 1 and 2 do not have conductivity in the thickness direction, and when a pressure equal to or more than a predetermined value is applied in the thickness direction, Only the part to which the pressure is applied has the property of having conductivity. Therefore, since the bump electrodes 13 of the first semiconductor chip 1 and the bump electrodes 15 of the second semiconductor chip 2 are arranged to face each other, a pressure equal to or more than a predetermined value is applied therebetween. In addition, they are electrically connected to each other via an anisotropic conductive adhesive 23. Therefore, the two semiconductor chips 1 and 2 are combined while being electrically connected to each other.

Returning to FIG. 1, a wire W made of a gold wire or the like is bonded to the pad-like electrode 14 formed on the main surface 11 of the first semiconductor chip 1, and this wire W is
It is connected to a plurality of lead frames 4.

The lead frame 4 is formed of a thin metal plate such as copper. The lead frame 4 has an internal lead 24 buried inside the packaging resin 5 and an external lead 25 projecting outside the packaging resin 5. Have. With this lead frame 4, this semiconductor device can be mounted on another mounting substrate. That is, after the semiconductor device is mounted so that the lead frame 4 is brought into contact with a predetermined region of another mounting substrate on which the solder paste is applied, the solder paste is heated to perform a solder reflow process. The device can be mounted on a predetermined area of another mounting substrate.

The die pad 3 is formed, for example, in a substantially rectangular shape in a plan view, and is formed of a thin metal plate such as copper similarly to the lead frame 4. An adhesive is applied to the die pad 3 and the first semiconductor chip 1 is joined. The lead frame 4 and the die pad 3 are derived from a conductor frame described later.

The packaging resin 5 is made of, for example, a thermosetting epoxy resin, and covers the peripheral portions of the semiconductor chips 1 and 2, the bonding position of the wire W, the die pad 3, and a part of the lead frame 4. It is molded into. The upper surface 5a of the packaging resin 5 is substantially flush with the upward rear surface 22 of the second semiconductor chip 2, and is formed so that substantially the entire rear surface 22 is exposed to the outside.

That is, according to the present embodiment, the packaging resin 5 is molded so that the back surface 22 of the second semiconductor chip 2 is exposed to the outside. Further, the pressing force applied to the second semiconductor chips 1 and 2 due to the curing and shrinkage of the packaging resin 5 can be reduced. In detail, in the related art, the bump electrodes 13 and 15 may be pushed into the semiconductor chips 1 and 2 by the above pressing force,
Although the circuit elements cannot be provided inside the semiconductor chips 1 and 2 near the base ends of the bump electrodes 13 and 15, in the present embodiment, the back surface 22 of the second semiconductor chip 2 is used. Since almost the entire surface is exposed to the outside, the pressing force affecting the bump electrodes 13 and 15 is reduced. Therefore, the bump electrode 1
3 and 15 are prevented from being pushed into the semiconductor chips 1 and 2,
Even if circuit elements are provided inside the semiconductor chips 1 and 2, damage to these circuit elements can be prevented. Therefore, the circuit element can perform stable operation and can provide a highly reliable semiconductor device.

Further, as a result of exposing the back surface 22 of the second semiconductor chip 2 to the outside, circuit elements can be provided inside the semiconductor chips 1 and 2 near the base ends of the bump electrodes 13 and 15. In addition, the degree of freedom in circuit design is not limited, and the mounting density of circuit elements can be increased.
Therefore, the size of the semiconductor device can be further reduced.

Next, a method of manufacturing the semiconductor device will be described. In this method of manufacturing a semiconductor device, a conductor frame 31 as shown in FIGS. 3 and 4 is used, and the first and second semiconductor chips 1 and 2 are mounted on the conductor frame 31.

First, before being mounted on the conductor frame 31, the first semiconductor chip 1 and the second semiconductor chip 2 are overlaid. That is, the first semiconductor chip 1 has its main surface 11 facing upward, and its back surface 21 is temporarily bonded to, for example, a tape carrier (not shown). Next, anisotropic conductive adhesive 23 and the like are applied to main surface 11 of first semiconductor chip 1. In this case, the thickness of the anisotropic conductive adhesive 23 is set to be slightly higher than the height of the bump electrode 13.

Next, the second semiconductor chip 2 is held by a suction collet (not shown) or the like, and is arranged above the first semiconductor chip 1. Then, the bump electrodes 13 and 15 of the first and second semiconductor chips 1 and 2 are opposed to each other.
The second semiconductor chip 2 is aligned with the first semiconductor chip 1. After that, the second semiconductor chip 2 is moved down to move the second semiconductor chip 2 to the first semiconductor chip 1.
The second semiconductor chip 2 is placed on top and pressed downward. Thereby, the anisotropic conductive adhesive 23 is compressed between the two semiconductor chips 1 and 2 and spreads over the entire main surfaces 11 and 12.

In this case, the anisotropic conductive adhesive 23 receives a large compressive force between the bump electrodes 13 and 15 facing each other, and as shown in FIG. As a result, the bump electrodes 13 and 15 are properly brought into conduction with each other. Then, the anisotropic conductive adhesive 23 is cured by heating. Thereby, the first semiconductor chip 1 and the second semiconductor chip 2 can be more securely bonded and fixed.

The first and second semiconductor chips 1 and 2 superposed by the above method are mounted on the above-described conductor frame 31. The conductor frame 31 is formed by, for example, punching and pressing a metal plate made of copper and performing a predetermined forming process, and has a long shape extending in a certain direction. More specifically, the conductor frame 31 mounts the first and second semiconductor chips 1 and 2 between two side edges 33 and 34 in which a large number of feed holes 32 are formed at regular intervals. The die pad 3 is formed at a plurality of locations at regular intervals in the longitudinal direction.
The conductive frame 31 is supported via support leads 35 for supporting the die pad 3, a plurality of internal leads 24 provided at positions separated from the die pad 3, and the plurality of internal leads 24 and tie bars 36. A plurality of connected external leads 25 are provided.

As shown in FIG. 4, the semiconductor chips 1 and 2 are bonded to the die pad 3 of the conductor frame 31. In this case, for example, a chip bonder or the like is applied in advance to the die pad 3 side or the back surface 21 side of the first semiconductor chip 1 or both. Thereafter, the pad-shaped electrode 14 of the first semiconductor chip 1 and the internal lead 24 of the lead frame 4 are connected and connected via the wire W.

Next, the packaging resin 5 is molded by using, for example, a transfer molding method, and a resin packaging operation for sealing the semiconductor chips 1 and 2 and the peripheral portions thereof is performed. More specifically, as shown in FIG. 5, both semiconductor chips 1 and 2 are packaged with a thermosetting resin such as an epoxy resin using predetermined molds 41 and 42 to form a packaging resin 5. In this case, as shown in FIG. 6, the dies 41, 42 are connected to the semiconductor chip 1, 2 and the lead frame so that the back surface 22 of the second semiconductor chip 2 and the inner surface 41a of the upper mold 41 are in contact with each other. 4 and the epoxy resin is injected into the molds 41 and 42.
As a result, the packaging resin 5 is formed to a height substantially flush with the back surface 22 of the second semiconductor chip 2.

When the resin package operation is completed, an unnecessary portion of the conductor frame 31 is removed, and a forming process for bending the lead frame 4 is performed. By such a series of operation steps, a semiconductor device as shown in FIG. 1 can be obtained.

FIG. 7 is a diagram showing a modification of the semiconductor device according to the present embodiment. According to the figure, this semiconductor device has a heat sink 43 provided on the back surface 22 of the second semiconductor chip 2 instead of the back surface 22 of the second semiconductor chip 2 being exposed to the outside. One side of 43 is exposed to the outside.

The heat radiating plate 43 is formed of a metal plate member having a substantially rectangular shape in a plan view, and has a size larger than that of the second semiconductor chip 2 in order to increase a heat radiating area. I have. The heat radiating plate 43 has one side surface 43.
a is bonded to the back surface 22 of the second semiconductor chip 2 by, for example, ultrasonic bonding, spot welding, or another method. And the other side surface 43b is exposed to the outside upward. The other configuration is substantially the same as the configuration of the above-described embodiment.

As in this modification, the heat radiating plate 43 is provided on the back surface 22 of the second semiconductor chip 2, so that the back surface 22 of the second semiconductor chip 2 is not directly exposed to the outside. It is indirectly exposed to the outside through the plate 43. Therefore, when the packaging resin 5 is sealed, the pressing force on the first and second semiconductor chips 1 and 2 is reduced, and the circuit by the bump electrodes 13 and 15 is performed similarly to the above-described embodiment. Element damage can be prevented.

In this embodiment, a heat sink 43 is provided on the back surface 22 of the second semiconductor chip 2.
Are directly exposed to the outside, the second semiconductor chip 2
Can be efficiently released from the back surface 22 to the outside. Therefore, it is necessary to maintain good heat radiation of the semiconductor device, suppress a rise in temperature when the semiconductor chips 1 and 2 are driven, and stabilize the operation of electronic circuits incorporated in the semiconductor chips 1 and 2. Can be.

Of course, the scope of the present invention is not limited to the above embodiment. For example, in the above-described embodiment, the back surface 22 of the second semiconductor chip 2 is configured to be exposed to the outside. However, instead of this configuration, the back surface 21 of the first semiconductor chip 1 is connected via the die pad 3. It may be formed so as to be exposed to the outside.
In addition, as shown in FIG. 8, the back surfaces 21 and 22 of both the first and second semiconductor chips 1 and 2 may be exposed to the outside.

Further, in the above embodiment, the heat dissipation plate 43 is provided on the second semiconductor chip 2, but as shown in FIG. 9, the heat dissipation plate 43 is provided via the back surface 21 of the first semiconductor chip 1 and the die pad 3. A heat sink 44 may be provided on the connected lower surface. Furthermore, both heat dissipation plates 43 and 44 may be provided on both semiconductor chips 1 and 2 respectively.

In the above embodiment, the semiconductor device having two semiconductor chips is described. However, the number of semiconductor chips is not limited to this, and three or more semiconductor chips may be mounted.

[Brief description of the drawings]

FIG. 1 is a sectional view showing an example of a semiconductor device according to the present invention.

FIG. 2 is a partially enlarged cross-sectional view of a main part of FIG.

FIG. 3 is a plan view of a main part of the conductor frame.

FIG. 4 is a view illustrating a method of manufacturing the semiconductor device shown in FIG. 1;

FIG. 5 is a view illustrating a method of manufacturing the semiconductor device illustrated in FIG. 1;

FIG. 6 is a view illustrating a method of manufacturing the semiconductor device shown in FIG. 1;

FIG. 7 is a sectional view showing a modification of the semiconductor device shown in FIG. 1;

FIG. 8 is a sectional view showing another modification of the semiconductor device shown in FIG. 1;

FIG. 9 is a sectional view showing another modification of the semiconductor device shown in FIG. 1;

FIG. 10 is a sectional view showing a conventional semiconductor device.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 first semiconductor chip 2 second semiconductor chip 5 packaging resin 11 main surface (of first semiconductor chip) 12 main surface (of second semiconductor chip) 13 bump electrode (of first semiconductor chip) 15 Bump electrode (of the second semiconductor chip) 22 Back surface (of the second semiconductor chip) 23 Anisotropic conductive adhesive 43 Heat sink

Claims (3)

[Claims] 1. A main surface of a first semiconductor chip and a main surface of a second semiconductor chip are bonded to face each other,
And a semiconductor device in which the electrodes formed on the main surfaces thereof are opposed to each other and conductive, and the plurality of semiconductor chips are resin-packaged with a packaging resin, and the plurality of semiconductor chips are resin-packaged. In order to reduce the pressing force due to shrinkage of the packaging resin, at least one surface of the one semiconductor chip is exposed to the outside of the packaging resin,
Semiconductor device. 2. The semiconductor device according to claim 1, wherein a heat radiator is provided on one surface of said one semiconductor chip. 3. The semiconductor device according to claim 1, wherein a circuit element is incorporated inside the semiconductor chip near a base end side of the electrode.