JP2001195148A - Clock stop detecting circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that one multipurpose IC is required only for a clock shutdown detecting circuit when it is constituted of a monostable multivibrator to enable re-trigger operation, an area to be occupied on a circuit board is large, however, when the clock shutdown detecting circuit is integrated in one device together with other logic circuits of a device, it is not suitable for integration in a logic device as it is since the multivibrator to enable re-trigger operation is complicated and includes analog voltage detecting circuit. SOLUTION: Two switching circuits to alternately become a conducted state according to the level of an input signal are provided. Capacitors are connected between each switching circuit and a power source, and two capacitors are connected by a resistor. When a clock is normally inputted, two capacitors are maintained at a charged state and when the clock stops, an electronic charge of one capacitor is gradually discharged through a resistor. Discharge of the capacitor is detected by using an electrode potential of the capacitor and the stop of the clock is decided by the level of the electrode potentials of two capacitors.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION In a device which operates by using an edge of a clock signal as a trigger, when a clock stops for some reason, a warning for stopping the device is displayed, a motor is prevented from burning, and a power battery is prevented from being over-discharged. A means for detecting clock stop is required. The present invention relates to a clock stop detection circuit for detecting a clock stop.

[0002]

2. Description of the Related Art Conventionally, as shown in FIG. 5, an input signal is connected to a terminal A using a retriggerable monostable multivibrator 108 which is a general-purpose integrated circuit, and a power supply positive electrode 100 (VCC) is connected to a power supply. A series circuit of a resistor 104 and a capacitor 106 is inserted between the negative electrode 102 (GND), and both ends of the capacitor 106 are connected to terminals T1 and T2, respectively. When the input signal has a clock input,
The detection output Q terminal becomes High, and when the clock stops, it goes Low after a fixed time from the last rising edge of the clock.

[0003]

If the clock stop detection circuit is constituted by a monostable multivibrator capable of retrigger operation, only one general-purpose IC is required, so that the area occupied on the circuit board is large. However, if it is attempted to combine the other logic circuit parts of the device into one logic device, the multivibrator capable of retrigger operation has a complicated circuit and includes an analog voltage detection circuit. The circuit was unsuitable for incorporation into a logic device. SUMMARY OF THE INVENTION The present invention provides a clock stop detection circuit which is simple in circuit and can be easily configured using a logic circuit and a small number of external components.

[0004]

SUMMARY OF THE INVENTION An input signal High, L
Two switching circuits that are turned on alternately according to ow are provided. A capacitor is connected between each of the switching circuits and the power supply, and the two capacitors are connected with a resistor. When the clock is input to the input signal, the two capacitors are kept in a charged state, and when the clock stops, the charge of one of the capacitors is gradually discharged through the resistor. The discharge of the capacitor is detected using the capacitor electrode potential, and the stop of the clock is determined in a state where the two capacitor electrode potentials are High and Low.

[0005] As another means, input signal High, L
Two switching circuits that are turned on alternately according to ow are provided. A first capacitor is connected between the first switching circuit and the power supply, and a second capacitor is connected between the first switching circuit and the second switching circuit. A resistor is connected in parallel with the second capacitor. When the clock is input to the input signal, the second capacitor is kept in a charged state, and when the clock is stopped, the charge of the second capacitor is gradually discharged through the resistor. The discharge of the capacitor is detected using the capacitor electrode potential,
The stop of the clock is determined when the capacitor electrode potentials are High and Low.

In any of the above means, the first and the second
Is constituted by a diode directly connected to an input signal or by a P-channel transistor and an N-channel transistor whose input signal is connected to a gate.

[0007]

FIG. 1 is a diagram illustrating a first embodiment of a clock stop detection circuit according to the present invention. In the present embodiment, the first diode 10 and the second diode 12 are connected in opposite directions to each other to form first and second switching circuits. The first capacitor 14 is connected between the first diode 10 and the power supply negative electrode 20. The second capacitor 16 is connected between the second diode 12 and the power supply positive electrode 18. The terminal A of the first capacitor 14 and the second
The terminals B of the capacitor 16 are connected by a resistor 22 which is a discharging means. The terminal A of the first capacitor 14 and the second
The determination circuit 24 for determining the stop of the clock from the respective potentials is connected to the terminal B of the capacitor 16.

The operation when a normal clock is input to the input signal will be described. When the input signal is High, the first diode 10 is turned on, the first capacitor 14 is charged, and the potential of the terminal A becomes High level. At this time, the second diode 12 is off. Next, when the input signal goes low, the second diode 1
2 becomes conductive, the second capacitor 16 is charged, and the potential of the terminal B becomes Low level. At this time,
Since the first diode 10 is in a non-conductive state because a reverse voltage is applied, the potential of the terminal A is kept at High. The resistor 22 connecting the terminal A and the terminal B serves as a means for charging and discharging the first capacitor 14 and the second capacitor 16. A current flows from the first capacitor 14 to the second capacitor 16 little by little. The potential of the terminal A and the terminal B changes slowly, and while the normal clock is input to the input signal, the first The decrease in the charges in the first capacitor 14 and the second capacitor 16 is compensated for through the diode 10 and the second diode 12, so that the potential of the terminal A is kept high and the potential of the terminal B is kept low.

Next, the operation when the clock of the input signal is stopped will be described. When the input signal is stopped in the high state, the potential of the terminal A is kept high because the first diode 10 is in the conductive state, but the electric charge of the second capacitor 16 is discharged through the resistor 22 and eventually the terminal The potential of B becomes High.

When the input signal is stopped in a low state, the second diode 12 is in a conductive state, so that the terminal B
Is kept low, but the electric charge of the first capacitor 14 is discharged through the resistor 22, and the potential of the terminal A eventually becomes low.

When a normal clock is input, that is, when the potential of the terminal A is High and the potential of the terminal B is Low, the detection output becomes High, and when the clock signal stops, that is, the terminal A When both of the potentials at the terminal B are High or both are Low, the detection output becomes Low.

The terminal of the first capacitor 14 and the terminal of the second capacitor 16 which is not connected to the determination circuit 24 only needs to be kept at a constant potential. Even if the power supply negative electrode 20 is used, there is no difference in the operation of clock stop detection. However, in the embodiment of FIG. 1, the first capacitor 14 is used as the power supply negative electrode 20 and the second capacitor 16 is used as the power supply positive electrode 18. The function can also serve as a power-on detection circuit. Since the first capacitor 14 and the second capacitor 16 are discharging while the power is off, when the power is turned on, the potential of the terminal A is low and the potential of the terminal B is high.
h and it is determined that the clock is stopped. When the clock cycle elapses, a normal clock input is detected, and the detection output becomes High.

FIG. 2 is an explanatory diagram of a second embodiment of the clock stop detection circuit according to the present invention. In this embodiment, a P-channel MOS transistor (hereinafter, a first transistor 30) having an input signal connected to a gate and a power supply positive electrode 38 connected to a drain constitutes a first switching circuit. An N-channel MOS transistor (hereinafter referred to as a second transistor 32) having the drain connected to the drain constitutes a second switching circuit. The first capacitor 34 is connected between the source of the first transistor 30 and the power supply positive electrode 38, and the second capacitor 36 is connected between the source of the second transistor 32 and the power supply negative electrode 40. A resistor 42 serving as a discharging means is connected between the terminal A of the first capacitor 34 and the second capacitor 36.
To the terminal B. A determination circuit 44 for determining whether to stop the clock based on the respective potentials is connected to the terminals A and B. The first and second switching circuits having this configuration can be easily formed using a three-state output pin in a standard programmable logic device.

While a normal clock is input to the input signal, when the input signal is high, the second transistor 32 is turned on, the second capacitor 36 is discharged, and the potential of the terminal B becomes low. Become. During this time, the first transistor 30 is off and the first capacitor 34
Is charged through the resistor 42, but charging is gradual, and the potential of the terminal A remains High while a normal clock is input. 1st when input signal is Low
Transistor 30 is turned on, and the first capacitor 34 is discharged and goes high. During this time, the second transistor 32 is non-conductive, and the second capacitor 3
6 is slowly charged through the resistor, but the potential of the terminal B remains Low while a normal clock is input. Since the determination circuit 44 performs the same operation as the determination circuit of FIG. 1, it determines that a clock is being input, and the detection output becomes High.

When the clock of the input signal is stopped, one of the first transistor 30 and the second transistor 32 is kept off. One of the first capacitor 34 and the second capacitor 36 is charged through the resistor, and the potentials of the terminal A and the terminal B both become High or both become Low. The determination circuit 44 determines that the clock is stopped, and the detection output becomes Low. Since the first capacitor 34 is connected to the power supply positive electrode 38 and the second capacitor 36 is connected to the power supply negative electrode 40, if the power supply is turned off and the first capacitor 34 and the second capacitor 36 are discharged,
When the power is turned on, the detection output becomes high, and it is determined that a normal clock is input.

FIG. 3 is an explanatory diagram of a third embodiment of the clock stop detection circuit of the present invention. In the present embodiment, the first capacitor 50 and the second diode 52 are connected to the input
4 and the second capacitor 56 are connected. A charge / discharge circuit is configured by connecting the first capacitor 54 between the first diode 50 and the power supply negative electrode 60. By connecting a second capacitor 56 between the second diode 52 and the first diode 50, a series charge / discharge circuit is formed. A resistor 62 serving as charging / discharging means is connected in parallel with the second capacitor 56. A determination circuit 64 for determining whether to stop the clock is connected to the terminals A and B of the second capacitor 56.

The operation when a clock is input with no charge in the first capacitor 54 and the second capacitor 56 will be described. When the input signal is high, the first diode 50 is turned on, the first capacitor 54 is charged, and the potential of the terminal A is at the high level.
At this time, since the second diode 52 is non-conductive, the potential difference between the terminal A and the terminal B is preserved, and the terminal B becomes High.
become. Next, when the input signal goes low, the second diode 52 is turned on and the first diode 50 is turned off. The potential of the terminal B becomes Low level,
At this time, a current flows from the power supply negative electrode 60 to the second capacitor 56 through the first capacitor 54, and the first capacitor 54 discharges a part of the electric charge and charges the second capacitor 56. The potential of the terminal A decreases. Input signal is H again
When the potential becomes high, the first diode 50 is turned on, the first capacitor 54 is charged, and the potential of the terminal A is almost at the high level. During this time, the second capacitor 5
Since the charge of No. 6 is unchanged, the potential of the terminal B rises,
The potential is lower than in the previous cycle. The determination circuit 64 performs the same operation as the determination circuit of FIG.
In this excessive state, it is determined that the clock is stopped although it is unstable, and the detection output becomes Low.

As described above, when the input signal is High, L
ow is repeated several times, the first capacitor 54 and the second capacitor
Is gradually charged, and the terminal A becomes High.
Then, the terminal B becomes low and stable. The charges of the first capacitor 54 and the second capacitor 56 are gradually discharged through the resistor 62, but if the clock is normal,
The electric charge is supplemented through the first diode 50 and the second diode 52. The determination circuit 64 determines that the clock is input, and the detection output becomes High.

Next, the operation when the clock of the input signal is stopped will be described. When the input signal is stopped in the High state, the terminal A of the first capacitor 54 is kept High because the first diode 50 is in the conductive state, but the electric charge of the second capacitor 56 is discharged through the resistor 62. Eventually, the terminal B of the second capacitor 56 becomes High
become. When the input signal is stopped in a low state, the voltage of the terminal B is kept low because the second diode 52 is in a conductive state, but the charges of the first capacitor 54 and the second capacitor 56 are discharged through the resistors. Then, the voltage of the terminal A eventually becomes low. In both cases, the judgment circuit 6
No. 4 determines that the clock is stopped, and the detection output becomes Low.
The first diode 50 and the second diode 52 of the present embodiment can be replaced with transistors, like the first MOS transistor 30 and the second transistor 32 of the MOS type shown in the embodiment of FIG. .

FIG. 4 is an explanatory diagram of another embodiment of the charging / discharging means. 1 to 3, a resistor is used as a charging / discharging means. In each of these cases, an N-channel transistor 70 and a P-channel transistor 72 are connected in parallel between terminals A and B as shown in FIG. Thus, the discharging means can be configured. N-channel transistor 70
And the base of the P-channel transistor 72 are given a potential at which current can flow slowly between the terminals A and B, respectively. In this way, the discharging means can be taken in the same integrated circuit as the logic. Furthermore, since the charging / discharging current through the discharging means can be set small,
First and second capacitors can also be made in the integrated circuit.

[0021]

As described above, the clock stop detection circuit of the present invention is composed of two simple switching circuits, two capacitors, charging / discharging means, and a detection circuit. Except for the above, it becomes easy to incorporate the clock stop detection circuit into the integrated circuit together with the logic part of the system of the entire device.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a clock stop detection circuit according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram of a clock stop detection circuit according to a second embodiment of the present invention.

FIG. 3 is an explanatory diagram of a clock stop detection circuit according to a third embodiment of the present invention.

FIG. 4 is an explanatory diagram of another embodiment of the charging / discharging means.

FIG. 5 is an explanatory diagram of a conventional clock stop detection circuit.

[Explanation of symbols]

 10, 50 First diode 12, 52 Second diode 14, 34, 54 First capacitor 16, 36, 56 Second capacitor 18, 38 Power supply positive electrode 20, 40 Power supply negative electrode 22, 42, 62 Resistance 24, 44, 64 Judgment circuit 30 First transistor 32 Second transistor 108 Monostable multivibrator

Continued on the front page (72) Inventor Masakuni Matsunaga 5-6-112 Maeharacho, Koganei-shi, Tokyo F-term (reference) 5J039 HH02 HH15 KK14 KK11 MM11

Claims (6)

[Claims] 1. A first switching circuit which alternately conducts according to the level of an input signal, High or Low, in which a current flows between a positive electrode of a power supply and an input terminal in a conductive state, and an input terminal in a conductive state. A second switching circuit that allows a current to flow between the power supply and the power supply negative electrode; a first capacitor having one end connected to the reference potential and the other end connected to the first switching circuit; A second capacitor connected to the second switching circuit; charging / discharging means for connecting the first capacitor and the second capacitor to gradually charge / discharge; and a terminal for the first capacitor and the second capacitor. A determination circuit for determining whether to stop the clock based on the potential; a first switching circuit constituting a charge / discharge circuit for the first capacitor; and a second switching circuit for charging / discharging the second capacitor. A clock stop detection circuit, comprising: 2. A first switching circuit for conducting current between an input terminal and a positive electrode of a power supply alternately in accordance with the level of an input signal, High and Low. A second switching circuit that allows a current to flow between the negative electrode and the input terminal; a first capacitor having one end connected to the reference potential and the other end connected to the first switching circuit; and one end connected to the first capacitor A second capacitor having the other end connected to the second switching circuit; charging / discharging means for gradually discharging the charge of the second capacitor; and determining whether to stop the clock from the potentials at both ends of the second capacitor. A determination circuit, wherein the first switching circuit forms a charging and discharging circuit of the first capacitor, and the second switching circuit forms a series charging and discharging circuit of the first and second capacitors. Clock stop detection circuit. 3. The clock stop detection circuit according to claim 1, wherein the first capacitor has one end connected to a power supply negative electrode, the other end connected to a first switching circuit, and the second capacitor connected at one end to a power supply. A clock stop detection circuit having a positive electrode and the other end connected to a second switching circuit. 4. The method according to claim 1, 2 or 3.
Wherein the first switching circuit is a forward diode connected in series with the input signal, and the second switching circuit is a reverse diode connected in series with the input signal. Characteristic clock stop detection circuit. 5. The method according to claim 1, 2 or 3.
Wherein the first switching circuit is a P-channel MOS transistor having a source connected to the positive terminal of the power supply and a gate connected to the input signal, and the second switching circuit is connected to the negative terminal of the power supply. And a gate connected to an input signal. 6. The clock stop detection circuit according to claim 1, wherein the charge / discharge means is an N-channel transistor and a P-channel transistor connected in parallel.