JP2001194645A - Optoelectric panel, method and circuit for driving data lines of optoelectric panel, optoelectric device, and electronic equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal panel of which the production costs are decreased and of which the characters are easy to read. SOLUTION: A lateraly long liquid crystal panel 100 is provided with a vertically-striped picture display area 110, a scanning line drive circuit 120 to be arranged on the long side LL, and a data line drive circuit 130 to be arranged on the short side LS. The data line drive circuit 130 sequentially converts image data DR, DG, DB into dot-sequential image data and then converts them into line-sequential image data, and further processes the line- sequential image data corresponding to each color by serial-parallel conversion and thereby generates serial mode image data corresponding to each data line 114, and furthermore processes them by D-A conversion, to generate each image signal. In such a manner, it is possible to supply image signals to R, G, B in each pixel area where pixels are arranged in order R, G, B along the data lines.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an electro-optical panel,
The present invention relates to a data line driving method and a data line driving circuit for an electro-optical panel, an electro-optical device, and an electronic apparatus.

[0002]

2. Description of the Related Art A conventional electro-optical device, for example, an active matrix type liquid crystal display device comprises a liquid crystal panel and peripheral circuits for supplying control signals and the like thereto. A liquid crystal panel mainly includes an element substrate in which switching elements are provided in each of pixel electrodes arranged in a matrix, a counter substrate in which a color filter and the like are formed, and a liquid crystal filled between these two substrates. Consists of

In such a configuration, when a scanning signal is applied to a switching element via a scanning line, the switching element becomes conductive. In this conductive state, when an image signal is applied to the pixel electrode via the data line, a predetermined charge is accumulated in the liquid crystal layer between the pixel electrode and the counter electrode (common electrode). After the charge accumulation, even if the switching element is turned off, if the resistance of the liquid crystal layer is sufficiently high, the accumulation of charge in the liquid crystal layer is maintained. As described above, when the amount of electric charge to be accumulated by driving each switching element is controlled, the alignment state of the liquid crystal changes for each pixel, so that predetermined information can be displayed.

[0004] At this time, it is sufficient to accumulate electric charges in the liquid crystal layer of each pixel during a part of the period. First, each scanning line is sequentially selected by a scanning line driving circuit, and secondly,
In the scanning line selection period, one or more data lines are sequentially selected by the data line driving circuit, and the third line is selected.
In addition, the configuration in which the image signal is supplied to the selected data line enables time division multiplex driving in which the scanning line and the data line are shared by a plurality of pixels.

[0005] Incidentally, the liquid crystal display device has a horizontally long screen and a vertically long screen depending on the application. For example, the former may be used as a display unit of a computer or the like, and the latter may be used as a display unit of a personal digital assistant (PDA).

FIG. 14 is a block diagram showing a main part of a liquid crystal panel having a horizontally long screen. As shown in this figure, in a horizontally long screen liquid crystal panel, the scanning lines 12A are formed in the screen longitudinal direction (X direction), and the data lines 13A are formed in the direction orthogonal to the scanning lines 12A (Y direction). I have. In this liquid crystal panel, the data lines 12A and the scanning lines 13A
R, R, G, and B pixel regions R, G, and B for displaying each color of red, green, and blue are provided in correspondence with the intersections. In the following description, a set of the R pixel region R, the G pixel region G, and the B pixel region B will be referred to as one pixel.

In the liquid crystal panel, the data line driving circuit 130A is formed on the long side LL of the liquid crystal panel, and the scanning line driving circuit 120A is disposed on the short side LS of the liquid crystal panel. In addition, mounting terminals for connecting the external circuit and the liquid crystal panel are provided on the long side LL side (not shown).

The mounting terminals are provided on the long side LL of the liquid crystal panel because the driving frequency of the data line driving circuit 130A is higher than that of the scanning line driving circuit 120A. If mounting terminals are provided on the short side LS side, the data line driving circuit 13
A clock signal for driving 0A needs to be routed through a long wiring. Since the parasitic capacitance of the wiring increases as the distance increases, when the mounting terminal is provided on the short side LS side, when the clock signal is input to the data line driving circuit 130A, the rising edge and the falling edge of the waveform become dull. This may cause the data line driving circuit 130A to malfunction. Therefore, the mounting terminal is provided on the long side LL side of the liquid crystal panel close to the data line driving circuit 130A.

FIG. 15 is a block diagram showing a main part of a vertically long liquid crystal panel. In this example, the data line driving circuit 130B is formed on the short side LS of the liquid crystal panel, and the scanning line driving circuit 120B is connected to the long side L of the liquid crystal panel.
It is formed on the L side. In addition, mounting terminals for connecting the peripheral circuit and the liquid crystal panel are provided on the short side LS side. In this liquid crystal panel, vertically long pixel regions R, G, and B are provided as shown in the figure. In the following description, a vertically formed pixel region on a display screen is referred to as a vertical stripe, and a horizontally formed pixel region is referred to as a horizontal stripe.

[0010]

As described above, a liquid crystal panel is formed by bonding an element substrate and a counter substrate. The mounting terminals, the data line driving circuit and the scanning line driving circuit are formed on an element substrate. Therefore, the area of the element substrate is larger than the area of the counter substrate. Here, in the liquid crystal panel in which the mounting terminals are provided on the long side LL side, the area of the element substrate is larger than that in the case where the mounting terminals are provided on the short side LS side. In the horizontally long screen liquid crystal panel shown in FIG. 14, the mounting terminals need to be provided on the long side LL side in relation to the data line driving circuit 130A, so that the area of the element substrate becomes large and the cost of the liquid crystal panel is reduced. There is a problem of rising.

On the other hand, when a vertically long liquid crystal panel shown in FIG. 15 is rotated by 90 degrees to display a horizontally long screen, the area of the element substrate does not increase because the mounting terminals are on the short side LS side of the liquid crystal panel. . However, in this case, since the image is rotated by 90 degrees, the screen becomes a horizontal stripe, and there is a problem that characters such as alphabets are difficult to read. This point will be specifically described with reference to FIG. FIG. 16 is a conceptual diagram showing an example in which the character "X" displayed in green is displayed on a horizontal stripe screen. In this figure, the shaded portion is a green character “X”.
Is a pixel area corresponding to. In this case, the character "X"
Is interrupted and it becomes difficult to read.

That is, in order to display a landscape screen,
When the liquid crystal panel shown in FIG. 14 is used, the area of the element substrate is increased. On the other hand, when the liquid crystal panel shown in FIG.

SUMMARY OF THE INVENTION The present invention has been made in view of these points, and an object of the present invention is to provide an electro-optical panel in which the area of an element substrate is small and characters are easy to read, a data line driving circuit and a driving method thereof, An object of the present invention is to provide an electro-optical device and an electronic apparatus using the same.

[0014]

A data line driving method for an electro-optical panel according to the present invention comprises a plurality of data lines, a plurality of scanning lines, and switching elements provided corresponding to their intersections. Assuming that it is used for an electro-optical panel including each pixel electrode connected to each switching element, image data corresponding to a plurality of colors are respectively converted into dot-sequential image data corresponding to the number of data lines. The dot-sequential image data is latched and converted into line-sequential image data at each scanning line selection cycle, and parallel-serial conversion is performed on the line-sequential image data of each color, and each of the data lines corresponding to each data line is converted. It is characterized in that serial data is generated, each serial data is DA converted, each image signal is generated, and each image signal is supplied to each data line.

According to the present invention, the line-sequential image data of each color is subjected to a parallel-serial conversion to generate each serial data corresponding to each data line. , Image data corresponding to each pixel region can be sequentially supplied.

Next, in the data driving circuit according to the present invention, a plurality of data lines, a plurality of scanning lines, each switching element provided corresponding to each intersection thereof, and A first conversion unit that converts image data corresponding to a plurality of colors into dot-sequential image data of a number corresponding to the number of data lines, assuming that the pixel data is used in an electro-optical panel including each pixel electrode connected thereto; The dot-sequential image data is latched and converted into line-sequential image data in each scanning line selection cycle, and the line-sequential image data of each color is subjected to parallel-serial conversion to obtain a corresponding one of the data lines. A second conversion unit that generates serial data;
A DA converter that supplies each image signal obtained by DA conversion of each serial data to each data line.

According to the present invention, similar to the data line driving method described above, line-sequential image data is subjected to parallel-serial conversion to generate each serial data corresponding to each data line. When corresponding pixel regions are formed along the data lines, image data corresponding to each pixel region can be sequentially supplied.

Here, the second conversion section includes units corresponding to the respective data lines, and one unit includes cascade-connected sub-units corresponding to the respective colors. A latch circuit that latches the dot-sequential image data at the start of a selection period; and a transfer circuit that transfers an output signal of each sub-unit to an input of the latch circuit of a next-stage sub-unit during the selection period of the scanning line. It may be something. In this case, the second conversion unit is configured by cascade-connecting each sub-unit corresponding to each color,
Each subunit transfers its output signal to the next subunit, so that serial-parallel conversion corresponding to each data line can be performed.

Further, the image data may include a first color and a second color.
If the data is three types of data for each of the color and the third color, the second conversion unit outputs the serial data obtained by performing the parallel-serial conversion in the order of the first color, the second color, and the third color; The unit includes a first sub-unit corresponding to a first color and extracting the serial data, and a second sub-unit provided before the first sub-unit and corresponding to a second color.
A first sub-unit provided before the second sub-unit and corresponding to a third color, wherein a latch circuit of each sub-unit is activated at the start of the scanning line selection period; The dot-sequential image data is latched based on a transfer signal, and the transfer circuit of the third sub-unit changes the selection period of the scanning line from a point in time when a predetermined time has elapsed after the end of the active period of the first transfer signal. An output signal of the third sub-unit is transferred to an input of the second sub-unit based on a second transfer signal which is active during a period until the termination, and a transfer circuit of the second sub-unit transfers the output signal of the second sub-unit. Based on a third transfer signal that is active during a period from a point in time when the signal transitions from inactive to active and a certain time has elapsed until the end of the selection period of the scanning line. It is preferable to transfer the output signal of the second subunit to the input of the first subunit.

The second conversion unit includes units corresponding to the data lines. One unit is formed by connecting the sub-units corresponding to the respective colors in a ring, and each sub-unit is connected to the scanning line. A latch circuit that latches the dot-sequential image data at the start of a selection period; and a transfer circuit that transfers an output signal of each sub-unit to an input of the latch circuit of a next-stage sub-unit during the selection period of the scanning line. It may be something. In this case, by performing data transfer between the sub-units by a number corresponding to the number of colors of the image data during a certain scanning line selection period, the state of each sub-unit is returned to the initial state of the scanning line selection period. be able to.

Further, the image data includes a first color and a second color.
If the data is three types of data for each of the color and the third color, the second conversion unit outputs the serial data obtained by performing the parallel-serial conversion in the order of the first color, the second color, and the third color; The unit includes a first sub-unit corresponding to a first color and extracting the serial data, and a second sub-unit provided before the first sub-unit and corresponding to a second color.
A first sub-unit provided before the second sub-unit and corresponding to a third color, wherein a latch circuit of each sub-unit is activated at the start of the scanning line selection period; The dot-sequential image data is latched based on a transfer signal, and the transfer circuit of each of the sub-units changes from the time when the first transfer signal changes from active to inactive until the selection period of the scanning line ends. It is preferable to transfer the output signal of the next stage to the input of the subsequent subunit based on the second transfer signal that is active three times during the period.

In this case, since the data transfer between the sub-units is performed three times by the second transfer signal, the state of each sub-unit is returned to the initial state in the scanning line selection period. Generally, since the correlation of the image signal between the adjacent pixels is extremely high, the state of each subunit is switched from one scanning line selection period to the next scanning line selection period by returning to the initial state of the scanning line selection period. At this time, the state of each sub-unit is switched between adjacent data of the same color. Therefore, at this time, since the data of each subunit hardly changes, power consumption can be reduced.

Next, an electro-optical panel according to the present invention includes one of the above-described data line driving circuits and a horizontally long image area, wherein the image area includes a plurality of data lines extending in a horizontal direction. It comprises a line, a plurality of scanning lines extending in the vertical direction, switching elements provided corresponding to their intersections, and pixel electrodes respectively connected to the switching elements. According to the invention,
The data lines extending in the horizontal direction can be driven in the image area of the horizontal screen.

Further, it is preferable that the image area has a vertically long pixel area divided by each of the scanning lines and each of the data lines, and the data line driving circuit is arranged on a short side. In this case, since vertical stripes are formed, alphabetic characters and the like can be displayed in the image area in a legible manner.

In addition, it is preferable that a scanning line driving circuit for driving the scanning lines is arranged on the long side, and a mounting terminal is arranged at an end on the short side close to the data line driving circuit. In this case, since the mounting terminals are arranged at the short end, the cost of the liquid crystal panel can be reduced. Further, since the mounting terminal and the data line driving circuit are arranged close to each other, the wiring from the mounting terminal to the data line driving circuit can be shortened, and the parasitic capacitance of the wiring can be reduced.
Therefore, the data line driving circuit with a high driving frequency can be operated stably, and the load on the external circuit can be reduced, and the current consumption can be reduced.

Next, an electro-optical device according to the present invention includes: any one of the above-described electro-optical panels, and an image processing section for switching the relationship between the rows and columns of input image data and supplying the data to the electro-optical panel. Features.

Next, an electro-optical device according to the present invention is characterized in that the electro-optical device is provided as a display unit.

[0028]

Embodiments of the present invention will be described below with reference to the drawings.

<1. First Embodiment> First, the first embodiment of the present invention
The electro-optical device according to the embodiment will be described by taking a liquid crystal display device using liquid crystal as an electro-optical material as an example.

<1-1. Overall configuration of electro-optical device> FIG.
FIG. 2 is a block diagram illustrating an electrical configuration of the liquid crystal display device according to the first embodiment. As shown in the figure, the liquid crystal display device has a liquid crystal panel 100 and a timing generation circuit 2.
00 and an image signal processing circuit 300.

Of these, the timing generation circuit 200
It outputs a timing signal (to be described later as necessary) used in each unit. Further, the image signal processing circuit 3
In the step 00, the input image data Dr, Dg, and Db corresponding to the three primary colors R, G, and B are subjected to a predetermined matrix conversion to generate the image data DR, DG, and DB. Here, input image data Dr, Dg, Db and image data DR, DG,
DB is 6-bit parallel data per sampling. The details of the matrix conversion will be described later.

Next, the electrical configuration of the liquid crystal panel 100 will be described. The liquid crystal panel 100 has an image display area 11
0, scanning line driving circuit 120 and data line driving circuit 13
0 is provided. Further, the liquid crystal panel 100 has a configuration in which an element substrate and a counter substrate are attached to each other with an electrode forming surface facing each other, as described later.

Of these, the image display area 110 of the element substrate
In FIG. 1, a plurality of scanning lines 112 are arranged in parallel along the Y direction in FIG. 1, and a plurality of data lines 114 are formed in parallel along the X direction orthogonal thereto. ing. At each intersection between the scanning line 112 and the data line 114, the gate electrode of the TFT 116 is connected to the scanning line 112, while the source electrode of the TFT 116 is connected to the data line 114,
The drain electrode of the FT 116 is connected to the pixel electrode 118. Each of the pixel regions R, G, and B is a pixel electrode 1
18 and a common electrode formed on a counter substrate, which will be described later, and a liquid crystal interposed between these electrodes. As a result, a matrix is formed corresponding to each intersection of the scanning line 112 and the data line 114. They will be arranged. In addition, a storage capacitor (not shown) may be formed for each of the pixel regions R, G, and B in parallel with the liquid crystal sandwiched between the pixel electrode 118 and the common electrode from an electrical viewpoint. good.

FIG. 2 is a conceptual diagram showing pixels constituting the image display area 110. Note that the code Pjk is the j-th
The pixel in the column, k-th row is shown. As shown in the figure, the image display area 110 is composed of pixels P11 to Pmn in n rows and m columns, and is a landscape screen in which the length in the horizontal direction is longer than the length in the vertical direction. Further, one pixel includes an R pixel region R,
It is composed of a G pixel area G and a B pixel area B.
These pixel regions R, G, and B are separated by the scanning lines 112 and the data lines 114, and have a vertically long rectangular shape.

Next, the scanning line driving circuit 120 and the data line driving circuit 130 shown in FIG. 1 are formed on the opposing surface of the element substrate and around the image display area 110 as described later. . The active elements of these circuits are all p-channel TFTs and n-channel TFTs.
It is formed by a combination of FT. Therefore, TF
It can be formed by a common manufacturing process with T116,
This is advantageous in terms of integration, manufacturing cost, element uniformity, and the like.

Here, the scanning line drive circuit 120 has a shift register, and receives the clock signal CLX from the timing generation circuit 200 and its inverted clock signal CLXINV,
The scanning signal is sequentially output to each scanning line 112 based on the transfer start pulse DX and the like.

Although the details of the data line driving circuit 130 will be described later, an image signal to be supplied to each data line 114 is generated based on the image data DR, DG and DB supplied from the image signal processing circuit 300. It has become.

<1-2. Configuration of Image Signal Processing Circuit> Next, the image signal processing circuit 300 will be described in detail. FIG. 3 is a block diagram illustrating a configuration of a main part of the image signal processing circuit 300. As shown in this figure, the main part of the image signal processing circuit 300 is composed of an address generation circuit 310,
RAMR320, RAMG330, and RAMB34
0.

First, the input image data Dr, Dg, Db
Is scanned from the leftmost pixel to the rightmost pixel for each row, and is provided as a data string obtained by repeating this from the first row to the nth row. That is, the input image data Dr, Dg, D
b are pixels P11, P21,..., Pm1, Pm shown in FIG.
12, P22, ..., Pm2, ..., P1n, P2n, ...,
Pmn, in this order. Here, input image data Dr, Dg, D corresponding to each pixel
Let b be Pjkr, Pjkg, Pjkb.
RAMR320, RAMG330, and RAM
Regarding the image data DR, DG, and DB output from B340, data per sampling corresponding to each pixel is represented as PjkR, PjkG, and PjkB. Here, j is 1 ≦ j ≦ m and indicates the number of the corresponding column, and k is 1 ≦ k ≦ n and indicates the number of the corresponding row.

The address generation circuit 310 has a write address W necessary for writing the input image data Dr, Dg, Db.
While generating ADR, a read address RADR required for reading image data DR, DG, and DB is generated.

Next, RAMR320, RAMG330,
The RAMB 340 includes a first storage unit and a second storage unit (not shown), and is configured to perform writing to one storage unit and read data from the other storage unit at the same time. . Further, the first storage unit and the second storage unit have a storage area of n rows and m columns, and have a storage capacity capable of storing data of one field. Then, assuming that data is written to one storage unit in one field and read from the other storage unit at the same time, in the next field, data is written to the other storage unit and read from one storage unit at the same time. I have.

Here, the write address WADR is one row, one row.
, 1 row, 2 columns, ..., 1 row, m columns, 2 rows, 1 column, 2 rows, 2 columns,
, 2 rows and m columns,..., N rows and 1 column, n rows and 2 columns,..., N rows and m columns, while the read address RADR is 1 row and 1 column, 2 rows and 1 column, ..., n rows and 1 column, 1 row and 2 columns, 2 rows and 2 columns, ..., n rows and 2 columns, ..., 1 row and m columns, 2 rows and m
Each storage area is specified in the order of columns,..., N rows and m columns.

Therefore, RAMR320, RAMG3
30 and the RAMB 340, writing is performed in order from the storage area in the first column to the storage area in the m-th column for each row, and this is repeated from the first row to the n-th row, whereby the input image data for one field is written. Dr, Dg, and Db are stored. On the other hand, at the time of reading, the reading is performed in order from the storage area of the first row to the storage area of the n-th row for each column, and this is repeated from the first column to the m-th column, so that the image data DR, DG , DB are output.

For this reason, RAMR320, RAMG33
0 and image data D output from RAMB 340
R, DG, and DB are pixel pixels P11 and P1 shown in FIG.
2, ..., P1n, P21, P22, ..., P2n, ..., P
A data sequence is sampled in the order of m1, Pm2,..., Pmn.

Thus, the input image data Dr, Dg,
The image data DR, DG, obtained by converting the rows and columns with respect to Db,
DB can be obtained.

In the above-described example, the write address WADR is hardware-based using the address generation circuit 310.
And the read address RADR. However, when the liquid crystal display device is used as a monitor of a computer system, the input image data Dr and D are stored in a storage area designated by a continuous address by the CPU.
In addition to writing g and Db, the image data DR, DG, and DB may be read from the storage area using an address designated so that the row and column can be converted. Alternatively, the input image data Dr, Dg, Db
May be written to the storage area using an address designated so that the row and column can be converted, and the image data DR, DG, and DB may be read from the continuous storage area.

<1-3. Configuration of Data Line Drive Circuit> Next, the data line drive circuit 130 will be described in detail.
FIG. 4 is a block diagram of the data line driving circuit. As shown in the figure, the data line driving circuit 130 includes a shift register 131, image data supply lines Lr, Lg, Lb, a first latch section 132, a second latch section 133, and a DA converter 134.

First, the shift register 131 transfers the transfer start signal DY based on the clock signal CLY from the timing generation circuit 200 and its inverted clock signal CLYINV.
Are sequentially shifted to sequentially output the sampling signals S1 to Sn.

Next, the image data supply lines Lr, Lg, Lb
Is composed of six wires each, and image data DR, DG, and DB supplied in a 6-bit parallel format are:
The image signal is supplied from the image signal processing circuit 300.

Next, the first latch section 132 is configured to latch each of the image data DR, DG, and DB using the sampling signals S1 to Sn, whereby the dot-sequential image data DR ', DG ', DB' can be obtained.

Next, the second latch section 133 uses the first transfer signal TRS1 to perform dot-sequential image data DR ', DG',.
DB ′ is converted into line-sequential image data DR ″, DG ″, DB ″, and thereafter, according to the second transfer signal TRS2 and the third transfer signal TRS3, the line-sequential image data DR ″, D
Image data DRG obtained by converting G '' and DB '' to serial format
It is configured to output B.

Next, the DA converter 134 converts each image signal obtained by DA conversion of the serial data into each data line 11.
4.

Now, the configuration of the first latch section 132 and the second latch section 133 will be described in detail with reference to FIG.
FIG. 5 is a circuit diagram showing a detailed configuration of the first latch unit and the second latch unit.

As shown in this figure, the first latch section 132
Has n units UA1 to UAn corresponding to the number “n” of the data lines 114. On the other hand, the second latch section 134 also includes n units UB1 to UBn.

Further, the unit U of the first latch 133
A1 is the bit number “6” of the image data DR, DG, DB
, Six bit units UA11 to UA16 are provided. The bit units UA12 to UA16 have the same configuration as the bit unit UA11, and each of the bit units UA11 to UA16 has image data DR and D.
The first to sixth bits of G and DB are respectively supplied. In addition, other units UA2 to UAn
Is configured similarly to the unit UA1. On the other hand, the unit UB1 of the second latch unit 133 has six bit units UB11 to UB11 similarly to the first latch unit 132.
The UB 16 is provided. Further, the bit unit UB1
2 to UB16 have the same configuration as the bit unit UB11. In addition, the other units UB2 to UBn are configured similarly to the unit UB1.

First, the bit unit UA11 of the first latch section 132 is connected to the analog switch SW as shown in FIG.
1 and three sets of latch circuits composed of inverters INV1 and INV2. Each set of analog switches SW1
Is supplied with a sampling signal S1. Therefore, when the sampling signal S1 becomes active, the first bit data of the image data DR, DG, and DB is supplied to the inverters INV1 and INV2.
Here, the output signal of the inverter INV1 is
Is fed back to its input terminal through the inverter, so that even if the analog switch SW1 is in a high impedance state, the logic level captured during the period in which the sampling signal S1 is active becomes the inverter.
It will be stored by INV1 and INV2. Therefore, the unit UA11 includes the image data DR, DG, and DB.
Are latched in accordance with the sampling signal S1. Since the sampling signal S1 is also supplied to the units UA12 to UA16 as shown in the figure, the unit UA1 outputs the image data DR, D for the first row.
G and DB are output. Similar processing is performed in units UA2 to UA
This is also performed in An. Thereby, the image data D
R, DG, and DB are converted into dot-sequential image data DR ', DG', and DB 'corresponding to each data line 114.

Next, the bit unit UB11 of the second latch section 133 is composed of subunits UB11r, UB11g and UB11b corresponding to each of R, G and B colors. The analog switch SW2 and the inverters INV3 and INV4 of each subunit function as a latch circuit. The inverter INV4 of the subunit UB11b is controlled by the first transfer signal TRS1, and the subunit UB1b
The inverter INV4 of 1g, UB11r is controlled by an OR circuit OR.

Here, the analog switch SW2 is controlled by the first transfer signal TRS1. First transfer signal TR
S1 is a signal that becomes active at the start of the period in which each scanning line 112 is selected. Therefore, each latch circuit takes in the dot-sequential image data DR ′, DG ′, and DB ′ at the start of the period in which each scanning line 112 is selected, and stores the logic level during the selection period of the scanning line 112. Thereby, the dot-sequential image data DR ′, DG ′,
DB ′ is converted into line-sequential image data DR ″, DG ″, DB ″.

The inverter INV5 of the subunit UB11b and the inverter INV6 of the subunit UB11gr
Functions as a transfer circuit that transfers the output signal of the subunit to the next subunit. In this example, based on the second transfer signal TRS2 and the third transfer signal TRS3, the output signal of the subunit UB11b is changed to the subunit UB11.
g, and the output signal of the subunit UB11g is transferred to the subunit UB11r. Thus, each line-sequential image data DR ″, DG ″, DB ″ is transferred to each data line 1.
14 is converted into serial-format image data DRGB.

<1-4. Operation of Data Line Drive Circuit> Next, the operation of the data line drive circuit 130 will be described.
6 and 7 are timing charts for explaining the operation of the data line driving circuit.

In FIG. 6, when the transfer start signal DY is supplied to the shift register 131 of the data line driving circuit 130, the shift register 131 sequentially shifts the transfer start signal DY according to the clock signal CLY and its inverted clock signal CLYINV. And the sampling signals S1, S2,
.., Sn are output.

Here, the image data DR, DG, DB are
As shown in the figure, it is synchronized with the sampling signals S1 to Sn. Therefore, the first latch unit 132 outputs the image data DR, DG, D based on the sampling signals S1 to Sn.
When B is latched, the dot-sequential image data DR ', DG', D
B ′ will be obtained.

Next, when the first transfer signal TRS1 becomes active (H level in this example) at the start of the selection period of a certain scanning line 112, the dot sequential image data D
R ′, DG ′, DB ′ are latched by the second latch unit 133, and the dot-sequential image data DR ′, DG ′, DB ′ are converted to line-sequential image data DR ″, DG ″, DB ″. .

As shown in FIG. 7, the second transfer signal TRS2
Is a signal that becomes active after the first transfer signal TRS1 changes from active to inactive, and maintains that state during the selection period of the scanning line. The third transfer signal TRS3 is a signal that becomes active after the second transfer signal TRS2 becomes inactive from a non-active state and after a certain period of time elapses, and maintains that state during the selection period of the scanning line.

As shown in FIGS. 6 and 7, during the period from time t10 to time t11, the first transfer signal TRS
When 1 becomes active, each analog switch SW2 of the UB 11 shown in FIG. 5 is turned on. At this time, FIG.
Are data P11R, P11G, and P11B as shown in FIG.

Thereafter, when a predetermined time has elapsed and time t12 is reached, the second transfer signal TRS2 changes from inactive (L) to active (H). Then, since the inverter INV5 of the subunit UB11g becomes active, P11G is transferred to the subunit UB11r and latched by the inverters INV3 and INV4. Therefore, during the period from time t12 to time t13, the signal PR1 becomes “P11G”.

At time t13, the third transfer signal TRS3 changes from inactive (L) to active (H).
Changes to Then, since the sub-unit UB11b and the sub-unit UB11g inverter INV5 become active, P11B is transferred to the sub-unit UB11r. Therefore, during the period from time t12 to time t13, the signal PR1 becomes “P11B”.

The above operation is repeatedly performed for each selection period of each scanning line 112, so that the line-sequential image data DR ″, DG ″, DB ″ supplied in parallel form is converted to serial form image data DRGB. Is converted to

The image data DRGB obtained in this way is
Since the image signal is converted into an analog signal by the A converter 134, an image signal is supplied to each data line 114 in the order of R, G, and B. For example, the image display area 1 shown in FIG.
P11R, P11
G, P11B, P21R, P21G, P21B, ..., P
Image signals are supplied in the order of m1R, Pm1G, and Pm1B.

As described above, in the data line driving circuit 130 of the present embodiment, the dot-sequential image data DR ′, DG ′, DB ′ are converted to the line-sequential image data DR ″, DG ″ in the second latch section 133. , DB '', and these are converted to serial format image data DRGB.
In the vertical stripe pixel configuration shown in (1), an image signal can be supplied from the horizontal direction. As a result, the data line driving circuit 130 can be arranged on the short side LS of the liquid crystal panel 100 as shown in FIG.

<Configuration Example of Liquid Crystal Panel> Next, the overall configuration of the liquid crystal panel 100 having the data line driving circuit 130 according to the above-described embodiment will be described with reference to FIGS. Here, FIG. 8 is a perspective view illustrating a configuration of the liquid crystal panel 100, and FIG. 9 is a cross-sectional view taken along line AA ′ in FIG.

As shown in these figures, the liquid crystal panel 100 is made of a glass on which the pixel electrodes 118 and the like are formed, an element substrate 101 of a semiconductor or quartz, and a transparent material such as a glass on which the common electrodes 108 and the like are formed. With the opposite substrate 102
A gap is maintained by a sealing material 104 mixed with a spacer 103 so that electrode forming surfaces are opposed to each other while maintaining a certain gap, and a liquid crystal 105 as an electro-optical material is sealed in this gap. . Note that the sealant 104 is formed along the periphery of the opposing substrate 102, but has a partly opened opening for enclosing the liquid crystal 105. Therefore, after the liquid crystal 105 is sealed, the opening is sealed by the sealing material 106.

Here, the data line driving circuit 130 described above is formed on the opposite surface of the element substrate 101 on the short side LS side of the sealing material 104 to drive the data line 114 extending in the X direction. Configuration. Further, a plurality of external circuit connection terminals 107 are formed on one side to input various signals from the timing generation circuit 200 and the image signal processing circuit 300. On the long side LL side, two scanning line driving circuits 12
0 is formed, and the scanning lines 112 extending in the Y direction are driven from both sides. If the delay of the scan signal supplied to the scan line 112 does not matter, the scan line drive circuit 120 may be formed on one side only.

On the other hand, the common electrode 108 of the counter substrate 102
Of the four corners of the portion to be bonded to the element substrate 101
By the conductive material provided in at least one place,
Electrical conduction with the element substrate 101 is achieved. In addition, the opposing substrate 102 is first provided with color filters arranged in stripes, and secondly, a metal material such as chromium or nickel, or carbon or titanium is dispersed in a photoresist. Third, a light-shielding film such as resin black is provided. Third, a backlight for irradiating the liquid crystal panel 100 with light is provided.

In addition, an alignment film (not shown) rubbed in a predetermined direction is provided on each of the opposing surfaces of the element substrate 101 and the opposing substrate 102, and each of the back surfaces thereof is arranged in accordance with the alignment direction. Polarizing plates (not shown) are provided. However, when a polymer-dispersed liquid crystal in which fine particles are dispersed in a polymer is used as the liquid crystal 105, the above-described alignment film and polarizing plate are not required, so that the light use efficiency is increased. This is advantageous in terms of low power consumption and the like.

Instead of forming part or all of the peripheral circuits such as the data line drive circuit 120 on the element substrate 101, for example, a drive IC mounted on a film using TAB (Tape Automated Bonding) technology. The chip may be electrically and mechanically connected via an anisotropic conductive film provided at a predetermined position on the element substrate 101, or the driving IC chip itself may be connected to a COG (Chip On Gr.
Ass) technology may be used to electrically and mechanically connect to a predetermined position of the element substrate 101 via an anisotropic conductive film.

As described above, in this embodiment, since the external circuit connection terminals 107 (mounting terminals) are provided on the short side LS side, the external circuit connection terminals 107 (mounting terminals) are provided on the element substrate 101 as compared with the case where they are provided on the long side LL side. Since the area can be reduced, the cost of the liquid crystal panel 100 can be reduced, and the cost of the entire liquid crystal display device can be reduced.

Further, since the data line drive circuit 130 is provided on the short side LS so as to be close to the external circuit connection terminal 107, the data line drive circuit 1
Since the wiring up to 30 can be shortened, the parasitic capacitance of the wiring can be reduced. Therefore, the clock signal CLY and the inverted clock signal CLYINV having a high frequency can be stably supplied to the data line driving circuit 130, and the clock signal CLY and the inverted clock signal CLYINV provided in the timing generation circuit 200 are driven. Therefore, the load of the circuit can be reduced, and the current consumption can be reduced.

In addition, the second of the data line driving circuit 130
In the latch unit 133, the dot sequential image data DR ', D
G ′ and DB ′ are line-sequential image data DR ″, DG ″, DB ″
And further converted to serial image data DRGB, so that the image signal can be supplied from the horizontal direction in the pixel configuration of the vertical stripe shown in FIG. As a result, characters that are easy to read can be displayed clearly without characters being interrupted and becoming difficult to read.

<2. Second Embodiment> Next, a liquid crystal display device according to a second embodiment will be described. The liquid crystal display device of the present embodiment is the same as the liquid crystal display device of the first embodiment except for the detailed configuration of the second latch unit of the data line driving circuit 130. Therefore, the second latch unit will be described.
FIG. 10 is a detailed circuit diagram of the second latch unit 133 'and the first latch unit 132 used in the data line drive circuit of the second embodiment.

The second latch section 133 'is provided for the first latch section 133 shown in FIG.
Like the second latch unit 133 of the embodiment, the unit includes n units UB1 to UBn. And the unit UB
1 is composed of six bit units UB11 'to UB16'. The second latch unit 133 'differs from the second latch unit 133 of the first embodiment in the detailed configuration of the bit unit.

As shown in FIG. 10, bit unit UB1
1 ′ is a subunit UB11r ′, UB11g ′, UB
11b '.

Each subunit UB11r ', UB11
g ′ and UB11b ′ function as a transfer circuit with the analog switch SW2 functioning as a first latch circuit, the inverters INV3, INV4, and the OR circuit OR, and the analog switch SW3 functioning as a second latch circuit and the inverters INV6, INV7. And an analog switch SW4.

First, the analog switch SW2 is turned on when the first transfer signal TRS1 becomes active. Therefore, during the active period of the first transfer signal TRS1, the analog switch SW2 is turned on.
Dot-sequential image data D output from the first latch unit 133
R ′, DG ′, DB ′ are taken into the first latch circuit.
The first transfer signal TRS1 is a signal that becomes active at the start of the selection period of the scanning line 112. Therefore, the dot-sequential image data DR ′, DG ′, D
B ′ is converted into line-sequential image data DR ″, DG ″, DB ″.

Next, the analog switch SW3 is turned on during the inactive period (L level) of the fourth transfer signal TRS4, and is turned off during the active period. Therefore, the second latch circuit takes in the output signal of the first latch circuit during the inactive period of the fourth transfer signal TRS4.

Next, the analog switch SW4 functioning as a transfer circuit is turned on during the active period (H level) of the fourth transfer signal TRS4, and turned off during the inactive period. Therefore, during the active period (H level) of the fourth transfer signal TRS4, the signal PB2 shown in FIG.
b 'through the analog switch SW4
B11g ′ and the signal PG2 is
The signal PR2 is transferred to the subunit UB11r 'via the analog switch SW4 of the subunit UB11r', and the signal PR2 is transferred to the subunit UB11b 'via the analog switch SW4 of the subunit UB11r'. That is, the second latch unit 133 of the second embodiment differs from the second latch unit 133 of the first embodiment in that the subunits are connected in a ring shape in that the subunits are connected in a ring shape. I do. The fourth transfer signal TRS4 is the first transfer signal TRS4.
It becomes active (H level) three times during the next active period after S1 becomes active (H level) (see FIG. 11). Therefore, the second latch unit 133 'of the second embodiment performs the transfer between the sub-units three times during the selection period of a certain scanning line 112, and thus completes the transfer between the sub-units twice. 2nd latch part 13 of form
3 is different.

Next, the operation of the data line driving circuit according to the second embodiment will be described. The data line driving circuit 130 of the second embodiment is the same as that of the first embodiment except for the detailed configuration of the second latch unit. Until dot-sequential image data is generated, the operation is the same as in the first embodiment (see FIG. 6).

FIG. 11 is a timing chart for explaining the operation of the second latch section. During the period from time t10 to time t11, the first transfer signal TRS1 is at H level.
When the level becomes the level, the analog switch SW1 is turned on, and the dot-sequential image data output from the first latch unit 132 is taken into the second latch unit 133. As a result, during the period, the signals PR1, PG1, PB1
Is data P11 corresponding to pixel P11 in the first row and the first column
R, P11G, and P11B. In addition, during the period, since the fourth transfer signal TRS4 is at the L level, the analog switch SW2 is on.
For this reason, the output signals PR1, PG1,
PB1 is taken into the second latch circuit. Therefore,
Signals PR2, PG2, and PB2 correspond to data P11R and P1.
1G and P11B.

Next, during the period from time t11 to time t12, since both first transfer signal TRS1 and fourth transfer signal TRS4 are at L level, inverter IN
V4 enters the operating state, and the logic level is held by the inverters INV3 and INV4. Therefore, during this period, the signals PR1, PG1, and PB1 output the data P11R, P
11G and P11B. Also, during that period,
Since the analog switch SW2 is on,
Signals PR2, PG2 and PB2 are data P11R and P11.
G, P11B.

Next, during the period from time t12 to time t13, the fourth transfer signal TRS4 goes high. Then, the analog switch SW3 is turned on, and data transfer between the subunits is performed. Specifically, the data is UB11b ′ → UB11g ′ → UB11r ′
→ Data is simultaneously transferred in the direction of UB11b '. At this time, since the analog switches SW2 and SW3 are in the off state, the data transferred from the preceding subunit is held by the first latch circuit, while the second latch circuit is in the period before the time t12. Maintain state. Therefore, during the period, the signal PR
1, PG1, PB1 are data P11G, P11B, P1
On the other hand, the signals PR2, PG2, and PB2 become data P11R, P11G, and P11B.

Next, during the period from time t13 to time t14, the analog switch SW3 is turned on and the analog switches SW2 and SW4 are turned off.
The signals PR1, PG1, PB1 and the signals PR2, PG2, P
B2 and the data P11G, P11B, P1
1B.

Thereafter, the second latch unit 133 'operates at time t1.
In the period from time t15 to time t14, the operation is the same as the period from time t12 to time t13 in the period from time t15 to time t13.
The operation is the same as in the period up to. Therefore, the signal PR
1, PG1, PB1 and signals PR2, PG2, PB2 change as shown in the figure.

Here, the output signal P of the second latch 133
Focusing on R2, during the period from time t10 to time t17, the signal PR2 is P11R → P11G → P11B
In the order of That is, the line-sequential image data D
R ″, DG ″, DB ″ are converted to serial format image data DRGB
Has been converted to.

By the way, the subunits of the present embodiment are connected in a ring shape, and before the time t18 at which the first transfer signal TRS1 becomes active again, the fourth transfer signal TRS
4 becomes active three times. The third active period is a period TA from time t16 to time t17 shown in the figure.
It is. By providing the period, the line-sequential image data captured in the period from time t10 to time t11 is input to each subunit. For example, in the subunit UB11r ′, the data P11R is taken in a period from time t16 to time t17. Thus, during the period from time t17 to time t18, signals PR1, PG1, PB1 and signal PR
2, PG2, and PB2 match, and data P11R,
P11G and P11B.

The line sequential image data DR ″, DG ″,
If DB '' is to be converted into serial image data DRGB, the subunits are connected linearly as in the first embodiment, and the fourth transfer signal TR is output during one scanning line selection period.
It is enough to activate S4 twice. However,
In the second embodiment, the subunits are connected in a ring shape as described above, and the third active period TA is provided. This is for the following reason.

Since the correlation between image signals is extremely high, the image data value does not often change between adjacent pixels.
On the other hand, the second latch unit 133 ′ is configured by p-channel and n-channel TFTs.
Consumes power when the logic level changes, and if the logic level does not change, little power is consumed.

As described above, the third active period T
A indicates that the signals PR1, PG1, P
B1 and the signals PR2, PG2, PB2 have returned to the initial state in the scanning line selection period. In this state, when the first transfer signal TRS1 becomes active next time, the dot-sequential image data DR ′,
DG 'and DB' correspond to adjacent pixels.
For example, focusing on the subunit UB11r ', the signal PR1 changes from data P11R to data P21R around time t18. Data P11R is R of pixel P11.
P21R corresponds to a pixel P11.
Corresponds to the R pixel area of the pixel P21 adjacent to. Therefore, the value of data P11R and data P21R
Are very likely to match. Therefore, at the time when the first transfer signal TRS1 becomes active (for example, at time t18), it is possible to significantly reduce the power consumed.

On the other hand, by providing the third active period TA, the state of each subunit changes three times during one scanning line selection period, and the power consumption increases accordingly. However, the state change due to the active period TA is performed within the same pixel. For example, by providing the period TA in the subunit UB11r ', the signals PR1 and PR2 change from the data P11B to the data P11R. Here, the image signal processing circuit 3
The image data DR, DG, and DB supplied from 00 are normalized to have the same value when displaying an achromatic image such as white, black, or gray as described above. Therefore, when the image to be displayed is achromatic, power consumption does not increase even if the period TA is provided. In particular, text displayed on a computer monitor is often black and its background is often white. Therefore, in particular, when the liquid crystal display device is used for display of a computer, the power consumption does not increase due to the provision of the period TA. Therefore, the power consumption can be reduced by connecting the subunits in a ring and providing the third active period TA.

<3. Modifications> (1) In each of the above embodiments, the liquid crystal panel 10
The element substrate 101 is made of a transparent insulating substrate such as glass, a silicon thin film is formed on the substrate, and the switching element of the pixel is formed by a TFT having a source, a drain and a channel formed on the thin film. (TF
T116) and the elements of the drive circuit 120 have been described, but the present invention is not limited thereto.

For example, the element substrate 101 is composed of a semiconductor substrate, and the switching element and the driving circuit 1 of the pixel are formed by an insulated gate field effect transistor having a source, a drain and a channel formed on the surface of the semiconductor substrate.
Twenty elements may be configured. Thus, the element substrate 10
When the pixel electrode 11 is made of a semiconductor substrate, the pixel electrode 11 cannot be used as a transmissive display panel.
8 is formed of aluminum or the like, and is used as a reflection type. Alternatively, the element substrate 101 may simply be a transparent substrate and the pixel electrode 118 may be of a reflection type.

(2) Furthermore, in each of the above-described embodiments, the switching element of the pixel is described as a three-terminal element represented by a TFT, but may be formed of a two-terminal element such as a diode. However, when a two-terminal element is used as a pixel switching element, the scanning line 112 is formed on one substrate, the data line 114 is formed on the other substrate, and the two-terminal element is connected to the scanning line 112 or the data line. It is necessary to form between any one of the pixel electrodes 114 and the pixel electrode. In this case, the pixel includes a two-terminal element connected in series between the scanning line 112 and the data line 114, and a liquid crystal.

(3) The present invention has been described as an active matrix type liquid crystal display device. However, the present invention is not limited to this, and can be applied to a passive type using STN (Super Twisted Nematic) liquid crystal. Further, as the electro-optical material, in addition to the liquid crystal, the present invention can be applied to a display device which uses an electroluminescence element or the like to perform display by the electro-optical effect. That is, the present invention
The present invention is applicable to all electro-optical devices having a configuration similar to that of the above-described liquid crystal display device.

(4) In each of the above-described embodiments, the pixel regions R, G, and B respectively corresponding to the three primary colors of RGB are formed along the data lines 114, but the present invention is not limited thereto. The present invention is not limited to this, and may display a plurality of colors. In this case, the image data corresponding to each color is converted into dot-sequential image data, this is converted into line-sequential image data, and the line-sequential image data corresponding to each color is subjected to parallel-serial conversion to obtain a serial format image. Data may be generated corresponding to each data line, and the obtained image data may be subjected to DA conversion and output to each data line.

<4. Application Examples> Next, the case where the above-described liquid crystal display device is applied to various electronic devices will be described.

<Part 1: Mobile Computer> First, an example in which this liquid crystal panel is applied to a mobile personal computer will be described. FIG. 12 is a perspective view showing the configuration of the personal computer. In the figure, a computer 1200 includes a keyboard 120
And a liquid crystal display unit 120 provided with
6 is comprised. This liquid crystal display unit 120
6 is configured by adding a backlight to the back surface of the liquid crystal panel 100 described above.

<Part 2: Cellular Phone> An example in which the liquid crystal panel 100 is applied to a cellular phone will be described. FIG. 13 is a perspective view showing the configuration of the mobile phone. In the figure, a mobile phone 1302 includes a reflective liquid crystal panel 100 together with a plurality of operation buttons 1302. In this reflection type liquid crystal panel 100, a front light is provided on the front surface as needed.

In addition to the electronic devices described with reference to FIGS. 12 and 13, a single-plate type video projector, a liquid crystal television, a viewfinder type or a monitor direct-view type video tape recorder, a car navigation device, a pager , An electronic organizer, a calculator, a word processor, a workstation, a videophone, a POS terminal, a device having a touch panel, and the like. It goes without saying that the present invention can be applied to these various electronic devices.

[0108]

As described above, according to the present invention, it is possible to provide an electro-optical panel in which characters can be easily read while manufacturing costs are reduced. Further, a data line driving circuit and a driving method for driving the data lines of the electro-optical panel can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an overall configuration of a liquid crystal display device according to a first embodiment of the present invention.

FIG. 2 is a conceptual diagram showing pixels forming an image display area in the device.

FIG. 3 is a block diagram illustrating a configuration of an image processing circuit in the device.

FIG. 4 is a block diagram showing a configuration of a data line driving circuit of the device.

FIG. 5 is a circuit diagram showing a configuration of first and second latch units of the same device.

FIG. 6 is a timing chart showing the operation of the data line drive circuit of the device.

FIG. 7 is a timing chart showing the operation of the data line drive circuit of the device.

FIG. 8 is a perspective view showing a structure of the liquid crystal panel.

FIG. 9 is a partial cross-sectional view illustrating the structure of the liquid crystal panel.

FIG. 10 is a circuit diagram showing a configuration of first and second latch units used in a second embodiment of the present invention.

FIG. 11 is a timing chart showing the operation of the second latch unit.

FIG. 12 is a perspective view showing a configuration of a personal computer as an example of an electronic apparatus to which the liquid crystal display device is applied.

FIG. 13 is a perspective view illustrating a configuration of a mobile phone as an example of an electronic apparatus to which the liquid crystal display device is applied.

FIG. 14 is a block diagram illustrating a main part of a conventional horizontally long liquid crystal panel.

FIG. 15 is a block diagram showing a main part of a conventional vertically long screen liquid crystal panel.

FIG. 16 is a conceptual diagram showing an example in which a character “X” displayed in green is displayed on a horizontal stripe screen.

[Explanation of symbols]

 100 liquid crystal panel 107 external circuit connection terminal (mounting terminal) 110 image display area 112 scanning line 114 data line 116 TFT 130 data line drive circuit 132 first latch unit (1st conversion part) 133, 133 '... 2nd latch part (2nd conversion part) 134 ... DA conversion part (DA converter) 300 ... Image processing circuit (image processing part) UB1-UBn ... Unit UB11r , UB11g, UB11b ... sub-unit

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 3/20 623 G09G 3/20 623R 660 660F 3/36 3/36 F term (Reference) 2H092 GA05 GA23 GA40 JA24 JB02 NA25 PA06 2H093 NA42 NA43 NC10 NC12 NC13 NC14 NC15 NC24 NC26 NC28 NC34 NC90 ND42 ND54 NE03 NE07 NF05 NF13 5C006 AA16 AA22 AC09 AF06 AF83 BB12 BB16 BC03 BC12 BC16 BF02 BF03 BF04 BF15 ABF12 BF27 A21 FA21 FB27 JJ02 JJ03 JJ04 JJ05 JJ06 KK07 KK47 5C094 AA02 AA15 AA22 AA44 AA48 AA53 BA03 BA43 CA19 CA24 CA25 DA09 DB01 DB02 DB04 EA04 EA07 EA10 FA01 FB12 FB13 FB15 GA10

Claims (11)

[Claims] 1. An electro-optical panel comprising: a plurality of data lines; a plurality of scanning lines; switching elements provided corresponding to respective intersections thereof; and pixel electrodes connected to the switching elements. A data line driving method, wherein image data corresponding to a plurality of colors is converted into dot-sequential image data of a number corresponding to the number of data lines, and the dot-sequential image data is latched for each scanning line selection cycle. And converts the line-sequential image data of each color into parallel-serial conversion, generates serial data corresponding to each data line, and DA-converts each serial data to obtain each image signal. Generating an image signal and supplying each image signal to each data line. 2. An electro-optical panel comprising: a plurality of data lines; a plurality of scanning lines; switching elements provided corresponding to respective intersections thereof; and pixel electrodes respectively connected to the switching elements. A data line driving circuit, comprising: a first conversion unit that converts image data corresponding to a plurality of colors into a number of dot-sequential image data according to the number of data lines; A second conversion unit that latches each time and converts the data into line-sequential image data, performs parallel-serial conversion on the line-sequential image data of each color, and generates each serial data corresponding to each data line; A data converter for supplying each image signal obtained by DA conversion of serial data to each data line. 3. The second conversion unit includes units corresponding to data lines, one unit cascade-connects sub-units corresponding to each color, and each sub-unit selects the scanning line. A latch circuit that latches the dot-sequential image data at the start of a period, and a transfer circuit that transfers an output signal of each subunit to an input of the latch circuit of a next-stage subunit during the selection period of the scanning line. The data line drive circuit for an electro-optical panel according to claim 2, wherein: 4. The image data is three types of data for a first color, a second color, and a third color, respectively, and the second conversion unit includes a first color, a second color, and a third color. The unit outputs the serial data that has been subjected to the parallel-serial conversion in the following order: a first sub-unit corresponding to a first color and extracting the serial data; and a second sub-unit provided at a stage preceding the first sub-unit. A corresponding second sub-unit, and a third sub-unit provided before the second sub-unit.
A third sub-unit corresponding to a color, wherein the latch circuit of each sub-unit latches the dot-sequential image data based on a first transfer signal that is active at the start of the scanning line selection period. The transfer circuit of the third sub-unit is configured to perform an active period of the first transfer signal based on a second transfer signal that is active for a period from a point in time when a predetermined time has elapsed to a point in time when the selection period of the scanning line ends. An output signal of the third sub-unit is transferred to an input of the second sub-unit, and the transfer circuit of the second sub-unit is configured such that a predetermined time has elapsed since the second transfer signal transited from inactive to active. Based on the third transfer signal that is active during the period until the scanning line selection period ends, the second
4. The data line driving circuit according to claim 3, wherein an output signal of the sub-unit is transferred to an input of the first sub-unit. 5. The second conversion unit includes units corresponding to data lines, and one unit includes sub-units corresponding to respective colors connected in a ring, and each sub-unit is connected to the scan line. A latch circuit that latches the dot-sequential image data at the start of a selection period; and a transfer circuit that transfers an output signal of each sub-unit to an input of the latch circuit of a next-stage sub-unit during the selection period of the scanning line. The data line drive circuit for an electro-optical panel according to claim 2, wherein: 6. The image data is three types of data for a first color, a second color, and a third color, respectively, and the second conversion unit includes a first color, a second color, and a third color. The unit outputs the serial data that has been subjected to the parallel-serial conversion in the following order: a first sub-unit corresponding to a first color and extracting the serial data; and a second sub-unit provided at a stage preceding the first sub-unit. A corresponding second sub-unit, and a third sub-unit provided before the second sub-unit.
A third sub-unit corresponding to a color, wherein the latch circuit of each of the sub-units latches the dot-sequential image data based on a first transfer signal that is active at the start of the scanning line selection period. The transfer circuit of each subunit determines the next transfer signal based on the second transfer signal that is active three times during the period from the time when the first transfer signal changes from active to inactive to the end of the scanning line selection period. 6. The data line driving circuit for an electro-optical panel according to claim 5, wherein an output signal of a stage is transferred to an input of a sub-unit of a subsequent stage. 7. An electro-optical panel comprising a data line driving circuit for an electro-optical panel according to claim 2 and a horizontally long image area, wherein the image area is arranged in a horizontal direction. A plurality of data lines extending, a plurality of scanning lines extending in the vertical direction, switching elements provided corresponding to their intersections, and pixel electrodes connected to the switching elements, respectively. An electro-optical panel, characterized in that: 8. The image area has a vertically long pixel area divided by each of the scanning lines and each of the data lines, and the data line driving circuit is arranged on a short side. An electro-optical panel according to item 1. 9. A scanning line driving circuit for driving the scanning lines on a long side, and a mounting terminal is disposed at an end on a short side close to the data line driving circuit. 8. The electro-optical panel according to 7. 10. An electro-optical panel according to claim 2, further comprising: an image processing unit that interchanges a relationship between a row and a column of input image data and supplies the input image data to the electro-optical panel. An electro-optical device characterized by the above-mentioned. 11. An electronic apparatus comprising the electro-optical device according to claim 11 as a display unit.