JP2001194425A - Integrated circuit and lot-sorting system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily discriminated a nondefective from a defective, by measuring the jitter value of a PLL circuit without increasing the cost for a testing. SOLUTION: In a phase-error generation circuit 9 for a test circuit which is mounted on the integrated circuit, a reference signal Fref and a frequency division signal Fvar of the PLL circuit which is mounted on the integrated circuit are input, a phase error between both is found, and a phase error signal Esig is generated so as to be output to an integrator 10. The integrator integrates the input phase error signal Esig, so as to generate an integrated voltage Verr corresponding to the phase error to be output to a voltage comparator 11. The voltage comparator compares the input integrated voltage Verr with a reference voltage Vref. When the integrated voltage Verr is larger than the reference voltage Vref, a high-level signal which indicates the defective is output. When the integrated voltage Verr is smaller than the reference voltage Vref, a low-level signal which indicates the nondefective is output. Consequently, by merely detecting the binary output of the voltage comparator, it is possible to immediately detect whether the integrated circuit is nondefective or defective.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL (Phase Lo
related to an integrated circuit equipped with a cked Loop) circuit and a lot selection system for selecting good and defective products of the integrated circuit.
In particular, the present invention relates to a test circuit for testing characteristics of a PLL circuit.

[0002]

2. Description of the Related Art In recent years, in a PLL (Phase Locked Loop) circuit, a characteristic that a frequency generated with respect to a reference frequency has low jitter and high stability has been required. Therefore, a jitter value of a frequency generated by a PLL (Phase Locked Loop) circuit is accurately measured by a test circuit, and a good product and a defective product are selected. FIG. 15 is a block diagram showing a configuration example of a basic PLL circuit according to the related art. Phase comparator (hereinafter PFD)
A reference signal Fref having a reference frequency is input to one input terminal of an input terminal 1 and an output signal Fout of a frequency oscillated by a voltage controlled oscillator (hereinafter abbreviated as VCO) 4 is input to the other input terminal. A frequency-divided signal Fvar having a frequency (Fout / N) obtained by dividing the frequency by N with a frequency divider (DIV) 5 is input. Here, the PFD 1 determines whether the UP signal and the DOWN signal correspond to the phase state of the frequency Fout / N and the reference frequency Fref.
Output a signal.

The UP signal and the DOWN signal output from the PFD 1 are input to a charge pump (CP) circuit 2, and the CP circuit 2 outputs a high level while the UP signal is output. Also, while the DOWN signal is being output, the CP circuit 2 outputs a low level.

[0004] Here, the PFD1 has a frequency Fout / N lower than Fref or is delayed in phase.
The UP signal is output only during the delay period. And
The CP circuit 2 to which the UP signal is input outputs a high level. This high-level pulse is integrated by a low-pass filter (hereinafter abbreviated as LPF) 3 to become a DC level.

If the LPF 3 is a passive filter composed of a resistor and a capacitor, the output level of the LPF 3 is higher than in the previous state. As a result, the VCO 4 oscillates at a higher frequency than the previous oscillation frequency. If this Fout / N is still lower than Fref, the same process as before is followed, and a higher frequency is oscillated.

As a result, if Fout / N is higher than Fref, the PFD 1 outputs the DOWN signal for the same period as the phase difference, contrary to the previous case. Then, the CP circuit 2 to which the DOWN signal has been input outputs a low level. This low-level pulse is integrated by the LPF 3 to become a DC level.

[0007] The output level of the LPF 3 is lower than in the previous state. As a result, the VCO 4 oscillates at a lower frequency than the previous oscillation frequency. Fo several times like this
ut / N and Fref are compared, and a loop operates so as to constantly eliminate the phase error. And finally, Fout
The phase difference between / N and Fref becomes zero. As a result, PFD
1, the CP circuit 2 in which neither the UP signal nor the DOWN signal is output, and neither the UP signal nor the DOWN signal is input.
Is in a high impedance state, and LPF3
Keeps the same level as the previous state. As a result, the VCO 4 also maintains the same frequency as the previous oscillation frequency.

The output frequency (Fout) of the PLL is determined by the reference frequency (Fref) and the frequency division number (N) of the frequency divider. Fout = Fref × N, and the output frequency (Fout) is the reference frequency (Fref).
The frequency becomes the frequency multiplied by N in f).

Here, when disturbance such as noise is applied to the PLL circuit, the generated output frequency fluctuates according to the power of the disturbance. The fluctuating output frequency is P
The frequency returns to the original frequency by the feedback control of the LL circuit.

However, when the disturbance occurs periodically, the generated output frequency repeats a periodic change. In addition to the disturbance, when a problem occurs in the loop of the PLL circuit due to a process or the like, the stability of the loop response is impaired by the fluctuation of the loop response, and the generated output frequency also varies periodically. May occur. This fluctuation amount of the output frequency is called jitter, and is an important factor indicating the performance of the PLL circuit.

Therefore, in the case of a product that requires high-precision jitter performance or a case where the jitter performance does not have a sufficient margin with respect to the required performance, the jitter value is measured to discriminate a good product from a defective product. There is a need to do. Usually PL
In order to measure the jitter value of the output frequency such as L, a dedicated high-precision measuring instrument such as a time interval analyzer is used.

The technical field of the test circuit for the PLL circuit includes LSIs such as a microcomputer (MCU) and a digital signal processor (DSP).
It is an auxiliary circuit of a PLL circuit used to generate a high-frequency clock for internal use. These PLL technologies are:
A low frequency clock is used as the external clock of the LSI,
By using a high-frequency clock as the internal clock of I, it is used in an application field where the processing performance of the LSI is improved or the power of the entire system is suppressed.

A dedicated and high-precision measuring instrument such as a time interval analyzer is expensive and requires a long measuring time. Therefore, when used in mass production of LSIs and the like, the test cost is low. Has led to a rise.
Further, since the PLL circuit is very susceptible to disturbance such as noise, it is necessary to adjust the measurement substrate and the measurement environment, which makes it difficult to measure the jitter value of the PLL circuit with high accuracy. For this reason, it is difficult to measure the jitter value of the PLL mounted on the integrated circuit and quickly sort out good and defective products.

If the duty ratio of the output signal is not 50% in addition to the jitter performance as the performance of the PLL circuit, the processing performed in synchronization with the period when the duty ratio is 50% or less may not be possible due to a shortage of time. There is. Therefore, it is measured how much the duty value of the output signal deviates from 50%, and the duty value of the output signal is 50%.
It is required to select a PLL circuit that satisfies the following condition, but such a measurement has not been performed so far.
It is the current situation.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to measure a jitter value of a PLL circuit and easily determine a non-defective product without increasing test cost. A good product can be determined.
Provided is an integrated circuit capable of easily measuring a deviation of a duty value of an L circuit, and a lot selection system capable of quickly and automatically selecting good and defective integrated circuits equipped with a PLL circuit. That is.

[0015]

In order to achieve the above object, a feature of the present invention is that a signal obtained by dividing the oscillation signal of the voltage controlled oscillator and a reference signal are inputted, and a phase error signal of both signals is inputted. A phase error generation circuit that detects the error, an integration circuit that integrates an error signal output by the phase error generation circuit, a reference voltage generation circuit that generates a predetermined reference voltage, and an integration result voltage output from the integration circuit. A voltage comparison circuit for comparing the reference voltage generated by the reference voltage generation circuit.

According to the first aspect of the present invention, in the normal PLL circuit, the feedback control operates so as to reduce the phase error between the reference signal and the signal obtained by dividing the output signal of the voltage controlled oscillator. When the value is small, the phase error between the two becomes small, and therefore, the integrated voltage Verr of the phase error generated by integrating the phase error signal also becomes small. Conversely, when the jitter value is large, the reference signal and V
The phase error of both of the signal Fvar obtained by dividing the output signal of the CO increases, and accordingly, the integrated voltage Verr of the phase error generated by integrating the phase error signal also increases. Therefore, as described above, the jitter value can be easily evaluated indirectly by integrating the phase error signal in the time axis direction and converting it into a voltage value Verr, and comparing this voltage value with a reference value. it can.

According to a second aspect of the present invention, the phase error generating circuit receives a DOWN signal and an UP signal generated by a phase comparator used in a PLL circuit, and obtains a logical sum of the two signals. Become.

According to a third aspect of the present invention, the phase error generating circuit includes a first frequency dividing circuit for dividing a signal obtained by dividing the oscillation signal of the voltage controlled oscillator, and a second frequency dividing circuit for receiving and dividing a reference signal.
And an exclusive OR circuit for taking the exclusive OR of the divided signals output from the first and second frequency divider circuits.

According to a fourth aspect of the present invention, a first integration circuit for inputting and integrating a non-inverted signal of an oscillation signal of a voltage controlled oscillator, and a second integration circuit for inputting and integrating an inverted signal of the oscillation signal.
And a subtraction circuit for obtaining a difference between the integration result voltages output from the first and second integration circuits.

A fifth aspect of the present invention is characterized in that a first integration circuit for inputting and integrating a non-inverted signal of an oscillation signal of a voltage controlled oscillator, and a second integration circuit for inputting and integrating an inverted signal of the oscillation signal.
An integration circuit, a subtraction circuit that takes a difference between integration result voltages output from the first and second integration circuits, a reference voltage generation circuit that generates a reference voltage higher and lower than a predetermined intermediate potential, A first voltage comparison circuit for comparing a difference voltage output from the subtraction circuit with a high reference voltage generated by the reference voltage generation circuit; and a difference voltage output from the subtraction circuit and generated by the reference voltage generation circuit. A second voltage comparison circuit for comparing the obtained low reference voltage, and the first and second voltage comparison circuits.
And a logical sum circuit for calculating a logical sum of the comparison results output from the voltage comparison circuit.

According to a sixth aspect of the present invention, there is provided a phase error generating circuit for inputting a frequency-divided signal of an oscillation signal of a voltage controlled oscillator and a reference signal to detect a phase error signal of the two, and the phase error generating circuit. An integration circuit that integrates the error signal output by the reference voltage generator, a reference voltage generation circuit that generates a predetermined reference voltage, and a comparison between the integration result voltage output from the integration circuit and the reference voltage generated by the reference voltage generation circuit. A voltage comparison circuit, a judgment circuit for judging pass / fail of an LSI chip on which each of the circuits is mounted based on a comparison result output from the voltage comparison circuit, and the LSI based on a judgment result of the judgment circuit
And a lot sorter for sorting chips.

The invention according to claim 7 is characterized in that a first integration circuit for inputting and integrating a non-inverted signal of an oscillation signal of a voltage controlled oscillator, and a second integration circuit for inputting and integrating an inverted signal of the oscillation signal.
An integration circuit, a subtraction circuit that takes a difference between integration result voltages output from the first and second integration circuits, a reference voltage generation circuit that generates a reference voltage higher and lower than a predetermined intermediate potential, A first voltage comparison circuit for comparing a difference voltage output from the subtraction circuit with a high reference voltage generated by the reference voltage generation circuit; and a difference voltage output from the subtraction circuit and generated by the reference voltage generation circuit. A second voltage comparison circuit for comparing the obtained low reference voltage, and the first and second voltage comparison circuits.
An OR circuit that takes a logical sum of the comparison results output from the voltage comparison circuits, and a determination circuit that determines the acceptability or failure of the LSI chip mounting each of the circuits based on the comparison results output from the OR circuit. A lot sorter that sorts the LSI chip according to the determination result of the determination circuit.

[0023]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a first embodiment of a test circuit mounted on the integrated circuit of the present invention. The test circuit mounted on the integrated circuit of the present embodiment includes a reference signal Fref of a PLL circuit (not shown) mounted on the integrated circuit and a signal Fvar obtained by dividing the output signal of the VCO.
And obtain a phase error between the two to obtain a phase error signal Esi
g, and a phase error integrated voltage Verr by integrating the generated phase error signal Esig.
And an integrated voltage Verr of the phase error
And a reference voltage Vref, and a reference voltage generation circuit 12 for generating a reference voltage Vref and supplying the reference voltage Vref to the voltage comparator 11.

The reference signal Fref and the divided signal Fvar
Is a reference signal Fref and a frequency-divided signal Fva of a PLL circuit (not shown) mounted on the integrated circuit as shown in FIG.
r.

Next, the operation of this embodiment will be described. The test circuit mounted on the integrated circuit of this embodiment measures a basic jitter value of the PLL circuit mounted on the integrated circuit. The phase error generation circuit 9 receives the reference signal Fref and the frequency-divided signal Fvar, obtains a phase error between them, generates a phase error signal Esig, and outputs this to the integrator 10. The integrator 10 generates the phase error signal Esig
To generate an integrated voltage Verr corresponding to the phase error, and output this to the voltage comparator 11. The voltage comparator 11 compares the input integrated voltage Verr with the reference voltage Vref.
If the integrated voltage Verr is higher than the reference voltage Vref, a high level (“1”) is output. If the integrated voltage Verr is lower than the reference voltage Vref, a low level (“0”) is output.

Here, in the normal PLL circuit, the reference signal F
Since the feedback control operates so as to reduce the phase error between the ref and the signal Fvar obtained by dividing the output signal of the VCO, when the jitter value is small, the phase error between the two becomes small. , The integral voltage Verr of the phase error generated by integrating is also reduced.

Conversely, when the jitter value is large, the reference signal Fref and the signal Fvar obtained by dividing the output signal of the VCO are output.
Of the phase error signal, the integrated voltage Verr of the phase error generated by integrating the phase error signal also increases. Therefore, as described above, the phase error signal Esig in the time axis direction is converted into the voltage value Verr, and the jitter value can be easily evaluated indirectly based on the voltage value.

That is, if the integrated voltage Verr output from the integrator 10 is small, it can be determined that the jitter value of the PLL circuit is small, and if the integrated voltage Verr is large,
It can be determined that the jitter value of the PLL circuit is large.

If the reference voltage input to the voltage comparator 11 is set to an appropriate value for distinguishing a good product having a small jitter value from a defective product having a large jitter value, the output of the voltage comparator 11 becomes When it is at the high level ("1"), it is determined to be defective, and when it is at the low level ("0"), it is determined to be non-defective.

According to this embodiment, a test circuit is mounted on an integrated circuit on which a PLL circuit is mounted, and the jitter value of the PLL circuit of the integrated circuit is small due to a binary signal output from the test circuit. It can be easily and quickly determined whether the PLL circuit of the integrated circuit is a defective product having a large jitter value.

In addition, by incorporating a test circuit for measuring the jitter value of the PLL circuit on an LSI chip (integrated circuit), although the chip cost is slightly increased by the additional circuit, the measurement time is shortened and the cost is increased. Since a measuring instrument can be eliminated, test costs can be significantly reduced.

Further, it contributes to the improvement of the throughput, etc.
It is also possible to reduce the total chip cost. Further, by incorporating the test circuit on the LSI chip, it is possible to make the measurement environment less susceptible to disturbance such as noise related to the measurement environment, and to simplify the adjustment of the measurement substrate and the measurement environment.

FIG. 2 is a circuit diagram showing the configuration of the first embodiment of the phase error generating circuit shown in FIG. 1 and a waveform diagram showing operation timing waveforms. In FIG. 2A, the phase error generation circuit includes a phase comparator (PFD) 13 and an OR circuit 14.

The phase comparator 13 uses a signal used in the PLL circuit, inputs a reference signal Fref and a signal Fvar obtained by dividing the output frequency of the VCO, and outputs an UP signal which is a phase difference signal between the two signals. And a DOWN signal.
The OR circuit 14 outputs the signal shown in FIG.
The logical sum (OR) of the UP signal and the DOWN signal as shown in FIG. 2B is obtained, and the obtained signal is output as the phase error signal Esig as shown in FIG. 2B. Therefore, the configuration of the phase error generator is substantially a configuration of only the two-input OR circuit 14.

FIG. 3 is a circuit diagram showing the configuration of the second embodiment of the phase error generating circuit shown in FIG. 1 and a waveform diagram showing the operation timing. In FIG. 3A, the phase error generating circuit includes half frequency dividing circuits 15 and 16, and an exclusive OR circuit (EX-OR) circuit 17.

The reference signal Fref as shown in FIG.
And the signal Fvar obtained by dividing the output frequency of the VCO are halved by 1/2 frequency dividers 15 and 16, respectively.
ref2 and Fvar2, and are shaped into a waveform with a duty value of 50%. The EX-OR circuit 17 takes an exclusive OR (EX-OR) of a signal obtained by dividing the waveform-shaped reference frequency and the waveform-shaped output frequency of the VCO, and outputs the result as a phase error signal Esig.

FIG. 4 is a circuit diagram showing a first embodiment of the integrator shown in FIG. The integrator calculates the phase error signal Esi
inverter 18 for inverting the polarity of g, and a phase error signal Es
a NOR circuit 19 for NORing a signal obtained by inverting the polarity of ig and a control signal CHGTMG for controlling the integration period, a constant current source 20 having one connected to a power supply voltage, and a constant current source 20 inserted between the constant current source 20 and the output terminal The storage switch circuit 21 controlled by the NOR output of the NOR circuit 19, the discharge switch circuit 22 inserted between the output terminal and the ground potential and controlled by the control signal CHGTMG, the output terminal and the ground potential And a capacitive element 23 connected between them.

The operation of the integrator is performed at the timing shown in FIG. As shown in FIG. 6A, the control signal CH
When GTMG goes high, the storage switch circuit 21
Is turned off, the NOR output goes high, and the discharge switch circuit 21 is turned on. Then, the electric charge accumulated in the capacitive element 23 is discharged by the discharging switch circuit 21, and the potential of the output voltage Verr becomes the ground potential.

Next, when the control signal CHGTMG goes low, the storage switch circuit 21 switches the phase error signal Esig.
Is turned on at a high level of the switch circuit 2 for discharging.
2 is turned off. And the storage switch circuit 21
When charge is accumulated in the capacitive element 23 through the
The potential of err gradually increases. FIG. 6B is an enlarged view showing the waveform of the output voltage Verr at a certain time and the phase error signal Esig at that time.

The potential of the output voltage Verr depends on the high-level time of the phase error signal Esig, and rises sharply when the high-level time is long, and rises slowly when the time is short. The high level time of the phase error signal Esig depends on the phase error between the reference signal Fref and the signal Fvar obtained by dividing the output frequency of the VCO, that is, the jitter value.

Therefore, when the output voltage is observed for a fixed time from the fall of the control signal CHGTMG, the output voltage increases as the jitter value increases. Then, the jitter value can be estimated by measuring the output voltage. However, it is necessary to measure the correlation between the jitter value and the output voltage value in advance.

Next, in the test circuit of FIG.
As shown in (c), when a binary output of the control signal CHGTMG is observed for a certain period of time from the fall,
When the jitter value is large, the output becomes high level, and when the jitter value is small, the output becomes low level. In this case, the control signal CH
The time from the rise of GTMG to the time of observation of the high-level output depends on the jitter value. The jitter value can be estimated by measuring the time. However, it is necessary to measure the correlation between the jitter value and the time in advance.

Therefore, if the measurement time is set to a time corresponding to the jitter value in the specification, if the binary output of the output is a high-level output at the set measurement, the jitter value is considered to be larger than the specification. Can be Therefore, it is possible to determine whether the jitter value is smaller or larger than the specification, depending on whether the binary output of the output during the set measurement is the low level output or the high level output. That is, as described above, it is possible to easily determine whether the integrated circuit on which the PLL circuit is mounted is good or defective.

FIG. 5 is a circuit diagram showing a second embodiment of the integrator shown in FIG. This example is the same as the circuit shown in FIG. 4 except that the power supply voltage is directly connected to one terminal of the storage switch circuit 21, and can perform the same operation.

FIG. 7 shows a PL mounted on the integrated circuit of the present invention.
FIG. 2 is a block diagram showing a first embodiment of a test circuit for measuring a duty value of an L circuit. The test circuit of the present example is a non-inverted signal F of the output signal of the VCO of the PLL circuit.
out, an integrator 25 for integrating an inverted signal / Fout of the output signal, and integrators 24, 2
5 is provided with a subtractor 26 for subtracting the integral value of 5.

Next, the operation of this embodiment will be described. The integrators 24 and 25 separately integrate the non-inverted signal FOUT and the inverted signal / FOUT of the output signal of the VCO, and input a signal indicating the result of the integration to the subtractor 26. The subtractor 26 calculates the difference between the input output signals of the integrators 24 and 25 and outputs the result as an output voltage Vduty.

Here, each of the integrators 24 and 25 is
In the waveforms of the non-inverting signal FOUT and the inverting signal / FOUT, the output voltage V
Duty increases. Then, the charge is discharged during the low level period, and the output voltage Vduty falls.

For example, when the output signals of the integrators 24 and 25 are at the same level, the difference between the output signals becomes zero, and the output of the subtracter 26 is at the intermediate potential (half the power supply voltage and half the ground potential). Becomes This indicates that the duty value of the waveform of the signal output from the VCO is 50%. If the duty value of the output signal waveform deviates from 50%, the high-level time in the signal waveform of the non-inverted signal FOUT and the inverted signal / FOUT of the output signal of the VCO differs.

As a result, a potential difference occurs between the output signals of the integrators 24 and 25 for inputting these signals.

Since the output of the subtracter 26 is this potential difference, the output of the subtracter 26 shifts from the intermediate potential to the power supply voltage side or to the ground potential side. Therefore, subtracter 2
By measuring how much the output voltage 6 is shifted from the intermediate potential, it is possible to estimate how much the duty value deviates from 50%.

According to the present embodiment, a test circuit for outputting a differential voltage of an integrated voltage obtained by integrating the non-inverted signal FOUT and the inverted signal / FOUT of the output signal of the VCO is integrated with a PLL circuit. By simply mounting the circuit on the circuit and measuring the differential voltage, it is possible to easily and inexpensively detect that the duty value of the output signal of the PLL circuit deviates from 50%. And so on.

FIG. 8 is a block diagram showing a second embodiment of a test circuit for measuring a basic duty value mounted on an integrated circuit of the present invention. The test circuit according to the present embodiment includes an integrator 27 for integrating the non-inverted signal Fout of the output signal of the PLL circuit, an integrator 28 for integrating the inverted signal / Fout of the output signal, and a difference between the integrated values of the integrators 27 and 28. , A reference voltage generation circuit 30 that generates a reference voltage (VRH) higher than a certain fixed potential and a reference voltage (VRL) lower than a certain fixed potential, and a difference output from the subtractor 29. Voltage and high reference voltage (VR
H), a voltage comparator 32 for comparing the difference voltage output from the subtractor 29 with a low reference voltage (VRL), and an OR circuit for taking the logical sum of the outputs of the voltage comparators 31 and 32. 33.

Next, the operation of this embodiment will be described. The integrators 27 and 28 receive the non-inverted signal Fout and the inverted signal / Fout of the output signal of the PLL circuit, integrate the respective signals, and output the obtained integrated voltages to the subtractor 29. The subtracter 29 calculates the difference between the input integrated voltages, and outputs the obtained difference voltage Vduty to the voltage comparators 31 and 32.

The voltage comparator 31 calculates the input differential voltage,
A reference voltage (VRH) higher than a certain intermediate potential is compared, and the result is output through an OR circuit 33. The voltage comparator 32 compares the input difference voltage with a reference voltage (VRL) lower than a certain intermediate potential, and outputs the result through an OR circuit 33.

Here, the voltage comparator 31 for comparing the potential difference between the output of the subtractor 29 and the high reference voltage (VRH) outputs a high-level signal when the output of the subtractor 29 becomes higher than the reference voltage (VRH). Is output, and when it becomes low,
Outputs a low-level signal. Then, the voltage comparator 32 that compares the potential difference between the output of the subtractor 29 and the low reference voltage (VRL) outputs a high-level signal when the output of the subtractor 29 becomes lower than the reference voltage (VRL), On the other hand, when it becomes high, it outputs a low level signal.

Therefore, when the duty value is 50%, the output of the subtractor 29 is at the intermediate potential, and the outputs of the two voltage comparators 31 and 32 both output low-level binary signals. . Further, the OR circuit 33 that inputs the outputs of the two voltage comparators 31 and 32 also outputs a low-level signal.

When the duty value deviates from 50%, the output of the subtractor 29 also deviates from the intermediate potential, so that it becomes higher than the high reference voltage (VRH) or lower than the low reference voltage (VRL). Therefore, one of the outputs of the two voltage comparators 31 and 32 outputs a high-level binary signal. Furthermore, two voltage comparators 3
The OR circuit 33 that inputs the outputs of the signals 1 and 32 also outputs a high-level binary signal.

As a result, the output of the OR circuit 33 becomes
By measuring the low level output or the high level output, it is determined whether the deviation of the duty value of the PLL circuit from 50% is small or large. That is, it is possible to easily determine whether the PLL circuit and the integrated circuit on which the test circuit is mounted are non-defective or defective.

According to the present embodiment, whether the PLL circuit mounted on the integrated circuit is good or defective can be notified by a binary output, and the duty cycle can be easily and quickly performed without the need for an external measuring device. A lot with a large deviation from 50% of the value can be detected.

Further, by incorporating a test circuit for measuring the jitter value of the PLL circuit on the LSI chip, although the chip cost is slightly increased by the additional circuit, the measurement time is shortened and the cost of an expensive measuring instrument is reduced. Since this can be eliminated, the test cost can be significantly reduced.

FIG. 9 is a circuit diagram showing a first embodiment of the integrator used in the circuits of FIGS. A constant current source 34 having one connected to the power supply voltage, and a normal signal FO of the output signal of the VCO inserted between the constant current source 34 and the output terminal.
A storage switch circuit 35 controlled by the UT or the inverted signal / FOUT, a discharge resistor 36 connected between the output terminal and the ground potential, and a discharge resistor 36 connected between the output terminal and the ground potential. And a capacitor 37.

FIG. 10 is a circuit diagram showing a second embodiment of the integrator used in the circuits of FIGS. A constant current source 38 having one connected to the power supply voltage, and a non-inverting signal F of the output signal of the VCO inserted between the constant current source 38 and the output terminal.
A storage switch circuit 39 controlled by OUT or an inverted signal / FOUT; an inverter circuit 40 for inverting a control signal for controlling the storage switch circuit 39; a constant current source 42 having one connected to the ground potential; A discharge switch circuit 41 inserted between the current source 42 and the output terminal and controlled by an inverted signal of a control signal for controlling the storage switch circuit 39; and a capacitor connected between the output terminal and the ground potential And an element 43.

Here, the storage switch circuit 39 is connected to the PMO
The discharge switch circuit 41 is composed of N transistors.
When a MOS transistor is used, the storage switch circuit 39 and the discharge switch circuit 41 can be controlled by the same control signal because the polarity of the transistor is different. Therefore, the control signal is inverted in FIG. The inverter circuit 40 becomes unnecessary.

FIG. 11 is a circuit diagram showing a third embodiment of the integrator used in the circuits of FIGS. Forward signal FOUT of the output signal of the VCO or inverted signal / FOU
A storage switch circuit 44 controlled by T, one of which is connected to a power supply voltage, an inverter circuit 46 for inverting a control signal for controlling the storage switch circuit 44, and an inverted signal of a control signal for controlling the storage switch circuit 44 One is connected to the ground potential, and the other is connected to the storage switch circuit 44.
, A resistor element 48 connected between a common connection terminal and an output terminal of the storage switch circuit 44 and the discharge switch circuit 45, and a resistor element 48 connected between the output terminal and the ground potential. And a capacitive element 47 connected thereto.

Here, the storage switch circuit 44 is connected to the PMO
An S transistor, and the discharging switch circuit 45
In the case of using MOS transistors, the storage switch circuit 44 and the discharge switch circuit 45 can be controlled by the same control signal because the transistors have different polarities. Therefore, the inverter circuit 46 in FIG. 11 for inverting the control signal becomes unnecessary.

FIG. 12 is a circuit diagram showing one embodiment of the subtractor used in the circuits of FIGS. An input resistance element R1, two feedback resistance elements R2, and an operational amplifier 55
And a capacitive element 5 inserted in parallel with each feedback resistance element R2.
1 and 52. Since the amplification degree of the subtractor 55 can be adjusted by the ratio R2 / R1 of the ratio of the resistance elements R1 and R2, the subtracter 5 can adjust the deviation of the duty value of the PLL circuit.
The amount of change in the output voltage of No. 5, ie, the sensitivity, can be made variable.

The capacitive element 51 inserted in parallel with one feedback resistance element R2 is for removing a harmonic noise component from the output of the subtractor 55, and is inserted in parallel with the other feedback resistance element R2. The capacitance element 52 removes a noise component from the input and stabilizes its potential.
The difference between the voltages input from the terminals VAM and VAS is
Output from OUT.

FIG. 13 is a block diagram showing a first embodiment of the lot selection system according to the present invention. The lot selection system according to the present embodiment includes a PL mounted on an integrated circuit to be selected.
A reference signal Fref of an L circuit (not shown) and a signal Fvar obtained by dividing the output frequency of the VCO, and a phase error generating circuit 9 for generating a phase error signal Esig from a phase error between the two; and a generated phase error signal Integrator 10 that integrates Esig to generate integrated voltage Verr of phase error
And a voltage comparator 11 which receives the integrated voltage Verr of the phase error and the reference voltage Vref to determine the magnitude of the voltage value of both.
And a reference voltage generation circuit 12 that generates a reference voltage Vref and supplies the reference voltage Vref to the voltage comparator 11, a tester 61 including a computer or the like that tests an integrated circuit to be sorted, and a lot (integrated circuit) )
And a lot sorter 62 that sorts the pieces. Here, the phase error generation circuit 9, the integrator 10, the voltage comparator 11 and the reference voltage generation circuit 12 are test circuits for testing jitter, and are mounted on the integrated circuit 100 to be sorted.

The tester 61 uses the integrated circuit (L
When the SI chip 100 is set to the test mode and the jitter value of the mounted PLL circuit is tested, the result is converted into a binary output from the test circuit and input to the tester 61. When the binary output is high and indicates a defective product, the tester 61 sends the integrated circuit 1 to the lot sorter 62.
00 is output at a low level to indicate a non-defective product.
A control signal for selecting 00 to be shipped is output. As a result, the lot sorter 62 sorts out the integrated circuits so as to remove defective products and ship only non-defective products.

According to the present embodiment, the test circuit which measures the jitter value of the PLL circuit and indicates the good or bad
Built-in chip, it is possible to build an automatic sorting system with an extremely simple configuration that sorts good and bad products according to the magnitude of the jitter value, dramatically improving the productivity and quality control of integrated circuits. Can be improved.

As a test circuit, the PL shown in FIG.
A system for automatically selecting an integrated circuit equipped with a circuit for detecting a shift in the duty value of the L circuit can be configured as shown in FIG. 14 and has the same operation and effect.

[0072]

As described above in detail, according to the first to third aspects of the present invention, the jitter value of the PLL circuit is measured and the non-defective product is easily discriminated without increasing the test cost. can do.

According to the fourth or fifth aspect of the invention, the deviation of the duty value of the PLL circuit can be easily measured,
Further, it is possible to easily discriminate a non-defective product having a small deviation from 50% of the duty value of the PLL circuit from a defective product having a large deviation.

According to the invention of claim 6 or 7, a good product and a bad product of the integrated circuit on which the PLL circuit is mounted can be quickly and automatically selected.

[Brief description of the drawings]

FIG. 1 shows a first example of a test circuit mounted on an integrated circuit of the present invention.
FIG. 2 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a first embodiment of the phase error generation circuit shown in FIG. 1 and a waveform diagram showing operation timing waveforms.

FIG. 3 is a circuit diagram showing a configuration of a second embodiment of the phase error generation circuit shown in FIG. 1 and a waveform diagram showing operation timings.

FIG. 4 is a circuit diagram showing a first embodiment of the integrator shown in FIG. 1;

FIG. 5 is a circuit diagram showing a second embodiment of the integrator shown in FIG. 1;

FIG. 6 is a waveform chart for explaining the operation of the integrator shown in FIG.

FIG. 7 is a block diagram showing a first embodiment of a test circuit for measuring a basic duty value mounted on the integrated circuit of the present invention.

FIG. 8 is a block diagram showing a second embodiment of a test circuit for measuring a basic duty value mounted on an integrated circuit of the present invention.

FIG. 9 is a circuit diagram showing a first embodiment of an integrator used in the circuits of FIGS. 7 and 8;

FIG. 10 shows a second example of the integrator used in the circuits of FIGS. 7 and 8;
FIG. 2 is a circuit diagram showing an example of the embodiment.

FIG. 11 shows a third example of the integrator used in the circuits of FIGS. 7 and 8;
FIG. 2 is a circuit diagram showing an example of the embodiment.

FIG. 12 is a circuit diagram showing one embodiment of a subtractor used in the circuits of FIGS. 7 and 8;

FIG. 13 is a block diagram showing a first embodiment of the lot selection system of the present invention.

FIG. 14 is a block diagram showing a second embodiment of the lot selection system of the present invention.

FIG. 15 is a block diagram showing a configuration example of a basic PLL circuit.

[Description of Signs] 9 Phase error generation circuit 10, 24, 25, 27, 28 Integrator 11, 31, 32 Voltage comparator 12, 30 Reference voltage generation circuit 13 Phase comparator 14, 33 Logical OR circuit (OR circuit) 15, 16 1/2 frequency divider 17 Exclusive OR circuit (EX-OR circuit) 26, 29 Subtractor 30 Reference voltage generator 55 Operational amplifier 61 Tester 62 Lot sorter 100 Integrated circuit

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2G032 AC03 AD04 AE07 AE08 AG01 5F038 BB01 DF01 DF14 DT10 DT11 EZ20 5J106 AA04 CC01 CC24 CC27 CC52 DD02 DD06 DD13 DD32 DD34 KK32 9A001 BB05 KK31 KK54 LL05

Claims (7)

[Claims] 1. A phase error generation circuit for inputting a signal obtained by dividing the oscillation signal of a voltage controlled oscillator and a reference signal and detecting a phase error signal of the two, and integrating an error signal output by the phase error generation circuit An integration circuit that generates a predetermined reference voltage; and a voltage comparison circuit that compares an integration result voltage output from the integration circuit with a reference voltage generated by the reference voltage generation circuit. An integrated circuit, comprising: 2. The phase error generating circuit according to claim 1, further comprising a logical sum circuit that inputs a DOWN signal and an UP signal generated by a phase comparator used inside the PLL circuit and takes a logical sum of the two signals. The integrated circuit according to claim 1, wherein 3. The phase error generating circuit according to claim 1, wherein the first frequency dividing circuit divides a signal obtained by dividing the oscillation signal of the voltage controlled oscillator, and the second frequency dividing circuit divides the frequency by inputting a reference signal. 2. The integrated circuit according to claim 1, further comprising: an exclusive-OR circuit for performing an exclusive-OR operation on the divided signals output from the first and second frequency dividing circuits. 4. A first integration circuit for inputting and integrating a non-inverted signal of an oscillation signal of a voltage controlled oscillator; a second integration circuit for receiving and integrating an inverted signal of the oscillation signal; And a subtraction circuit for taking a difference between the integration result voltages output from the second integration circuit. 5. A first integration circuit for inputting and integrating a non-inverted signal of an oscillation signal of a voltage controlled oscillator; a second integration circuit for receiving and integrating an inverted signal of the oscillation signal; A subtraction circuit for obtaining a difference between the integration result voltages output from the second integration circuit, a reference voltage generation circuit for generating a reference voltage higher and lower than a predetermined intermediate potential, and a difference output from the subtraction circuit A first voltage comparison circuit that compares a voltage with a high reference voltage generated by the reference voltage generation circuit; and compares a difference voltage output from the subtraction circuit with a low reference voltage generated by the reference voltage generation circuit. An integrated circuit, comprising: a second voltage comparison circuit; and a logical sum circuit that performs a logical sum of comparison results output from the first and second voltage comparison circuits. 6. A phase error generation circuit for inputting a signal obtained by dividing the oscillation signal of a voltage controlled oscillator and a reference signal and detecting a phase error signal of the two, and integrating an error signal output by the phase error generation circuit An integration circuit that generates a predetermined reference voltage; a voltage comparison circuit that compares an integration result voltage output from the integration circuit with a reference voltage generated by the reference voltage generation circuit; A judgment circuit for judging good or bad of an LSI chip on which each of the circuits is mounted based on a comparison result output from a comparison circuit; and a lot sorter for sorting the LSI chip based on the judgment result of the judgment circuit A lot sorting system. 7. A first integration circuit for inputting and integrating a non-inverted signal of an oscillation signal of a voltage controlled oscillator; a second integration circuit for receiving and integrating an inverted signal of the oscillation signal; A subtraction circuit for obtaining a difference between the integration result voltages output from the second integration circuit, a reference voltage generation circuit for generating a reference voltage higher and lower than a predetermined intermediate potential, and a difference output from the subtraction circuit A first voltage comparison circuit that compares a voltage with a high reference voltage generated by the reference voltage generation circuit; and compares a difference voltage output from the subtraction circuit with a low reference voltage generated by the reference voltage generation circuit. A second voltage comparison circuit, a logical sum circuit for calculating a logical sum of comparison results output from the first and second voltage comparison circuits, and each of the circuits based on the comparison result output from the logical sum circuit LSI chip Goodness, lots sorting system characterized by comprising a lot sorter for sorting the LSI chip and the determination circuit, the judgment result of the judgment circuit failure.